From 150259e2bada95b53c554a5f712d9b42ca41e88c Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 5 Jul 2019 11:40:02 -0700 Subject: [PATCH] Added write_size to control_logic_r parameters. --- compiler/sram/sram_base.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3477c2e0..821c75d4 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -324,6 +324,7 @@ class sram_base(design, verilog, lef): self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + write_size=self.write_size, sram=self, port_type="r") self.add_mod(self.control_logic_r)