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Added write_size to control_logic_r parameters.

This commit is contained in:
jsowash 2019-07-05 11:40:02 -07:00
parent 02a0cd71ac
commit 150259e2ba
1 changed files with 1 additions and 0 deletions
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compiler/sram/sram_base.py
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@ -324,6 +324,7 @@ class sram_base(design, verilog, lef):
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row, words_per_row=self.words_per_row,
word_size=self.word_size, word_size=self.word_size,
write_size=self.write_size,
sram=self, sram=self,
port_type="r") port_type="r")
self.add_mod(self.control_logic_r) self.add_mod(self.control_logic_r)