From 0c203c1c7ebefdc42f082a44f59b7fb8acc1758a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 5 Mar 2018 10:23:13 -0800 Subject: [PATCH] RBL width is max of delay chain or bitcell load. --- compiler/modules/replica_bitline.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index 394e4c18..b5c2118c 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -70,7 +70,8 @@ class replica_bitline(design.design): self.rbl_offset = self.bitcell_offset - self.height = self.rbl_offset.y + self.rbl.height + self.m2_pitch + self.height = max(self.rbl_offset.y + self.rbl.height + self.m2_pitch, + self.delay_chain_offset.y + self.delay_chain.width + self.m2_pitch) self.width = self.rbl_offset.x + self.bitcell.width