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https://github.com/VLSIDA/OpenRAM.git
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Update unit tests to all use the sram_factory
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@@ -9,18 +9,17 @@ import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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from sram_factory import factory
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import debug
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class precharge_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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import precharge_array
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# check precharge array in single port
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debug.info(2, "Checking 3 column precharge")
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pc = precharge_array.precharge_array(name="pre1", columns=3)
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pc = factory.create(module_type="precharge_array", columns=3)
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self.local_check(pc)
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# check precharge array in multi-port
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@@ -31,7 +30,7 @@ class precharge_test(openram_test):
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factory.reset()
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debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
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pc = precharge_array.precharge_array(name="pre2", columns=3, bitcell_bl="bl0", bitcell_br="br0")
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pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(pc)
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# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
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