mirror of
https://github.com/VLSIDA/OpenRAM.git
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Add new DFF. Create DFF module. Start dff_array, not tested.
This commit is contained in:
Matt Guthaus
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* File: DFFPOSX1.pex.netlist
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* Created: Wed Jan 2 18:36:24 2008
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* Program "Calibre xRC"
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* Version "v2007.2_34.24"
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*
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.subckt dff d clk q vdd gnd
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*
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MM21 q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
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MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM20 gnd q a_76_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM18 a_66_6# clk a_61_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM17 a_61_6# a_34_4# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM10 gnd clk a_2_6# gnd NMOS_VTG L=5e-08 W=5e-07
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MM16 a_34_4# a_22_6# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM15 gnd a_34_4# a_31_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM14 a_31_6# clk a_22_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM13 a_22_6# a_2_6# a_17_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM12 a_17_6# d gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM11 q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06
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MM9 vdd q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07
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MM8 a_76_84# clk a_66_6# vdd PMOS_VTG L=5e-08 W=2.5e-07
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MM7 a_66_6# a_2_6# a_61_74# vdd PMOS_VTG L=5e-08 W=5e-07
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MM6 a_61_74# a_34_4# vdd vdd PMOS_VTG L=5e-08 W=5e-07
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MM0 vdd clk a_2_6# vdd PMOS_VTG L=5e-08 W=1e-06
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MM5 a_34_4# a_22_6# vdd vdd PMOS_VTG L=5e-08 W=5e-07
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MM4 vdd a_34_4# a_31_74# vdd PMOS_VTG L=5e-08 W=5e-07
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MM3 a_31_74# a_2_6# a_22_6# vdd PMOS_VTG L=5e-08 W=5e-07
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MM2 a_22_6# clk a_17_74# vdd PMOS_VTG L=5e-08 W=5e-07
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MM1 a_17_74# d vdd vdd PMOS_VTG L=5e-08 W=5e-07
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* c_9 a_66_6# 0 0.271997f
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* c_20 clk 0 0.350944f
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* c_27 q 0 0.202617f
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* c_32 a_76_84# 0 0.0210573f
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* c_38 a_76_6# 0 0.0204911f
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* c_45 a_34_4# 0 0.172306f
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* c_55 a_2_6# 0 0.283119f
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* c_59 a_22_6# 0 0.157312f
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* c_64 d 0 0.0816386f
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* c_73 gnd 0 0.254131f
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* c_81 vdd 0 0.23624f
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*
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*.include "dff.pex.netlist.dff.pxi"
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*
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.ends
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*
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*
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@@ -274,6 +274,11 @@ spice["msflop_hold"] = 1 # DFF hold time in ps
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spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["msflop_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
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spice["dff_setup"] = 9 # DFF setup time in ps
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spice["dff_hold"] = 1 # DFF hold time in ps
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spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
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###################################################
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magic
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tech scmos
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timestamp 1090351116
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<< nwell >>
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rect -8 48 104 105
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<< ntransistor >>
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rect 7 6 9 26
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rect 15 6 17 16
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rect 20 6 22 16
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rect 29 6 31 16
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rect 59 6 61 16
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rect 64 6 66 16
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rect 74 6 76 16
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rect 79 6 81 16
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rect 87 6 89 26
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<< ptransistor >>
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rect 7 54 9 94
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rect 15 74 17 94
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rect 21 74 23 94
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rect 29 74 31 94
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rect 35 74 37 94
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rect 64 74 66 94
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<< ndiffusion >>
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<< pdiffusion >>
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<< ndcontact >>
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rect 2 6 6 25
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rect 10 6 14 25
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rect 24 6 28 15
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rect 37 6 41 15
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rect 54 6 58 15
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rect 68 6 72 15
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rect 82 6 86 25
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rect 90 6 94 25
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<< pdcontact >>
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rect 2 54 6 93
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rect 10 55 14 94
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rect 24 74 28 93
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rect 38 74 42 93
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rect 54 74 58 93
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rect 68 74 72 93
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rect 82 54 86 93
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rect 90 54 94 93
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<< psubstratepcontact >>
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rect -2 -2 2 2
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rect 14 -2 18 2
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rect 30 -2 34 2
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rect 46 -2 50 2
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rect 62 -2 66 2
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rect 78 -2 82 2
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<< nsubstratencontact >>
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rect -2 98 2 102
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rect 14 98 18 102
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rect 30 98 34 102
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rect 46 98 50 102
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rect 62 98 66 102
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rect 78 98 82 102
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<< polysilicon >>
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rect 7 94 9 96
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rect 15 94 17 96
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rect 21 94 23 96
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rect 29 94 31 96
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rect 87 4 89 6
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<< polycontact >>
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rect 13 42 17 46
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rect 6 33 10 37
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<< metal1 >>
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rect -2 102 98 103
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rect 2 98 14 102
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rect 18 98 30 102
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rect -2 2 98 3
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rect 2 -2 14 2
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rect 18 -2 30 2
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rect 34 -2 46 2
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rect 50 -2 62 2
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rect 66 -2 78 2
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rect 82 -2 98 2
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rect -2 -3 98 -2
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<< m2contact >>
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rect 18 70 22 74
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rect 66 70 70 74
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rect 18 57 22 61
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rect 2 50 6 54
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rect 18 16 22 20
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<< metal2 >>
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rect 18 61 22 70
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rect 2 30 6 50
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rect 18 20 22 57
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rect 66 44 70 70
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rect 66 20 70 40
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<< m1p >>
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rect 34 43 38 47
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rect 90 43 94 47
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rect 10 33 14 37
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<< labels >>
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<< end >>
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@@ -0,0 +1,47 @@
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* Positive edge-triggered FF
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.subckt dff d q clk vdd gnd
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M0 vdd clk a_2_6# vdd p w=12u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M1 a_17_74# d vdd vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M9 vdd q a_76_84# vdd p w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M10 gnd clk a_2_6# gnd n w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M11 q a_66_6# vdd vdd p w=12u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M12 a_17_6# d gnd gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M20 gnd q a_76_6# gnd n w=3u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M21 q a_66_6# gnd gnd n w=6u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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.ends dff
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@@ -238,6 +238,11 @@ spice["msflop_hold"] = 1 # DFF hold time in ps
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spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
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spice["dff_setup"] = 9 # DFF setup time in ps
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spice["dff_hold"] = 1 # DFF hold time in ps
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spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
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###################################################
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