From 0804a1eceb1d9a5e8bbb92de9b41ad6243736a32 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 14 Feb 2018 15:16:28 -0800 Subject: [PATCH] Add new DFF. Create DFF module. Start dff_array, not tested. --- compiler/modules/dff.py | 29 +++ compiler/modules/dff_array.py | 138 ++++++++++++ compiler/options.py | 2 + compiler/tests/11_dff_array_test.py | 40 ++++ technology/freepdk45/gds_lib/dff.gds | Bin 0 -> 22528 bytes technology/freepdk45/sp_lib/dff.sp | 46 ++++ technology/freepdk45/tech/tech.py | 5 + technology/scn3me_subm/gds_lib/dff.gds | Bin 0 -> 18432 bytes technology/scn3me_subm/mag_lib/dff.mag | 293 +++++++++++++++++++++++++ technology/scn3me_subm/sp_lib/dff.sp | 47 ++++ technology/scn3me_subm/tech/tech.py | 5 + 11 files changed, 605 insertions(+) create mode 100644 compiler/modules/dff.py create mode 100644 compiler/modules/dff_array.py create mode 100644 compiler/tests/11_dff_array_test.py create mode 100644 technology/freepdk45/gds_lib/dff.gds create mode 100644 technology/freepdk45/sp_lib/dff.sp create mode 100644 technology/scn3me_subm/gds_lib/dff.gds create mode 100644 technology/scn3me_subm/mag_lib/dff.mag create mode 100644 technology/scn3me_subm/sp_lib/dff.sp diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py new file mode 100644 index 00000000..2a5c459b --- /dev/null +++ b/compiler/modules/dff.py @@ -0,0 +1,29 @@ +import globals +import design +from math import log +import design +from tech import GDS,layer +import utils + +class dff(design.design): + """ + Memory address flip-flop + """ + + pin_names = ["d", "clk", "q", "vdd", "gnd"] + (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"]) + + def __init__(self, name="dff"): + design.design.__init__(self, name) + + self.width = dff.width + self.height = dff.height + self.pin_map = dff.pin_map + + def analytical_delay(self, slew, load = 0.0): + # dont know how to calculate this now, use constant in tech file + from tech import spice + result = self.return_delay(spice["dff_delay"], spice["dff_slew"]) + return result + diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py new file mode 100644 index 00000000..831d9db4 --- /dev/null +++ b/compiler/modules/dff_array.py @@ -0,0 +1,138 @@ +import debug +import design +from tech import drc +from math import log +from vector import vector +from globals import OPTS + +class dff_array(design.design): + """ + This is a simple row (or multiple rows) of flops. + Unlike the data flops, these are never spaced out. + """ + + def __init__(self, rows, columns, name=""): + self.rows = rows + self.columns = columns + + if name=="": + name = "dff_array_c{0}_w{1}".format(columns,word_size) + design.design.__init__(self, name) + debug.info(1, "Creating {}".format(self.name)) + + c = reload(__import__(OPTS.dff)) + self.mod_dff = getattr(c, OPTS.dff) + self.ms = self.mod_dff("dff") + self.add_mod(self.ms) + + self.width = self.columns * self.ms.width + self.height = self.rows * self.ms.height + + self.create_layout() + + def create_layout(self): + self.add_pins() + self.create_dff_array() + self.add_layout_pins() + self.DRC_LVS() + + def add_pins(self): + for row in range(self.rows): + for col in range(self.columns): + self.add_pin("din[{0}][{1}]".format(row,col)) + for row in range(self.rows): + for col in range(self.columns): + self.add_pin("dout[{0}][{1}]".format(row,col)) + #self.add_pin("dout_bar[{0}]".format(i)) + self.add_pin("clk") + self.add_pin("vdd") + self.add_pin("gnd") + + def create_dff_array(self): + self.ms_inst={} + for row in range(self.rows): + for col in range(self.columns): + name = "Xdff_r{0}_c{1}".format(row,col) + if (row % 2 == 0): + base = vector(i*self.ms.width,0) + mirror = "R0" + else: + base = vector((i+1)*self.ms.width,0) + mirror = "MY" + self.ms_inst[row,col]=self.add_inst(name=name, + mod=self.ms, + offset=base, + mirror=mirror) + self.connect_inst(["din[{0}][{1}]".format(row,col), + "dout[{0}][{1}]".format(row,col), + "clk", + "vdd", + "gnd"]) + + def add_layout_pins(self): + + for i in range(self.word_size): + + for gnd_pin in self.ms_inst[i].get_pins("gnd"): + if gnd_pin.layer!="metal2": + continue + self.add_layout_pin(text="gnd", + layer="metal2", + offset=gnd_pin.ll(), + width=gnd_pin.width(), + height=gnd_pin.height()) + + din_pins = self.ms_inst[i].get_pins("din") + for din_pin in din_pins: + self.add_layout_pin(text="din[{}]".format(i), + layer=din_pin.layer, + offset=din_pin.ll(), + width=din_pin.width(), + height=din_pin.height()) + + dout_pin = self.ms_inst[i].get_pin("dout") + self.add_layout_pin(text="dout[{}]".format(i), + layer="metal2", + offset=dout_pin.ll(), + width=dout_pin.width(), + height=dout_pin.height()) + + doutbar_pin = self.ms_inst[i].get_pin("dout_bar") + self.add_layout_pin(text="dout_bar[{}]".format(i), + layer="metal2", + offset=doutbar_pin.ll(), + width=doutbar_pin.width(), + height=doutbar_pin.height()) + + + # Continous clk rail along with label. + self.add_layout_pin(text="clk", + layer="metal1", + offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1), + width=self.width, + height=drc["minwidth_metal1"]) + + + # Continous vdd rail along with label. + for vdd_pin in self.ms_inst[i].get_pins("vdd"): + if vdd_pin.layer!="metal1": + continue + self.add_layout_pin(text="vdd", + layer="metal1", + offset=vdd_pin.ll().scale(0,1), + width=self.width, + height=drc["minwidth_metal1"]) + + # Continous gnd rail along with label. + for gnd_pin in self.ms_inst[i].get_pins("gnd"): + if gnd_pin.layer!="metal1": + continue + self.add_layout_pin(text="gnd", + layer="metal1", + offset=gnd_pin.ll().scale(0,1), + width=self.width, + height=drc["minwidth_metal1"]) + + + def analytical_delay(self, slew, load=0.0): + return self.ms.analytical_delay(slew=slew, load=load) diff --git a/compiler/options.py b/compiler/options.py index d6414b6c..1899d085 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -58,6 +58,8 @@ class options(optparse.Values): decoder = "hierarchical_decoder" ms_flop = "ms_flop" ms_flop_array = "ms_flop_array" + dff = "dff" + dff_array = "dff_array" control_logic = "control_logic" bitcell_array = "bitcell_array" sense_amp = "sense_amp" diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py new file mode 100644 index 00000000..89b374c4 --- /dev/null +++ b/compiler/tests/11_dff_array_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python2.7 +""" +Run a regresion test on a dff_array. +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +class dff_array_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + global verify + import verify + OPTS.check_lvsdrc = False + + import dff_array + + debug.info(2, "Testing dff_array for columns=8, word_size=8") + a = dff_array.dff_array(columns=8, word_size=8) + self.local_check(a) + + debug.info(2, "Testing dff_array for columns=16, word_size=8") + a = dff_array.dff_array(columns=16, word_size=8) + self.local_check(a) + + OPTS.check_lvsdrc = True + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/technology/freepdk45/gds_lib/dff.gds b/technology/freepdk45/gds_lib/dff.gds new file mode 100644 index 0000000000000000000000000000000000000000..32873c775a87e697ee878608afe2b5d821f13cb7 GIT binary patch literal 22528 zcmeI4d#GjAeaH7buY2y}+{fIRh*eQzt%!Lb63E2ZR7FavQU((wjS?pHfjBk^treTn zV1tN=H9@SIiZv!R(k5a`Xr&bqv1yW;G;PI7n-(h*2&q_Ui?u?fc}t?&A+_hX;6Z#Ag~)ucLpX;AIaZyWL7wEq3Q)!VA|!Q_f7uR3`Bp$!S%!`~f8_u6#njKh)56v8b=E zk>+RQQ=EQZe4(N3V(8cF{J)L-PmWpQ|3Ah5*N+?j+_8rbe^I|y>y&Hyr^@%&tLd?m ztAFJR<(>S$5q9PT_F-u(Tg-Nchg_f^+wCv#b!H(!=MbK~}^+PX<~l)1T?{FxhTDSdP6TPb~W{XbP-rz*dh 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W=2.5e-07 +MM17 a_61_6# a_34_4# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07 +MM10 gnd clk a_2_6# gnd NMOS_VTG L=5e-08 W=5e-07 +MM16 a_34_4# a_22_6# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07 +MM15 gnd a_34_4# a_31_6# gnd NMOS_VTG L=5e-08 W=2.5e-07 +MM14 a_31_6# clk a_22_6# gnd NMOS_VTG L=5e-08 W=2.5e-07 +MM13 a_22_6# a_2_6# a_17_6# gnd NMOS_VTG L=5e-08 W=2.5e-07 +MM12 a_17_6# d gnd gnd NMOS_VTG L=5e-08 W=2.5e-07 +MM11 q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06 +MM9 vdd q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07 +MM8 a_76_84# clk a_66_6# vdd PMOS_VTG L=5e-08 W=2.5e-07 +MM7 a_66_6# a_2_6# a_61_74# vdd PMOS_VTG L=5e-08 W=5e-07 +MM6 a_61_74# a_34_4# vdd vdd PMOS_VTG L=5e-08 W=5e-07 +MM0 vdd clk a_2_6# vdd PMOS_VTG L=5e-08 W=1e-06 +MM5 a_34_4# a_22_6# vdd vdd PMOS_VTG L=5e-08 W=5e-07 +MM4 vdd a_34_4# a_31_74# vdd PMOS_VTG L=5e-08 W=5e-07 +MM3 a_31_74# a_2_6# a_22_6# vdd PMOS_VTG L=5e-08 W=5e-07 +MM2 a_22_6# clk a_17_74# vdd PMOS_VTG L=5e-08 W=5e-07 +MM1 a_17_74# d vdd vdd PMOS_VTG L=5e-08 W=5e-07 +* c_9 a_66_6# 0 0.271997f +* c_20 clk 0 0.350944f +* c_27 q 0 0.202617f +* c_32 a_76_84# 0 0.0210573f +* c_38 a_76_6# 0 0.0204911f +* c_45 a_34_4# 0 0.172306f +* c_55 a_2_6# 0 0.283119f +* c_59 a_22_6# 0 0.157312f +* c_64 d 0 0.0816386f +* c_73 gnd 0 0.254131f +* c_81 vdd 0 0.23624f +* +*.include "dff.pex.netlist.dff.pxi" +* +.ends +* +* diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index dacc3644..e75f4994 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -274,6 +274,11 @@ spice["msflop_hold"] = 1 # DFF hold time in ps spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load spice["msflop_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad] +spice["dff_setup"] = 9 # DFF setup time in ps +spice["dff_hold"] = 1 # DFF hold time in ps +spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad] ################################################### diff --git a/technology/scn3me_subm/gds_lib/dff.gds b/technology/scn3me_subm/gds_lib/dff.gds new file mode 100644 index 0000000000000000000000000000000000000000..407a629205832540bb2c9e0ec56598b0b47a1765 GIT binary patch literal 18432 zcmeI(zpv#*8OQNqSuPu0*JW98A&6@rin1sQ1W=-^B0@w(#NTLET@jU#ivh$)L1BT3 zg$0F)7F(ETK|x_bVX=iV6c!c~78Vv3TToaSVC<3znA&%!NccQz;mrVc3nGg>DJ??PuKsw=zsK-zdYY~_n@_ZMVO_xE zzi;i~t5=L(-0kNp`A;3|`S4A5w|4r46}4x%KJ3{e4C4U#<`RH=gV5NB;NzWJT>?t`Gg!+~4yf|GRHqQU2xn z(0}>yo*(tsJq+bvt`GfhIM(A)e*VzwEZ2wrj61$@yR~~OXXtg7>qCFW4KKO9wObxq zk$<^9^uK+7kH<@2=>E{_E!U@h@!~G~Yirm3YQ^Zqq5p~}dVb`;^6C}kU#<`R8Fw^p za)$c9Tp#*B`{&l){PWh(y}SRJ6{8oYem?%I?(6eEj9wi2tsCO;=G(eIj9wi2Z+o=0 zw?5k%zU>dKefX*sqZfyMeKhXKZ~VjP#i9ST&-eLqGy(&-M9-a+`CZ ze=paEelhxq+AV(=eb)c@&|2}4Cs*`3%k^P?^Yfj5>htuvgMI#n(Th{Rc&~H)k6ZiN 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zJ@38uM&Cj8-HkAMap*sJrq3VL2j86w&7bA^(66o54m4i&Y+>}`&~M!3L3xdT7=2^@ z?iqjYan%Vr!}#j*4ZQo`uPp> +rect -8 48 104 105 +<< ntransistor >> +rect 7 6 9 26 +rect 15 6 17 16 +rect 20 6 22 16 +rect 29 6 31 16 +rect 34 6 36 16 +rect 43 6 45 16 +rect 59 6 61 16 +rect 64 6 66 16 +rect 74 6 76 16 +rect 79 6 81 16 +rect 87 6 89 26 +<< ptransistor >> +rect 7 54 9 94 +rect 15 74 17 94 +rect 21 74 23 94 +rect 29 74 31 94 +rect 35 74 37 94 +rect 43 74 45 94 +rect 59 74 61 94 +rect 64 74 66 94 +rect 74 84 76 94 +rect 79 84 81 94 +rect 87 54 89 94 +<< ndiffusion >> +rect 2 25 7 26 +rect 6 6 7 25 +rect 9 25 14 26 +rect 9 6 10 25 +rect 82 25 87 26 +rect 14 6 15 16 +rect 17 6 20 16 +rect 22 15 29 16 +rect 22 6 24 15 +rect 28 6 29 15 +rect 31 6 34 16 +rect 36 15 43 16 +rect 36 6 37 15 +rect 41 6 43 15 +rect 45 15 50 16 +rect 45 6 46 15 +rect 54 15 59 16 +rect 58 6 59 15 +rect 61 6 64 16 +rect 66 15 74 16 +rect 66 6 68 15 +rect 72 6 74 15 +rect 76 6 79 16 +rect 81 6 82 16 +rect 86 6 87 25 +rect 89 25 94 26 +rect 89 6 90 25 +<< pdiffusion >> +rect 2 93 7 94 +rect 6 54 7 93 +rect 9 55 10 94 +rect 14 74 15 94 +rect 17 74 21 94 +rect 23 93 29 94 +rect 23 74 24 93 +rect 28 74 29 93 +rect 31 74 35 94 +rect 37 93 43 94 +rect 37 74 38 93 +rect 42 74 43 93 +rect 45 93 50 94 +rect 45 74 46 93 +rect 54 93 59 94 +rect 58 74 59 93 +rect 61 74 64 94 +rect 66 93 74 94 +rect 66 74 68 93 +rect 72 84 74 93 +rect 76 84 79 94 +rect 81 93 87 94 +rect 81 84 82 93 +rect 72 74 73 84 +rect 9 54 14 55 +rect 86 54 87 93 +rect 89 93 94 94 +rect 89 54 90 93 +<< ndcontact >> +rect 2 6 6 25 +rect 10 6 14 25 +rect 24 6 28 15 +rect 37 6 41 15 +rect 46 6 50 15 +rect 54 6 58 15 +rect 68 6 72 15 +rect 82 6 86 25 +rect 90 6 94 25 +<< pdcontact >> +rect 2 54 6 93 +rect 10 55 14 94 +rect 24 74 28 93 +rect 38 74 42 93 +rect 46 74 50 93 +rect 54 74 58 93 +rect 68 74 72 93 +rect 82 54 86 93 +rect 90 54 94 93 +<< psubstratepcontact >> +rect -2 -2 2 2 +rect 14 -2 18 2 +rect 30 -2 34 2 +rect 46 -2 50 2 +rect 62 -2 66 2 +rect 78 -2 82 2 +<< nsubstratencontact >> +rect -2 98 2 102 +rect 14 98 18 102 +rect 30 98 34 102 +rect 46 98 50 102 +rect 62 98 66 102 +rect 78 98 82 102 +<< polysilicon >> +rect 7 94 9 96 +rect 15 94 17 96 +rect 21 94 23 96 +rect 29 94 31 96 +rect 35 94 37 96 +rect 43 94 45 96 +rect 59 94 61 96 +rect 64 94 66 96 +rect 74 94 76 96 +rect 79 94 81 96 +rect 87 94 89 96 +rect 7 37 9 54 +rect 15 46 17 74 +rect 7 26 9 33 +rect 15 16 17 42 +rect 21 38 23 74 +rect 29 54 31 74 +rect 29 29 31 50 +rect 20 27 31 29 +rect 35 71 37 74 +rect 20 16 22 27 +rect 35 23 37 67 +rect 43 61 45 74 +rect 59 73 61 74 +rect 50 71 61 73 +rect 30 19 31 23 +rect 29 16 31 19 +rect 34 19 35 23 +rect 34 16 36 19 +rect 43 16 45 57 +rect 49 19 51 67 +rect 64 63 66 74 +rect 74 67 76 84 +rect 72 65 76 67 +rect 59 61 66 63 +rect 57 24 59 33 +rect 64 31 66 61 +rect 79 53 81 84 +rect 75 51 81 53 +rect 74 31 76 47 +rect 87 45 89 54 +rect 85 41 89 45 +rect 64 29 71 31 +rect 57 22 66 24 +rect 49 17 61 19 +rect 59 16 61 17 +rect 64 16 66 22 +rect 69 19 71 29 +rect 74 27 75 31 +rect 69 17 76 19 +rect 74 16 76 17 +rect 79 16 81 31 +rect 87 26 89 41 +rect 7 4 9 6 +rect 15 4 17 6 +rect 20 4 22 6 +rect 29 4 31 6 +rect 34 4 36 6 +rect 43 4 45 6 +rect 59 4 61 6 +rect 64 4 66 6 +rect 74 4 76 6 +rect 79 4 81 6 +rect 87 4 89 6 +<< polycontact >> +rect 13 42 17 46 +rect 6 33 10 37 +rect 27 50 31 54 +rect 21 34 25 38 +rect 35 67 39 71 +rect 41 57 45 61 +rect 26 19 30 23 +rect 35 19 39 23 +rect 49 67 53 71 +rect 55 59 59 63 +rect 70 61 74 65 +rect 55 33 59 37 +rect 73 47 77 51 +rect 81 41 85 45 +rect 75 27 79 31 +<< metal1 >> +rect -2 102 98 103 +rect 2 98 14 102 +rect 18 98 30 102 +rect 34 98 46 102 +rect 50 98 62 102 +rect 66 98 78 102 +rect 82 98 98 102 +rect -2 97 98 98 +rect 10 94 14 97 +rect 2 93 6 94 +rect 24 93 28 94 +rect 18 74 24 77 +rect 38 93 42 97 +rect 46 93 50 94 +rect 54 93 58 97 +rect 67 93 73 94 +rect 67 74 68 93 +rect 72 74 73 93 +rect 82 93 86 97 +rect 46 71 49 74 +rect 39 68 49 71 +rect 22 57 41 60 +rect 48 60 55 63 +rect 48 54 51 60 +rect 67 56 70 65 +rect 6 50 27 52 +rect 31 51 51 54 +rect 58 53 70 56 +rect 90 93 94 94 +rect 2 49 30 50 +rect 34 46 38 47 +rect 17 43 38 46 +rect 10 34 21 37 +rect 58 37 61 53 +rect 90 51 94 54 +rect 77 48 94 51 +rect 70 41 81 44 +rect 25 34 55 37 +rect 10 33 14 34 +rect 2 25 6 26 +rect 10 25 14 26 +rect 27 23 30 34 +rect 59 34 61 37 +rect 90 31 94 48 +rect 79 28 94 31 +rect 90 25 94 28 +rect 39 19 49 22 +rect 46 16 49 19 +rect 18 15 28 16 +rect 18 13 24 15 +rect 37 15 42 16 +rect 41 6 42 15 +rect 46 15 50 16 +rect 54 15 58 16 +rect 66 15 73 16 +rect 66 13 68 15 +rect 67 6 68 13 +rect 72 6 73 15 +rect 10 3 14 6 +rect 37 3 42 6 +rect 54 3 58 6 +rect 82 3 86 6 +rect -2 2 98 3 +rect 2 -2 14 2 +rect 18 -2 30 2 +rect 34 -2 46 2 +rect 50 -2 62 2 +rect 66 -2 78 2 +rect 82 -2 98 2 +rect -2 -3 98 -2 +<< m2contact >> +rect 18 70 22 74 +rect 66 70 70 74 +rect 18 57 22 61 +rect 2 50 6 54 +rect 66 40 70 44 +rect 2 26 6 30 +rect 18 16 22 20 +rect 66 16 70 20 +<< metal2 >> +rect 18 61 22 70 +rect 2 30 6 50 +rect 18 20 22 57 +rect 66 44 70 70 +rect 66 20 70 40 +<< m1p >> +rect 34 43 38 47 +rect 90 43 94 47 +rect 10 33 14 37 +<< labels >> +<< end >> diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp new file mode 100644 index 00000000..6d57e652 --- /dev/null +++ b/technology/scn3me_subm/sp_lib/dff.sp @@ -0,0 +1,47 @@ +* Positive edge-triggered FF +.subckt dff d q clk vdd gnd +M0 vdd clk a_2_6# vdd p w=12u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M1 a_17_74# d vdd vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M9 vdd q a_76_84# vdd p w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M10 gnd clk a_2_6# gnd n w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M11 q a_66_6# vdd vdd p w=12u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M12 a_17_6# d gnd gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M20 gnd q a_76_6# gnd n w=3u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +M21 q a_66_6# gnd gnd n w=6u l=0.6u ++ ad=0p pd=0u as=0p ps=0u +.ends dff diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index b8270578..f7f476c7 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -238,6 +238,11 @@ spice["msflop_hold"] = 1 # DFF hold time in ps spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] +spice["dff_setup"] = 9 # DFF setup time in ps +spice["dff_hold"] = 1 # DFF hold time in ps +spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] ###################################################