From 0354e2dfb73bbc247fec7a0a4dd1b63ce03580b5 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 8 Mar 2019 10:47:41 -0800 Subject: [PATCH] Rename config_20 to config since it is used in all tests --- compiler/tests/01_library_drc_test.py | 2 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/03_contact_test.py | 2 +- compiler/tests/03_path_test.py | 2 +- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 2 +- compiler/tests/03_ptx_4finger_nmos_test.py | 2 +- compiler/tests/03_ptx_4finger_pmos_test.py | 2 +- compiler/tests/03_wire_test.py | 2 +- compiler/tests/04_pand2_test.py | 2 +- compiler/tests/04_pbitcell_test.py | 2 +- compiler/tests/04_pbuf_test.py | 2 +- compiler/tests/04_pdriver_test.py | 2 +- compiler/tests/04_pinv_10x_test.py | 2 +- compiler/tests/04_pinv_1x_beta_test.py | 2 +- compiler/tests/04_pinv_1x_test.py | 2 +- compiler/tests/04_pinv_2x_test.py | 2 +- compiler/tests/04_pinvbuf_test.py | 2 +- compiler/tests/04_pnand2_test.py | 2 +- compiler/tests/04_pnand3_test.py | 2 +- compiler/tests/04_pnor2_test.py | 2 +- compiler/tests/04_precharge_test.py | 2 +- compiler/tests/04_replica_pbitcell_test.py | 2 +- compiler/tests/04_single_level_column_mux_test.py | 2 +- compiler/tests/05_bitcell_1rw_1r_array_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/05_pbitcell_array_test.py | 2 +- compiler/tests/06_hierarchical_decoder_test.py | 2 +- compiler/tests/06_hierarchical_predecode2x4_test.py | 2 +- compiler/tests/06_hierarchical_predecode3x8_test.py | 2 +- compiler/tests/07_single_level_column_mux_array_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- compiler/tests/08_wordline_driver_test.py | 2 +- compiler/tests/09_sense_amp_array_test.py | 2 +- compiler/tests/10_write_driver_array_test.py | 2 +- compiler/tests/11_dff_array_test.py | 2 +- compiler/tests/11_dff_buf_array_test.py | 2 +- compiler/tests/11_dff_buf_test.py | 2 +- compiler/tests/12_tri_gate_array_test.py | 2 +- compiler/tests/13_delay_chain_test.py | 2 +- compiler/tests/14_replica_bitline_multiport_test.py | 2 +- compiler/tests/14_replica_bitline_test.py | 2 +- compiler/tests/16_control_logic_test.py | 2 +- compiler/tests/19_bank_select_test.py | 2 +- compiler/tests/19_multi_bank_test.py | 2 +- compiler/tests/19_pmulti_bank_test.py | 2 +- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_test.py | 2 +- compiler/tests/20_sram_2bank_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 2 +- compiler/tests/21_hspice_setuphold_test.py | 2 +- compiler/tests/21_ngspice_delay_test.py | 2 +- compiler/tests/21_ngspice_setuphold_test.py | 2 +- compiler/tests/22_psram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_8mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_8mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py | 2 +- compiler/tests/23_lib_sram_model_corners_test.py | 2 +- compiler/tests/23_lib_sram_model_test.py | 2 +- compiler/tests/23_lib_sram_prune_test.py | 2 +- compiler/tests/23_lib_sram_test.py | 2 +- compiler/tests/24_lef_sram_test.py | 2 +- compiler/tests/25_verilog_sram_test.py | 2 +- compiler/tests/26_pex_test.py | 2 +- compiler/tests/27_worst_case_delay_test.py | 2 +- compiler/tests/28_delay_model_test.py | 2 +- compiler/tests/30_openram_test.py | 4 ++-- .../tests/{config_20_freepdk45.py => config_freepdk45.py} | 0 .../tests/{config_20_scn3me_subm.py => config_scn3me_subm.py} | 0 .../tests/{config_20_scn4m_subm.py => config_scn4m_subm.py} | 0 90 files changed, 88 insertions(+), 88 deletions(-) rename compiler/tests/{config_20_freepdk45.py => config_freepdk45.py} (100%) rename compiler/tests/{config_20_scn3me_subm.py => config_scn3me_subm.py} (100%) rename compiler/tests/{config_20_scn4m_subm.py => config_scn4m_subm.py} (100%) diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index 046e6378..1f4aa853 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -12,7 +12,7 @@ import debug class library_drc_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import verify (gds_dir, gds_files) = setup_files() diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 4ec40dc7..f312c298 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -12,7 +12,7 @@ import debug class library_lvs_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import verify (gds_dir, sp_dir, allnames) = setup_files() diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 33aa45ae..29d7ca0e 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -12,7 +12,7 @@ import debug class contact_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import contact diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index f0fc2299..78abc9e3 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -12,7 +12,7 @@ import debug class path_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import wire_path import tech import design diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 32372e25..a5ea028c 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size NMOS with 1 finger") diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 2ca3181b..f1a4de56 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size PMOS with 1 finger") diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 4e5e2eaf..535560e1 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 53a4aeca..fd2abc0b 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 10f7deda..56102419 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index e8dc2bc0..4d7181b1 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 1b18e14b..1cce5f08 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -12,7 +12,7 @@ import debug class wire_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import wire import tech import design diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index ff722500..8dd900fe 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -15,7 +15,7 @@ import debug class pand2_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index eca1fbda..b1edb5d7 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -16,7 +16,7 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 5dff97d7..7ee53781 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -15,7 +15,7 @@ import debug class pbuf_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pbuf", size=8) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index 0cb50a97..65cc3ee3 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -15,7 +15,7 @@ import debug class pdriver_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index fb68dc01..d24b3ef4 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -15,7 +15,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index aaa9f2de..0786ed80 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -15,7 +15,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index b0e0d6f3..a83fc6ee 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -14,7 +14,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index f34f08f7..517c5b0a 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -15,7 +15,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 8bef3c93..2febfab3 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -15,7 +15,7 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index ffdc542c..b8e25d52 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -17,7 +17,7 @@ import debug class pnand2_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 4ff2478b..9d0d8241 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -17,7 +17,7 @@ import debug class pnand3_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index ddfec78d..bb458b63 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -17,7 +17,7 @@ import debug class pnor2_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index cd3e79f3..ccf05090 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -15,7 +15,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 1f00ccca..7ce1b9cf 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -15,7 +15,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import replica_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 98a696d6..58d79ca4 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -17,7 +17,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check single level column mux in single port debug.info(2, "Checking column mux") diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 9e070038..9ea0cc32 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -17,7 +17,7 @@ import debug class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for cell_1rw_1r") OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index a1ee5b1a..82eaf256 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -17,7 +17,7 @@ import debug class array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index a6216a10..15040649 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -16,7 +16,7 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index d77e7572..f2277335 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -15,7 +15,7 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 8b82b721..dce5069f 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -15,7 +15,7 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index f8d22e69..1710b459 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -15,7 +15,7 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 9ccf56fc..1ff0d65b 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -14,7 +14,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import single_level_column_mux_array # check single level column mux array in single port diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index c5d72190..eb6d75dd 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -15,7 +15,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check precharge array in single port debug.info(2, "Checking 3 column precharge") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 8f8c51ac..12edf32e 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -17,7 +17,7 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 57654353..903e5512 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -15,7 +15,7 @@ import debug class sense_amp_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 53338a32..f3ed3ee6 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -15,7 +15,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index d1889388..5e3ce761 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -15,7 +15,7 @@ import debug class dff_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index 3d866ec8..86d394e6 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -15,7 +15,7 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index e25399a6..30b56957 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -15,7 +15,7 @@ import debug class dff_buf_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index c52aa641..04ef1369 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -15,7 +15,7 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index b4dae777..1dbfbc67 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -15,7 +15,7 @@ import debug class delay_chain_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) diff --git a/compiler/tests/14_replica_bitline_multiport_test.py b/compiler/tests/14_replica_bitline_multiport_test.py index aee4bcfe..3a83d397 100755 --- a/compiler/tests/14_replica_bitline_multiport_test.py +++ b/compiler/tests/14_replica_bitline_multiport_test.py @@ -15,7 +15,7 @@ import debug class replica_bitline_multiport_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) stages=4 fanout=4 diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index cd314126..8c1c306c 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -15,7 +15,7 @@ import debug class replica_bitline_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check replica bitline in single port stages=4 diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 1ba54cea..2b9a8be2 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -15,7 +15,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import control_logic import tech diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index 3f511464..9dcb6039 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -15,7 +15,7 @@ import debug class bank_select_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index af2ef7b0..57a089aa 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -16,7 +16,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 6b842160..f201c778 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -16,7 +16,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 524f3025..c36df8ef 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -16,7 +16,7 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from bank import bank from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index 41255b7b..96fc2512 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 1e4c59de..368a7cad 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -15,7 +15,7 @@ import debug class single_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 878cb252..22b878b9 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 255faa9b..61d636d9 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index bc8b90d8..7c38da90 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 3a0a9c8e..f7cb57fc 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 9cd7fe76..b13c8020 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 36b23800..a0d75054 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" OPTS.replica_bitcell="replica_bitcell_1w_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index d9118690..7f305c0e 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 59a7cdcc..96e8cfda 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index fd62f39a..b2cd395f 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index df2b3d8c..f8b43835 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=2, num_words=128, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 00191aec..b33ef2c4 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 6369398b..004c7604 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index db4782a8..b63691ec 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -16,7 +16,7 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 09d75e24..abe65b02 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -15,7 +15,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 2488317b..11020365 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -15,7 +15,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 2a0a4cb1..c0b2c8fe 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -15,7 +15,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 0bf004b9..774e3e75 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -15,7 +15,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 11db4842..8606fd5f 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index e8a436bd..45c4676d 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 34e974a5..7bc75e2e 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index f9e80915..1673c4f7 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 15dfc902..60e8929d 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 1ea8b6b9..b768a7b9 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index 95536c17..45aa2bff 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index d3712bee..baf10e9e 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index 4bb17eb6..df0ad3a6 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 5c787245..6cac68b1 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -14,7 +14,7 @@ import debug class model_corners_lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from characterizer import lib from sram import sram diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 0b4a17b0..0b4e1efb 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -14,7 +14,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from characterizer import lib from sram import sram diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index f8666d6f..266d3ba3 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -14,7 +14,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 6cddd840..a81b1479 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -14,7 +14,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 5417a40f..bd1fdc6a 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -15,7 +15,7 @@ import debug class lef_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 18d626cd..63810357 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -14,7 +14,7 @@ import debug class verilog_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index df4ff0f7..cd47a21c 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -16,7 +16,7 @@ import debug class sram_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.use_pex = True diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py index a023a614..0b208f62 100755 --- a/compiler/tests/27_worst_case_delay_test.py +++ b/compiler/tests/27_worst_case_delay_test.py @@ -17,7 +17,7 @@ class worst_case_timing_sram_test(openram_test): def runTest(self): OPTS.tech_name = "freepdk45" - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/28_delay_model_test.py b/compiler/tests/28_delay_model_test.py index a999cd20..95db008b 100755 --- a/compiler/tests/28_delay_model_test.py +++ b/compiler/tests/28_delay_model_test.py @@ -15,7 +15,7 @@ import debug class delay_model_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 531302cf..2681b351 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -19,7 +19,7 @@ class openram_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/config_20_{1}".format(OPENRAM_HOME,OPTS.tech_name)) + globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name)) debug.info(1, "Testing top-level openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" @@ -49,7 +49,7 @@ class openram_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}config_20_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) + config_name = "{0}config_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/config_20_freepdk45.py b/compiler/tests/config_freepdk45.py similarity index 100% rename from compiler/tests/config_20_freepdk45.py rename to compiler/tests/config_freepdk45.py diff --git a/compiler/tests/config_20_scn3me_subm.py b/compiler/tests/config_scn3me_subm.py similarity index 100% rename from compiler/tests/config_20_scn3me_subm.py rename to compiler/tests/config_scn3me_subm.py diff --git a/compiler/tests/config_20_scn4m_subm.py b/compiler/tests/config_scn4m_subm.py similarity index 100% rename from compiler/tests/config_20_scn4m_subm.py rename to compiler/tests/config_scn4m_subm.py