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update pex to work with dev changes

This commit is contained in:
jcirimel 2020-08-03 17:14:34 -07:00
parent 3221b4ec57
commit 02e65a00ef
3 changed files with 12 additions and 8 deletions
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6
compiler/characterizer/delay.py
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@ -181,7 +181,11 @@ class delay(simulation):
meas.targ_name_no_port)) meas.targ_name_no_port))
self.dout_volt_meas[-1].meta_str = meas.meta_str self.dout_volt_meas[-1].meta_str = meas.meta_str
self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9) if not OPTS.use_pex:
self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
else:
self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9)
self.sen_meas.meta_str = sram_op.READ_ZERO self.sen_meas.meta_str = sram_op.READ_ZERO
self.sen_meas.meta_add_delay = True self.sen_meas.meta_add_delay = True
self.dout_volt_meas.append(self.sen_meas) self.dout_volt_meas.append(self.sen_meas)

8
compiler/sram/sram_base.py
View File

@ -111,15 +111,15 @@ class sram_base(design, verilog, lef):
bl = [] bl = []
br = [] br = []
storage_layer_name = "metal1" storage_layer_name = "m1"
bitline_layer_name = "metal2" bitline_layer_name = "m2"
for cell in range(len(bank_offset)): for cell in range(len(bank_offset)):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
OPTS.words_per_row = self.words_per_row OPTS.words_per_row = self.words_per_row
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))) , storage_layer_name, Q) self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))), storage_layer_name, Q_bar) self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar)
for cell in range(len(bl_offsets)): for cell in range(len(bl_offsets)):
col = bl_meta[cell][0][2] col = bl_meta[cell][0][2]

2
compiler/verify/magic.py
View File

@ -464,7 +464,7 @@ def correct_port(name, output_file_name, ref_file_name):
control_list = "+ " control_list = "+ "
for bank in range(OPTS.num_banks): for bank in range(OPTS.num_banks):
control_list += "s_en{0}".format(bank) control_list += "bank_{}/s_en0".format(bank)
control_list += '\n' control_list += '\n'
part2 = bitcell_list + control_list + part2 part2 = bitcell_list + control_list + part2