diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 21355b0e..f5a57324 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -180,8 +180,12 @@ class delay(simulation):
             self.dout_volt_meas.append(voltage_at_measure("v_{}".format(meas.name), 
                                                            meas.targ_name_no_port)) 
             self.dout_volt_meas[-1].meta_str = meas.meta_str
-         
-        self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
+        
+            if not OPTS.use_pex:
+                self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
+            else:
+                self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9)
+
         self.sen_meas.meta_str = sram_op.READ_ZERO        
         self.sen_meas.meta_add_delay = True
         self.dout_volt_meas.append(self.sen_meas)
diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index 6dc98835..ffaca694 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -111,16 +111,16 @@ class sram_base(design, verilog, lef):
             bl = []
             br = []
 
-            storage_layer_name = "metal1"
-            bitline_layer_name = "metal2"
+            storage_layer_name = "m1"
+            bitline_layer_name = "m2"
             
             for cell in range(len(bank_offset)):
                 Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
                 Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
                 OPTS.words_per_row = self.words_per_row
-                self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))) , storage_layer_name, Q) 
-                self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))), storage_layer_name, Q_bar)
-            
+                self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q) 
+                self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar)
+
             for cell in range(len(bl_offsets)):
                 col = bl_meta[cell][0][2]
                 for bitline in range(len(bl_offsets[cell])):
diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py
index 1be2f2cd..dcdf6951 100644
--- a/compiler/verify/magic.py
+++ b/compiler/verify/magic.py
@@ -464,7 +464,7 @@ def correct_port(name, output_file_name, ref_file_name):
 
     control_list = "+ "
     for bank in range(OPTS.num_banks):
-        control_list += "s_en{0}".format(bank)
+        control_list += "bank_{}/s_en0".format(bank)
     control_list += '\n'
 
     part2 = bitcell_list + control_list + part2