Fixes to replica bitline array.

Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
This commit is contained in:
mrg
2020-10-08 14:53:44 -07:00
parent 03e1b9c50d
commit 01fe02bd90
3 changed files with 25 additions and 12 deletions
+12 -5
View File
@@ -53,6 +53,8 @@ class replica_column(bitcell_base_array):
self.create_instances()
def create_layout(self):
self.height = self.total_size * self.cell.height
self.width = self.cell.width
self.place_instances()
self.add_layout_pins()
@@ -62,11 +64,15 @@ class replica_column(bitcell_base_array):
def add_pins(self):
self.create_all_bitline_names()
#remove 2 wordlines to account for top/bot
if not cell_properties.bitcell.end_caps:
try:
if cell_properties.bitcell.end_caps:
# remove 2 wordlines to account for top/bot
self.create_all_wordline_names(num_remove_wordlines=2)
else:
self.create_all_wordline_names()
except AttributeError:
self.create_all_wordline_names()
else:
self.create_all_wordline_names(2)
self.add_pin_list(self.all_bitline_names, "OUTPUT")
self.add_pin_list(self.all_wordline_names, "INPUT")
@@ -112,7 +118,6 @@ class replica_column(bitcell_base_array):
self.colenda_p_cent = factory.create(module_type="s8_col_end", version = "colenda_p_cent")
self.add_mod(self.colenda_p_cent)
def create_instances(self):
self.cell_inst = {}
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
@@ -309,3 +314,5 @@ class replica_column(bitcell_base_array):
for row, cell in self.cell_inst.items():
if row != self.replica_bit:
self.graph_inst_exclude.add(cell)