mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Fixes to replica bitline array.
Copy pasta error for right dummy column offset. Put end_caps in try/except block. PEP 8 formatting
This commit is contained in:
@@ -56,8 +56,8 @@ class bitcell_base_array(design.design):
|
||||
# def get_all_wordline_names(self, prefix=""):
|
||||
# return [prefix + x for x in self.all_wordline_names]
|
||||
|
||||
def create_all_wordline_names(self, remove_wordline = 0):
|
||||
for row in range(self.row_size - remove_wordline):
|
||||
def create_all_wordline_names(self, num_remove_wordline=0):
|
||||
for row in range(self.row_size - num_remove_wordline):
|
||||
for port in self.all_ports:
|
||||
if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
|
||||
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
|
||||
@@ -245,4 +245,4 @@ class bitcell_base_array(design.design):
|
||||
Return an array of the x offsets of all the regular bits
|
||||
"""
|
||||
offsets = [self.cell_inst[0, col].lx() for col in range(self.column_size)]
|
||||
return offsets
|
||||
return offsets
|
||||
|
||||
Reference in New Issue
Block a user