diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py
index e7b45d05..34d9b7f3 100644
--- a/compiler/modules/dff_buf.py
+++ b/compiler/modules/dff_buf.py
@@ -20,6 +20,12 @@ class dff_buf(design.design):
         design.design.__init__(self, name)
         debug.info(1, "Creating {}".format(self.name))
 
+        # This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
+        # This causes a DRC in the pinv which assumes min width rails. This ensures the output
+        # contact does not violate spacing to the rail in the NMOS.
+        debug.check(inv1_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
+        debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")        
+
         from importlib import reload
         c = reload(__import__(OPTS.dff))
         self.mod_dff = getattr(c, OPTS.dff)
diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py
index 2b165bd0..cb5b0478 100644
--- a/compiler/modules/dff_inv.py
+++ b/compiler/modules/dff_inv.py
@@ -19,13 +19,16 @@ class dff_inv(design.design):
         design.design.__init__(self, name)
         debug.info(1, "Creating {}".format(self.name))
 
+        # This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
+        # This causes a DRC in the pinv which assumes min width rails. This ensures the output
+        # contact does not violate spacing to the rail in the NMOS.
+        debug.check(inv_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
+
         from importlib import reload
         c = reload(__import__(OPTS.dff))
         self.mod_dff = getattr(c, OPTS.dff)
         self.dff = self.mod_dff("dff")
         self.add_mod(self.dff)
-
-        debug.check(inv_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
         
         self.inv1 = pinv(size=inv_size,height=self.dff.height)
         self.add_mod(self.inv1)