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Fix power ring routing boundary bug.

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This commit is contained in:
mrg
2022-03-18 10:32:25 -07:00
parent 7e7670581c
commit 01a73b31e1
10 changed files with 98 additions and 71 deletions
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compiler/modules/delay_chain.py
+11 -8
View File
@@ -177,15 +177,18 @@ class delay_chain(design.design):
# The routing to connect the loads is over the first and last cells
# We have an even number of drivers and must only do every other
# supply rail
if OPTS.experimental_power:
self.route_horizontal_pins("vdd")
self.route_horizontal_pins("gnd")
else:
for inst in self.driver_inst_list:
load_list = self.load_inst_map[inst]
for pin_name in ["vdd", "gnd"]:
pin = load_list[0].get_pin(pin_name)
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
for inst in self.driver_inst_list:
load_list = self.load_inst_map[inst]
for pin_name in ["vdd", "gnd"]:
pin = load_list[0].get_pin(pin_name)
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
pin = load_list[-2].get_pin(pin_name)
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
pin = load_list[-2].get_pin(pin_name)
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
def add_layout_pins(self):
compiler/modules/wordline_driver_array.py
+1 -1
View File
@@ -78,7 +78,7 @@ class wordline_driver_array(design.design):
"""
# Experiment with power straps
if OPTS.experimental_power:
if OPTS.tech_name=="sky130" or OPTS.experimental_power:
if layer_props.wordline_driver.vertical_supply:
self.route_vertical_pins("vdd", insts=self.wld_inst)
self.route_vertical_pins("gnd", insts=self.wld_inst)