OpenRAM/compiler/example_config_freepdk45.py

word_size = 2
num_words = 16

tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

#Setting for multiport
# netlist_only = True
# bitcell = "pbitcell"
# replica_bitcell="replica_pbitcell"
# num_rw_ports = 1
# num_r_ports = 0
# num_w_ports = 1
Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 20:11:57 +02:00			`word_size = 2`
Fix num words in example. 2018-02-23 21:17:43 +01:00			`num_words = 16`
RELEASE 1.0 2016-11-08 18:57:35 +01:00
			`tech_name = "freepdk45"`
Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 20:22:47 +01:00			`process_corners = ["TT"]`
			`supply_voltages = [1.0]`
			`temperatures = [25]`
RELEASE 1.0 2016-11-08 18:57:35 +01:00
Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-20 01:38:19 +01:00			`output_path = "temp"`
Remove banks from example configs 2018-10-12 19:23:34 +02:00			`output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)`
Enable output filename and path to be in config file. Command line will over-ride config file. 2017-06-12 23:37:15 +02:00
Multiport variable bug fix and removed unused code. 2018-09-25 21:49:27 +02:00			`#Setting for multiport`
Altered web to only be generated for rw ports. 2018-10-04 22:30:58 +02:00			`# netlist_only = True`
			`# bitcell = "pbitcell"`
			`# replica_bitcell="replica_pbitcell"`
			`# num_rw_ports = 1`
			`# num_r_ports = 0`
			`# num_w_ports = 1`