mirror of https://github.com/VLSIDA/OpenRAM.git
58 lines
3.3 KiB
Plaintext
58 lines
3.3 KiB
Plaintext
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[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Temporary files saved in /home/jesse/output/
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[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/giant_config_scn4m_subm.py
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[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
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[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
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[globals/init_paths]: Creating temp directory: /home/jesse/output/
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[verify/<module>]: Initializing verify...
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[verify/<module>]: LVS/DRC/PEX disabled.
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[characterizer/<module>]: Initializing characterizer...
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[characterizer/<module>]: Analytical model enabled.
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[globals/setup_bitcell]: Using bitcell: bitcell
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|==============================================================================|
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|========= OpenRAM v1.1.4 =========|
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|========= =========|
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|========= VLSI Design and Automation Lab =========|
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|========= Computer Science and Engineering Department =========|
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|========= University of California Santa Cruz =========|
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|========= =========|
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|========= Usage help: openram-user-group@ucsc.edu =========|
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|========= Development help: openram-dev-group@ucsc.edu =========|
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|========= Temp dir: /home/jesse/output/ =========|
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|========= See LICENSE for license info =========|
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|==============================================================================|
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** Start: 04/09/2020 05:13:06
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Technology: scn4m_subm
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Total size: 65536 bits
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Word size: 64
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Words: 1024
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Banks: 1
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Write size: None
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RW ports: 1
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R-only ports: 0
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W-only ports: 0
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Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).
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DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
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DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
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Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
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[sram_config/recompute_sizes]: Recomputing with words per row: 4
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[sram_config/recompute_sizes]: Rows: 256 Cols: 256
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[sram_config/recompute_sizes]: Row addr size: 8 Col addr size: 2 Bank addr size: 10
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Words per row: 4
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Output files are:
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.sp
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.v
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.lib
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.py
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.html
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.log
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.lef
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/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.gds
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[dff_array/__init__]: Creating row_addr_dff rows=8 cols=1
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[dff_array/__init__]: Creating col_addr_dff rows=1 cols=2
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[dff_array/__init__]: Creating data_dff rows=1 cols=64
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[precharge_array/__init__]: Creating precharge_array_0
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[sense_amp_array/__init__]: Creating sense_amp_array_0
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[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array_0
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[write_driver_array/__init__]: Creating write_driver_array_0
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