[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /home/jesse/output/
[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/giant_config_scn4m_subm.py
[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
[globals/init_paths]: Creating temp directory: /home/jesse/output/
[verify/<module>]: Initializing verify...
[verify/<module>]: LVS/DRC/PEX disabled.
[characterizer/<module>]: Initializing characterizer...
[characterizer/<module>]: Analytical model enabled.
[globals/setup_bitcell]: Using bitcell: bitcell
|==============================================================================|
|=========                       OpenRAM v1.1.4                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========               Temp dir: /home/jesse/output/                =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 04/09/2020 05:13:06
Technology: scn4m_subm
Total size: 65536 bits
Word size: 64
Words: 1024
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
[sram_config/recompute_sizes]: Recomputing with words per row: 4
[sram_config/recompute_sizes]: Rows: 256 Cols: 256
[sram_config/recompute_sizes]: Row addr size: 8 Col addr size: 2 Bank addr size: 10
Words per row: 4
Output files are: 
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.sp
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.v
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.lib
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.py
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.html
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.log
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.lef
/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.gds
[dff_array/__init__]: Creating row_addr_dff rows=8 cols=1
[dff_array/__init__]: Creating col_addr_dff rows=1 cols=2
[dff_array/__init__]: Creating data_dff rows=1 cols=64
[precharge_array/__init__]: Creating precharge_array_0
[sense_amp_array/__init__]: Creating sense_amp_array_0
[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array_0
[write_driver_array/__init__]: Creating write_driver_array_0