2021-04-19 22:24:18 +02:00

2018-11-16 00:09:38 +01:00
# OpenRAM
2018-11-21 17:54:38 +01:00
[](https://www.python.org/)
2018-11-16 00:09:38 +01:00
[](./LICENSE)
2021-04-21 22:00:49 +02:00
[](https://github.com/VLSIDA/OpenRAM/archive/stable.zip)
2018-11-21 17:54:38 +01:00
[](https://github.com/VLSIDA/OpenRAM/archive/dev.zip)
2018-11-16 00:09:38 +01:00
An open-source static random access memory (SRAM) compiler.
2017-11-09 19:57:24 +01:00
2018-11-16 00:09:38 +01:00
# What is OpenRAM?
< img align = "right" width = "25%" src = "images/SCMOS_16kb_sram.jpg" >
2017-11-09 19:57:24 +01:00
2020-02-27 07:09:26 +01:00
OpenRAM is an award winning open-source Python framework to create the layout,
2018-11-16 00:09:38 +01:00
netlists, timing and power models, placement and routing models, and
other views necessary to use SRAMs in ASIC design. OpenRAM supports
integration in both commercial and open-source flows with both
predictive and fabricable technologies.
2017-11-09 19:57:24 +01:00
2019-03-06 17:29:43 +01:00
# Documentation
Please take a look at our presentation We have created a detailed
presentation that serves as our [documentation][documentation].
This is the most up-to-date information, so please let us know if you see
things that need to be fixed.
2018-11-16 00:09:38 +01:00
# Basic Setup
2017-11-09 19:57:24 +01:00
2019-02-17 19:35:56 +01:00
## Dependencies
2022-07-13 19:57:56 +02:00
Please see the Dockerfile for the required versions of tools.
In general, the OpenRAM compiler has very few dependencies:
+ Docker
+ Make
2021-11-16 20:17:00 +01:00
+ Python 3.6 or higher
2021-04-21 19:39:15 +02:00
+ Various Python packages (pip install -r requirements.txt)
2021-10-04 23:43:14 +02:00
+ [Git]
2017-11-09 19:57:24 +01:00
2022-07-13 19:57:56 +02:00
## Docker
We have a [docker setup ](./docker ) to run OpenRAM. To use this, you should run:
```
2022-08-26 17:51:01 +02:00
cd OpenRAM/docker
2022-07-13 19:57:56 +02:00
make build
```
This must be run once and will take a while to build all the tools.
## Environment
2017-11-09 19:57:24 +01:00
2021-11-16 20:17:00 +01:00
You must set two environment variables:
+ OPENRAM\_HOME should point to the compiler source directory.
2021-01-22 19:33:11 +01:00
+ OPENERAM\_TECH should point to one or more root technology directories (colon separated).
2017-11-09 19:57:24 +01:00
2022-07-20 19:27:10 +02:00
You should also add OPENRAM\_HOME to your PYTHONPATH.
2019-02-17 19:35:56 +01:00
2018-11-16 00:09:38 +01:00
For example add this to your .bashrc:
2017-11-09 19:57:24 +01:00
```
2022-08-26 22:25:47 +02:00
export OPENRAM_HOME="$HOME/OpenRAM/compiler"
export OPENRAM_TECH="$HOME/OpenRAM/technology"
2017-11-09 19:57:24 +01:00
```
2022-07-13 19:57:56 +02:00
You should also add OPENRAM\_HOME to your PYTHONPATH:
2018-11-21 17:54:38 +01:00
```
2022-07-13 19:57:56 +02:00
export PYTHONPATH=$OPENRAM_HOME
```
2022-07-20 19:27:10 +02:00
2022-07-13 19:57:56 +02:00
Note that if you want symbols to resolve in your editor, you may also want to add the specific technology
directory that you use and any custom technology modules as well. For example:
```
export PYTHONPATH="$OPENRAM_HOME:$OPENRAM_TECH/sky130:$OPENRAM_TECH/sky130/custom"
```
2018-11-21 17:54:38 +01:00
2021-11-16 20:17:00 +01:00
We include the tech files necessary for [SCMOS] SCN4M_SUBM,
2022-03-04 23:21:58 +01:00
[FreePDK45]. The [SCMOS] spice models, however, are
2021-11-16 20:17:00 +01:00
generic and should be replaced with foundry models. You may get the
entire [FreePDK45 PDK here][FreePDK45].
2017-11-09 19:57:24 +01:00
2022-07-13 19:57:56 +02:00
2022-03-04 23:21:58 +01:00
### Sky130 Setup
To install [Sky130], you must have the open_pdks files installed in $PDK_ROOT.
To install this automatically, you can run:
2021-11-16 23:33:35 +01:00
2022-08-26 22:25:47 +02:00
```
cd $HOME/OpenRAM
make pdk
```
2022-03-04 23:21:58 +01:00
Then you must also install the [Sky130] SRAM build space and the appropriate cell views
by running:
2022-08-26 22:25:47 +02:00
```
cd $HOME/OpenRAM
make install
```
2022-07-13 19:57:56 +02:00
2018-11-16 00:09:38 +01:00
# Basic Usage
2017-11-09 19:57:24 +01:00
2021-11-16 20:17:00 +01:00
Once you have defined the environment, you can run OpenRAM from the command line
using a single configuration file written in Python.
2017-11-09 19:57:24 +01:00
2018-11-16 00:09:38 +01:00
For example, create a file called *myconfig.py* specifying the following
parameters for your memory:
2022-07-13 19:57:56 +02:00
```
2018-11-16 00:09:38 +01:00
# Data word size
word_size = 2
# Number of words in the memory
num_words = 16
2017-11-09 19:57:24 +01:00
2018-11-21 17:54:38 +01:00
# Technology to use in $OPENRAM_TECH
2018-11-16 00:09:38 +01:00
tech_name = "scn4m_subm"
2019-12-06 18:50:03 +01:00
# You can use the technology nominal corner only
nominal_corner_only = True
# Or you can specify particular corners
2018-11-16 00:09:38 +01:00
# Process corners to characterize
2019-12-06 18:50:03 +01:00
# process_corners = ["SS", "TT", "FF"]
2018-11-16 00:09:38 +01:00
# Voltage corners to characterize
2019-12-06 18:50:03 +01:00
# supply_voltages = [ 3.0, 3.3, 3.5 ]
2018-11-16 00:09:38 +01:00
# Temperature corners to characterize
2019-12-06 18:50:03 +01:00
# temperatures = [ 0, 25 100]
2018-02-06 20:22:22 +01:00
2018-11-16 00:09:38 +01:00
# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
2017-11-09 19:57:24 +01:00
2018-11-16 00:09:38 +01:00
# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False
2019-01-04 00:37:53 +01:00
2018-11-16 00:09:38 +01:00
```
2017-11-09 19:57:24 +01:00
2018-11-16 00:09:38 +01:00
You can then run OpenRAM by executing:
2017-11-09 19:57:24 +01:00
```
2018-11-21 17:54:38 +01:00
python3 $OPENRAM_HOME/openram.py myconfig
2017-11-09 19:57:24 +01:00
```
2018-11-16 00:09:38 +01:00
You can see all of the options for the configuration file in
$OPENRAM\_HOME/options.py
2017-11-09 19:57:24 +01:00
2021-11-16 23:33:35 +01:00
To run designs in Docker, it is suggested to use, for example:
```
2022-08-26 22:25:47 +02:00
cd OpenRAM/macros
2021-11-16 23:33:35 +01:00
make example_config_scn4m_subm
```
2018-11-16 00:09:38 +01:00
# Unit Tests
2017-11-09 19:57:24 +01:00
2018-11-16 00:09:38 +01:00
Regression testing performs a number of tests for all modules in OpenRAM.
2021-11-16 20:17:00 +01:00
From the unit test directory ($OPENRAM\_HOME/tests),
2018-11-16 00:09:38 +01:00
use the following command to run all regression tests:
2017-11-09 19:57:24 +01:00
```
2022-08-26 22:25:47 +02:00
cd OpenRAM/compiler/tests
2022-03-04 23:21:58 +01:00
make -j 3
2017-11-09 19:57:24 +01:00
```
2022-03-04 23:21:58 +01:00
The -j can run with 3 threads. By default, this will run in all technologies.
2021-11-16 23:33:35 +01:00
2022-07-13 19:57:56 +02:00
To run a specific test in all technologies:
2017-11-09 19:57:24 +01:00
```
2022-08-26 22:25:47 +02:00
cd OpenRAM/compiler/tests
2021-11-16 23:33:35 +01:00
make 05_bitcell_array_test
2022-05-04 19:21:12 +02:00
```
2022-03-04 23:21:58 +01:00
To run a specific technology:
2022-05-04 19:21:12 +02:00
```
2022-08-26 22:25:47 +02:00
cd OpenRAM/compiler/tests
2022-03-04 23:21:58 +01:00
TECHS=scn4m_subm make 05_bitcell_array_test
2022-05-04 19:21:12 +02:00
```
2018-11-16 00:09:38 +01:00
2021-11-16 23:33:35 +01:00
To increase the verbosity of the test, add one (or more) -v options and
pass it as an argument to OpenRAM:
2017-11-09 19:57:24 +01:00
```
2022-03-04 23:21:58 +01:00
ARGS="-v" make 05_bitcell_array_test
2022-05-04 19:21:12 +02:00
```
2018-02-06 20:14:43 +01:00
2022-07-13 19:57:56 +02:00
Unit test results are put in a directory:
```
2022-08-26 22:25:47 +02:00
OpenRAM/compiler/tests/results/< technology > /< test >
2022-07-13 19:57:56 +02:00
```
If the test fails, there will be a tmp directory with intermediate results.
If the test passes, this directory will be deleted to save space.
You can view the .out file to see what the output of a test is in either case.
2018-11-16 00:09:38 +01:00
# Get Involved
2021-11-16 23:33:35 +01:00
+ [Port it ](./PORTING.md ) to a new technology.
2018-11-16 00:09:38 +01:00
+ Report bugs by submitting [Github issues].
+ Develop new features (see [how to contribute ](./CONTRIBUTING.md ))
2021-11-16 20:17:00 +01:00
+ Submit code/fixes using a [Github pull request]
2020-02-25 17:06:26 +01:00
+ Follow our [project][Github project].
2018-11-16 00:09:38 +01:00
+ Read and cite our [ICCAD paper][OpenRAMpaper]
# Further Help
2019-03-06 17:29:43 +01:00
+ [Documentation][documentation]
2018-11-16 00:09:38 +01:00
+ [OpenRAM Slack Workspace][Slack]
+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
2021-11-16 20:17:00 +01:00
# License
2018-11-16 00:09:38 +01:00
OpenRAM is licensed under the [BSD 3-clause License ](./LICENSE ).
# Contributors & Acknowledgment
- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
- [James Stine] from [VLSIARCH] co-founded the project.
2020-02-25 17:06:26 +01:00
- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera
2018-11-16 00:09:38 +01:00
2018-11-21 17:54:38 +01:00
If I forgot to add you, please let me know!
2018-11-16 00:09:38 +01:00
* * *
[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg
[James Stine]: https://ece.okstate.edu/content/stine-james-e-jr-phd
[VLSIDA]: https://vlsida.soe.ucsc.edu
[VLSIARCH]: https://vlsiarch.ecen.okstate.edu/
[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
2018-11-21 17:54:38 +01:00
[Github issues]: https://github.com/VLSIDA/OpenRAM/issues
[Github pull request]: https://github.com/VLSIDA/OpenRAM/pulls
2022-10-15 01:38:10 +02:00
[Github project]: https://github.com/VLSIDA/OpenRAM
2018-11-16 00:09:38 +01:00
2022-10-15 01:43:06 +02:00
[documentation]: docs/source/index.md
2018-11-16 00:09:38 +01:00
[dev-group]: mailto:openram-dev-group@ucsc.edu
[user-group]: mailto:openram-user-group@ucsc.edu
[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu
[user-group-subscribe]: mailto:openram-user-group+subscribe@ucsc.edu
2022-07-13 19:57:56 +02:00
[Klayout]: https://www.klayout.de/
2018-11-16 00:09:38 +01:00
[Magic]: http://opencircuitdesign.com/magic/
[Netgen]: http://opencircuitdesign.com/netgen/
[Qflow]: http://opencircuitdesign.com/qflow/history.html
[Ngspice]: http://ngspice.sourceforge.net/
2021-05-15 01:16:25 +02:00
[Xyce]: http://xyce.sandia.gov/
2021-10-04 23:43:14 +02:00
[Git]: https://git-scm.com/
2018-11-16 00:09:38 +01:00
[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf
2021-11-16 20:17:00 +01:00
[Sky130]: https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
2018-11-16 00:09:38 +01:00
2022-05-04 19:15:40 +02:00
[Slack]: https://join.slack.com/t/openram/shared_invite/zt-onim74ue-zlttW5XI30xvdBlJGJF6JA
2022-05-04 19:21:12 +02:00
2022-05-04 19:15:40 +02:00