2019-02-24 18:54:45 +01:00
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.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
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MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
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MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
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MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
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MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
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MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
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2019-02-24 19:48:54 +01:00
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MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
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MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
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2019-02-24 18:54:45 +01:00
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MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
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MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
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.ENDS
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