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OpenRAM/technology/freepdk45/sp_lib/dummy_cell_1rw.sp

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Add freepdk45 dummy cells
2019-07-03 23:53:44 +02:00
Rework bitcells. Name them 1port and 2port consistently. Allow cell overrides to cell_1rw and cell_2rw or other. Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
2020-11-13 19:07:40 +01:00
.SUBCKT dummy_cell_1rw bl br wl vdd gnd
Add freepdk45 dummy cells
2019-07-03 23:53:44 +02:00
* Inverter 1
change Qbar to Q_bar in freepdk45 bitcells
2020-08-05 00:21:54 +02:00
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
Add freepdk45 dummy cells
2019-07-03 23:53:44 +02:00
* Inverer 2
change Qbar to Q_bar in freepdk45 bitcells
2020-08-05 00:21:54 +02:00
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
Add freepdk45 dummy cells
2019-07-03 23:53:44 +02:00
* Access transistors
MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n
change Qbar to Q_bar in freepdk45 bitcells
2020-08-05 00:21:54 +02:00
MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n
fix end subckt typo
2021-02-28 00:28:07 +01:00
.ENDS dummy_cell_1rw
Add freepdk45 dummy cells
2019-07-03 23:53:44 +02:00