OpenRAM/compiler/example_configs/example_config_1rw_1r_scn4m...

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word_size = 2
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num_words = 16
num_rw_ports = 1
num_r_ports = 1
num_w_ports = 0
tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True
output_path = "temp"
output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name)
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drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"