2023-03-03 23:17:57 +01:00
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.base import contact
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from openram.sram_factory import factory
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from openram.tech import drc, spice
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from openram.tech import cell_properties as props
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from openram import OPTS
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2023-08-26 01:39:32 +02:00
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from openram.modules.capped_replica_bitcell_array import capped_replica_bitcell_array
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2023-03-03 23:17:57 +01:00
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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2023-08-26 01:39:32 +02:00
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class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_bitcell_base_array):
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2023-03-03 23:17:57 +01:00
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"""
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Creates a replica bitcell array then adds the row and column caps to all
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sides of a bitcell array.
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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2023-08-26 01:39:32 +02:00
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super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
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2023-08-27 03:54:07 +02:00
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