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OpenRAM/compiler/modules/hierarchical_predecode4x16.py

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Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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# See LICENSE for licensing information.
#
Update copyright year
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
Use library imports globally
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from openram import OPTS
Use packages for imports. Must set PYTHONPATH to include OPENRAM_HOME now. Reorganizes subdirs as packages. Rewrites unit tests to use packages. Update README.md with instructions, dependencies etc. Update sky130 module imports. Change tech specific package from modules to custom.
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from .hierarchical_predecode import hierarchical_predecode
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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class hierarchical_predecode4x16(hierarchical_predecode):
"""
Pre 4x16 decoder used in hierarchical_decoder.
"""
Skywater changes. Default 1 thread and no temp subdirectory. Add skywater setup/hold golden data Add CLI option for simulation threads (-m) Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading. Make subdir when using default /tmp dir. Pass num_threads so temp subdirs are created.
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def __init__(self, name, column_decoder=False, height=None):
super().__init__(name, 4, column_decoder, height)
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
def create_netlist(self):
self.add_pins()
self.add_modules()
self.create_input_inverters()
connections=[["inbar_0", "inbar_1", "inbar_2", "inbar_3", "out_0", "vdd", "gnd"],
Remove EOL whitespace globally
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["in_0", "inbar_1", "inbar_2", "inbar_3", "out_1", "vdd", "gnd"],
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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["inbar_0", "in_1", "inbar_2", "inbar_3", "out_2", "vdd", "gnd"],
Remove EOL whitespace globally
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["in_0", "in_1", "inbar_2", "inbar_3", "out_3", "vdd", "gnd"],
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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["inbar_0", "inbar_1", "in_2", "inbar_3", "out_4", "vdd", "gnd"],
["in_0", "inbar_1", "in_2", "inbar_3", "out_5", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "inbar_3", "out_6", "vdd", "gnd"],
["in_0", "in_1", "in_2", "inbar_3", "out_7", "vdd", "gnd"],
Add decoder4x16
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["inbar_0", "inbar_1", "inbar_2", "in_3", "out_8", "vdd", "gnd"],
Remove EOL whitespace globally
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["in_0", "inbar_1", "inbar_2", "in_3", "out_9", "vdd", "gnd"],
Add decoder4x16
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["inbar_0", "in_1", "inbar_2", "in_3", "out_10", "vdd", "gnd"],
Remove EOL whitespace globally
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["in_0", "in_1", "inbar_2", "in_3", "out_11", "vdd", "gnd"],
Add decoder4x16
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["inbar_0", "inbar_1", "in_2", "in_3", "out_12", "vdd", "gnd"],
["in_0", "inbar_1", "in_2", "in_3", "out_13", "vdd", "gnd"],
["inbar_0", "in_1", "in_2", "in_3", "out_14", "vdd", "gnd"],
["in_0", "in_1", "in_2", "in_3", "out_15", "vdd", "gnd"] ]
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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self.create_and_array(connections)
def get_and_input_line_combination(self):
""" These are the decoder connections of the AND gates to the A,B pins """
combination = [["Abar_0", "Abar_1", "Abar_2", "Abar_3"],
["A_0", "Abar_1", "Abar_2", "Abar_3"],
["Abar_0", "A_1", "Abar_2", "Abar_3"],
["A_0", "A_1", "Abar_2", "Abar_3"],
["Abar_0", "Abar_1", "A_2" , "Abar_3"],
Remove EOL whitespace globally
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["A_0", "Abar_1", "A_2" , "Abar_3"],
["Abar_0", "A_1", "A_2" , "Abar_3"],
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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["A_0", "A_1", "A_2" , "Abar_3"],
["Abar_0", "Abar_1", "Abar_2", "A_3"],
["A_0", "Abar_1", "Abar_2", "A_3"],
["Abar_0", "A_1", "Abar_2", "A_3"],
["A_0", "A_1", "Abar_2", "A_3"],
["Abar_0", "Abar_1", "A_2", "A_3"],
Remove EOL whitespace globally
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["A_0", "Abar_1", "A_2", "A_3"],
["Abar_0", "A_1", "A_2", "A_3"],
Thin-cell decoder changes. Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
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["A_0", "A_1", "A_2", "A_3"]]
return combination