luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
ae6d2716025a892b9af5ca022595dff6d45480e8
OpenRAM/compiler/modules
T
History
Sam Crow ae6d271602 add support for no rbl to port data
2023-04-05 15:33:45 -07:00
..
__init__.py
Update copyright year
2023-01-28 22:56:27 -08:00
and2_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
and3_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
and4_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
bank.py
use capped array to create banks
2023-02-21 09:58:46 -08:00
bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
bitcell_2port.py
Update copyright year
2023-01-28 22:56:27 -08:00
bitcell_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
bitcell_base_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
bitcell_base.py
Update copyright year
2023-01-28 22:56:27 -08:00
capped_replica_bitcell_array.py
change array modules to allow rbl=[0, 0]
2023-03-09 10:23:28 -08:00
col_cap_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
col_cap_bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
col_cap_bitcell_2port.py
Update copyright year
2023-01-28 22:56:27 -08:00
column_decoder.py
Update copyright year
2023-01-28 22:56:27 -08:00
column_mux_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
column_mux.py
Update copyright year
2023-01-28 22:56:27 -08:00
control_logic_base.py
Update copyright year
2023-01-28 22:56:27 -08:00
control_logic.py
Update copyright year
2023-01-28 22:56:27 -08:00
delay_chain.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff_buf_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff_buf.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff_inv_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff_inv.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff.py
Update copyright year
2023-01-28 22:56:27 -08:00
dummy_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
dummy_bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
dummy_bitcell_2port.py
Update copyright year
2023-01-28 22:56:27 -08:00
dummy_pbitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
global_bitcell_array.py
add no rbl support to global array
2023-04-05 14:47:15 -07:00
hierarchical_decoder.py
Update copyright year
2023-01-28 22:56:27 -08:00
hierarchical_predecode2x4.py
Update copyright year
2023-01-28 22:56:27 -08:00
hierarchical_predecode3x8.py
Update copyright year
2023-01-28 22:56:27 -08:00
hierarchical_predecode4x16.py
Update copyright year
2023-01-28 22:56:27 -08:00
hierarchical_predecode.py
Update copyright year
2023-01-28 22:56:27 -08:00
internal_base.py
Update copyright year
2023-01-28 22:56:27 -08:00
inv_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
local_bitcell_array.py
support no rbls in local array
2023-03-09 14:44:05 -08:00
multibank.py
Update copyright year
2023-01-28 22:56:27 -08:00
nand2_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
nand3_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
nand4_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
orig_bitcell_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
pand2.py
Update copyright year
2023-01-28 22:56:27 -08:00
pand3.py
Update copyright year
2023-01-28 22:56:27 -08:00
pand4.py
Update copyright year
2023-01-28 22:56:27 -08:00
pbitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
pbuf_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
pbuf.py
Update copyright year
2023-01-28 22:56:27 -08:00
pdriver.py
Update copyright year
2023-01-28 22:56:27 -08:00
pgate.py
Update copyright year
2023-01-28 22:56:27 -08:00
pinv_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
pinv.py
Update copyright year
2023-01-28 22:56:27 -08:00
pinvbuf.py
Update copyright year
2023-01-28 22:56:27 -08:00
pnand2.py
Update copyright year
2023-01-28 22:56:27 -08:00
pnand3.py
Update copyright year
2023-01-28 22:56:27 -08:00
pnand4.py
Update copyright year
2023-01-28 22:56:27 -08:00
pnor2.py
Update copyright year
2023-01-28 22:56:27 -08:00
port_address.py
Update copyright year
2023-01-28 22:56:27 -08:00
port_data.py
add support for no rbl to port data
2023-04-05 15:33:45 -07:00
precharge_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
precharge.py
Update copyright year
2023-01-28 22:56:27 -08:00
ptristate_inv.py
Update copyright year
2023-01-28 22:56:27 -08:00
ptx.py
Update copyright year
2023-01-28 22:56:27 -08:00
pwrite_driver.py
Update copyright year
2023-01-28 22:56:27 -08:00
replica_bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
replica_bitcell_2port.py
Update copyright year
2023-01-28 22:56:27 -08:00
replica_bitcell_array.py
change array modules to allow rbl=[0, 0]
2023-03-09 10:23:28 -08:00
replica_column.py
Merge remote-tracking branch 'origin/dev' into no_rbl
2023-02-20 22:11:02 -08:00
replica_pbitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
row_cap_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
row_cap_bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
row_cap_bitcell_2port.py
Update copyright year
2023-01-28 22:56:27 -08:00
sense_amp_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
sense_amp.py
Update copyright year
2023-01-28 22:56:27 -08:00
sram_1bank.py
Update copyright year
2023-01-28 22:56:27 -08:00
sram_multibank_template.v
Shrunk address register in multibank verilog
2022-07-28 15:03:41 -07:00
sram_multibank.py
Update copyright year
2023-01-28 22:56:27 -08:00
template.py
Update copyright year
2023-01-28 22:56:27 -08:00
tri_gate_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
tri_gate.py
Update copyright year
2023-01-28 22:56:27 -08:00
wordline_buffer_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
wordline_driver_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
wordline_driver.py
Update copyright year
2023-01-28 22:56:27 -08:00
write_driver_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
write_driver.py
Update copyright year
2023-01-28 22:56:27 -08:00
write_mask_and_array.py
Update copyright year
2023-01-28 22:56:27 -08:00