OpenRAM/compiler/example_configs/medium_config_scn4m_subm.py

word_size = 16
num_words = 256

tech_name = "scn4m_subm"
nominal_corners_only = False
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]

output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,
                                        num_words,
                                        tech_name)
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 23:15:16 +01:00			`word_size = 16`
			`num_words = 256`
RELEASE 1.0 2016-11-08 18:57:35 +01:00
Remove scn3me lib files. Remove bank references. 2018-09-24 20:28:43 +02:00			`tech_name = "scn4m_subm"`
Change default nominal corners to false and enable in test config. 2019-11-29 21:08:53 +01:00			`nominal_corners_only = False`
Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 20:22:47 +01:00			`process_corners = ["TT"]`
Change default nominal corners to false and enable in test config. 2019-11-29 21:08:53 +01:00			`supply_voltages = [5.0]`
Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 19:30:16 +02:00			`temperatures = [25]`
Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-10 00:33:03 +01:00
Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-20 01:38:19 +01:00			`output_path = "temp"`
Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 19:30:16 +02:00			`output_name = "sram_{0}_{1}_{2}".format(word_size,`
			`num_words,`
			`tech_name)`
Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-23 04:04:42 +02:00