OpenRAM/compiler/example_config_scn4m_subm.py

word_size = 2
num_words = 16

tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [ 5.0 ]
temperatures = [ 25 ]

output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

#Setting for multiport
netlist_only = True
bitcell = "pbitcell"
replica_bitcell="replica_pbitcell"
num_rw_ports = 1
num_r_ports = 1
num_w_ports = 1
Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 19:24:44 +01:00			`word_size = 2`
RELEASE 1.0 2016-11-08 18:57:35 +01:00			`num_words = 16`

Remove scn3me lib files. Remove bank references. 2018-09-24 20:28:43 +02:00			`tech_name = "scn4m_subm"`
Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 20:22:47 +01:00			`process_corners = ["TT"]`
Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-10 00:33:03 +01:00			`supply_voltages = [ 5.0 ]`
Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 20:22:47 +01:00			`temperatures = [ 25 ]`
Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-10 00:33:03 +01:00
Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-20 01:38:19 +01:00			`output_path = "temp"`
Remove banks from example configs 2018-10-12 19:23:34 +02:00			`output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)`
Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-23 04:04:42 +02:00
			`#Setting for multiport`
Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-23 21:55:54 +02:00			`netlist_only = True`
			`bitcell = "pbitcell"`
			`replica_bitcell="replica_pbitcell"`
			`num_rw_ports = 1`
Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 09:08:05 +02:00			`num_r_ports = 1`
Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-23 21:55:54 +02:00			`num_w_ports = 1`