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add LC oscillator

This commit is contained in:
Phillip Ferreira Baade-Pedersen 2025-11-18 14:17:02 +01:00
parent 1567a3ce0c
commit ecce5eea7c
842 changed files with 44458 additions and 20 deletions
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BIN
modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-312.pyc Normal file
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8
modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch
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@ -1,8 +1,9 @@
v {xschem version=3.4.6 file_version=1.2}
v {xschem version=3.4.8RC file_version=1.3}
G {}
K {}
V {}
S {}
F {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
@ -19,6 +20,7 @@ N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.param A=0
.control
set noaskquit
set numdgt=12
@ -62,10 +64,10 @@ C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
.include CACE\{DUT_path\}
.temp CACE\{temperature\}
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb_0.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.952325246460e-01
1.728000000000e-10 -6.043942197180e-02
1.828000000000e-10 1.817064006720e-01
1.928000000000e-10 3.985392356515e-01
2.028000000000e-10 5.562505249699e-01
2.128000000000e-10 6.572874178466e-01
2.228000000000e-10 7.087352858161e-01
2.328000000000e-10 7.029522511861e-01
2.428000000000e-10 6.344368312078e-01
2.528000000000e-10 5.013241237787e-01
2.628000000000e-10 3.030080742176e-01
2.728000000000e-10 6.578821975767e-02
2.828000000000e-10 -1.781586778972e-01
2.928000000000e-10 -3.964040373443e-01
3.028000000000e-10 -5.555461653242e-01
3.128000000000e-10 -6.571022283471e-01
3.228000000000e-10 -7.092808909864e-01
3.328000000000e-10 -7.040843150938e-01
3.428000000000e-10 -6.362469325195e-01
3.528000000000e-10 -5.032364212786e-01
3.628000000000e-10 -3.051350358226e-01
3.728000000000e-10 -6.762904380973e-02
3.828000000000e-10 1.763878132349e-01
3.928000000000e-10 3.951284969670e-01
4.028000000000e-10 5.545978983505e-01
4.128000000000e-10 6.566315830069e-01
4.228000000000e-10 7.089962487465e-01
4.328000000000e-10 7.042633111532e-01
4.428000000000e-10 6.365365170049e-01
4.528000000000e-10 5.037912579488e-01
4.628000000000e-10 3.056253251435e-01
4.728000000000e-10 6.823087043489e-02
4.828000000000e-10 -1.759620590786e-01
4.928000000000e-10 -3.946766675460e-01
5.028000000000e-10 -5.543918551335e-01
5.128000000000e-10 -6.564106038653e-01
5.228000000000e-10 -7.089804674794e-01
5.328000000000e-10 -7.042284637667e-01
5.428000000000e-10 -6.366831677063e-01
5.528000000000e-10 -5.038654128054e-01
5.628000000000e-10 -3.058301627321e-01
5.728000000000e-10 -6.832081314378e-02
5.828000000000e-10 1.757744687450e-01
5.928000000000e-10 3.946207346164e-01
6.028000000000e-10 5.542681653143e-01
6.128000000000e-10 6.564162326939e-01
6.228000000000e-10 7.089102158365e-01
6.328000000000e-10 7.042850183822e-01
6.428000000000e-10 6.366586213363e-01
6.528000000000e-10 5.039505543903e-01
6.628000000000e-10 3.058219717524e-01
6.728000000000e-10 6.840961740524e-02
6.828000000000e-10 -1.757862033444e-01
6.928000000000e-10 -3.945467987447e-01
7.028000000000e-10 -5.542929102277e-01
7.128000000000e-10 -6.563603422698e-01
7.228000000000e-10 -7.089481650220e-01
7.328000000000e-10 -7.042424683005e-01
7.428000000000e-10 -6.367078290897e-01
7.528000000000e-10 -5.039165471509e-01
7.628000000000e-10 -3.058753018579e-01
7.728000000000e-10 -6.837707225292e-02
7.828000000000e-10 1.757345833407e-01
7.928000000000e-10 3.945785215449e-01
8.028000000000e-10 5.542482652542e-01
8.128000000000e-10 6.563959408481e-01
8.228000000000e-10 7.089082113076e-01
8.328000000000e-10 7.042817797830e-01
8.428000000000e-10 6.366719399828e-01
8.528000000000e-10 5.039573608246e-01
8.628000000000e-10 3.058408732486e-01
8.728000000000e-10 6.841772818469e-02
8.828000000000e-10 -1.757686495942e-01
8.928000000000e-10 -3.945419964750e-01
9.028000000000e-10 -5.542809328797e-01
9.128000000000e-10 -6.563614885531e-01
9.228000000000e-10 -7.089411806967e-01
9.328000000000e-10 -7.042479976407e-01
9.428000000000e-10 -6.367051444468e-01
9.528000000000e-10 -5.039245834310e-01
9.628000000000e-10 -3.058742220339e-01
9.728000000000e-10 -6.838526492007e-02
9.828000000000e-10 1.757358039920e-01
9.928000000000e-10 3.945718167364e-01
1.000000000000e-09 5.155910006549e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 0
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00
temperature: '-40'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/.spiceinit Normal file
View File

@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb_1.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.647956442563e-01
1.728000000000e-10 -3.672466403620e-02
1.828000000000e-10 1.978055322165e-01
1.928000000000e-10 4.056017943518e-01
2.028000000000e-10 5.547344088879e-01
2.128000000000e-10 6.487490848065e-01
2.228000000000e-10 6.923653634957e-01
2.328000000000e-10 6.780886353961e-01
2.428000000000e-10 6.039598047192e-01
2.528000000000e-10 4.698168410475e-01
2.628000000000e-10 2.751260896566e-01
2.728000000000e-10 4.430157580526e-02
2.828000000000e-10 -1.925038311834e-01
2.928000000000e-10 -4.023301580756e-01
3.028000000000e-10 -5.533152551340e-01
3.128000000000e-10 -6.481954476962e-01
3.228000000000e-10 -6.930655672739e-01
3.328000000000e-10 -6.800540209913e-01
3.428000000000e-10 -6.070129146880e-01
3.528000000000e-10 -4.732295235615e-01
3.628000000000e-10 -2.788311309623e-01
3.728000000000e-10 -4.769207273318e-02
3.828000000000e-10 1.893739393663e-01
3.928000000000e-10 3.999895682405e-01
4.028000000000e-10 5.516914161753e-01
4.128000000000e-10 6.473194453459e-01
4.228000000000e-10 6.926967113745e-01
4.328000000000e-10 6.804409619078e-01
4.428000000000e-10 6.077344291363e-01
4.528000000000e-10 4.743209278754e-01
4.628000000000e-10 2.799315218230e-01
4.728000000000e-10 4.887682675205e-02
4.828000000000e-10 -1.884058832182e-01
4.928000000000e-10 -3.991237321070e-01
5.028000000000e-10 -5.511979674959e-01
5.128000000000e-10 -6.469402879887e-01
5.228000000000e-10 -6.926225993557e-01
5.328000000000e-10 -6.804805060919e-01
5.428000000000e-10 -6.080204415279e-01
5.528000000000e-10 -4.745961817340e-01
5.628000000000e-10 -2.803459413605e-01
5.728000000000e-10 -4.918721233066e-02
5.828000000000e-10 1.880320213273e-01
5.928000000000e-10 3.989072784961e-01
6.028000000000e-10 5.509784832100e-01
6.128000000000e-10 6.468776696433e-01
6.228000000000e-10 6.925382949500e-01
6.328000000000e-10 6.805520167761e-01
6.428000000000e-10 6.080522625696e-01
6.528000000000e-10 4.747422384222e-01
6.628000000000e-10 2.804194075907e-01
6.728000000000e-10 4.934414267879e-02
6.828000000000e-10 -1.879699706397e-01
6.928000000000e-10 -3.987854446736e-01
7.028000000000e-10 -5.509613139230e-01
7.128000000000e-10 -6.468062697707e-01
7.228000000000e-10 -6.925630874809e-01
7.328000000000e-10 -6.805223964692e-01
7.428000000000e-10 -6.081132322697e-01
7.528000000000e-10 -4.747366406660e-01
7.628000000000e-10 -2.804933490724e-01
7.728000000000e-10 -4.934235519722e-02
7.828000000000e-10 1.879006367827e-01
7.928000000000e-10 3.987938070562e-01
8.028000000000e-10 5.509093463144e-01
8.128000000000e-10 6.468293959909e-01
8.228000000000e-10 6.925252291894e-01
8.328000000000e-10 6.805590879185e-01
8.428000000000e-10 6.080875904937e-01
8.528000000000e-10 4.747803907956e-01
8.628000000000e-10 2.804721530083e-01
8.728000000000e-10 4.938687520288e-02
8.828000000000e-10 -1.879222775604e-01
8.928000000000e-10 -3.987554695640e-01
9.028000000000e-10 -5.509333914335e-01
9.128000000000e-10 -6.467969990881e-01
9.228000000000e-10 -6.925530415231e-01
9.328000000000e-10 -6.805304150604e-01
9.428000000000e-10 -6.081187600045e-01
9.528000000000e-10 -4.747542418837e-01
9.628000000000e-10 -2.805045225794e-01
9.728000000000e-10 -4.936125388638e-02
9.828000000000e-10 1.878908530872e-01
9.928000000000e-10 3.987795364060e-01
1.000000000000e-09 5.142017254263e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 1
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ff
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01
temperature: '-40'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb_2.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -3.226907107526e-01
1.728000000000e-10 -8.539968284410e-02
1.828000000000e-10 1.614480909662e-01
1.928000000000e-10 3.869191924745e-01
2.028000000000e-10 5.540483396157e-01
2.128000000000e-10 6.620167995175e-01
2.228000000000e-10 7.202634748901e-01
2.328000000000e-10 7.212523007105e-01
2.428000000000e-10 6.566979396260e-01
2.528000000000e-10 5.250303609426e-01
2.628000000000e-10 3.265092852166e-01
2.728000000000e-10 8.707604756770e-02
2.828000000000e-10 -1.611600424348e-01
2.928000000000e-10 -3.873238626333e-01
3.028000000000e-10 -5.550746884823e-01
3.128000000000e-10 -6.629366269634e-01
3.228000000000e-10 -7.212894794449e-01
3.328000000000e-10 -7.220878341254e-01
3.428000000000e-10 -6.576651735802e-01
3.528000000000e-10 -5.257535323793e-01
3.628000000000e-10 -3.273054874384e-01
3.728000000000e-10 -8.759901468451e-02
3.828000000000e-10 1.605580394287e-01
3.928000000000e-10 3.869863823107e-01
4.028000000000e-10 5.547303069787e-01
4.128000000000e-10 6.628461833305e-01
4.228000000000e-10 7.211466820779e-01
4.328000000000e-10 7.221995653822e-01
4.428000000000e-10 6.577128147927e-01
4.528000000000e-10 5.259884868760e-01
4.628000000000e-10 3.274163471898e-01
4.728000000000e-10 8.784541550780e-02
4.828000000000e-10 -1.604682108624e-01
4.928000000000e-10 -3.867888973241e-01
5.028000000000e-10 -5.547066546217e-01
5.128000000000e-10 -6.627253094524e-01
5.228000000000e-10 -7.211826888209e-01
5.328000000000e-10 -7.221369141817e-01
5.428000000000e-10 -6.577994031943e-01
5.528000000000e-10 -5.259620192587e-01
5.628000000000e-10 -3.275201865204e-01
5.728000000000e-10 -8.782404636233e-02
5.828000000000e-10 1.603689538405e-01
5.928000000000e-10 3.868153343854e-01
6.028000000000e-10 5.546284247412e-01
6.128000000000e-10 6.627691182366e-01
6.228000000000e-10 7.211205707397e-01
6.328000000000e-10 7.221945096033e-01
6.428000000000e-10 6.577508134366e-01
6.528000000000e-10 5.260261908485e-01
6.628000000000e-10 3.274760111912e-01
6.728000000000e-10 8.788851273295e-02
6.828000000000e-10 -1.604138329037e-01
6.928000000000e-10 -3.867579820075e-01
7.028000000000e-10 -5.546733587088e-01
7.128000000000e-10 -6.627166397254e-01
7.228000000000e-10 -7.211676696649e-01
7.328000000000e-10 -7.221448613305e-01
7.428000000000e-10 -6.577993970261e-01
7.528000000000e-10 -5.259796511606e-01
7.628000000000e-10 -3.275252420812e-01
7.728000000000e-10 -8.784270745333e-02
7.828000000000e-10 1.603648729372e-01
7.928000000000e-10 3.868003178892e-01
8.028000000000e-10 5.546284703905e-01
8.128000000000e-10 6.627594909397e-01
8.228000000000e-10 7.211247368625e-01
8.328000000000e-10 7.221884517678e-01
8.428000000000e-10 6.577581123739e-01
8.528000000000e-10 5.260226393584e-01
8.628000000000e-10 3.274844581735e-01
8.728000000000e-10 8.788515759553e-02
8.828000000000e-10 -1.604054537172e-01
8.928000000000e-10 -3.867616376768e-01
9.028000000000e-10 -5.546662826942e-01
9.128000000000e-10 -6.627215467888e-01
9.228000000000e-10 -7.211618152183e-01
9.328000000000e-10 -7.221504122635e-01
9.428000000000e-10 -6.577943183983e-01
9.528000000000e-10 -5.259856282734e-01
9.628000000000e-10 -3.275204867996e-01
9.728000000000e-10 -8.784851998896e-02
9.828000000000e-10 1.603694682536e-01
9.928000000000e-10 3.867951846118e-01
1.000000000000e-09 5.139507493642e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 2
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ss
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02
temperature: '-40'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 27
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb_3.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.752371518652e-01
1.728000000000e-10 -5.371376319542e-02
1.828000000000e-10 1.789877413053e-01
1.928000000000e-10 3.904548691103e-01
2.028000000000e-10 5.481842948229e-01
2.128000000000e-10 6.473880529986e-01
2.228000000000e-10 6.910106576952e-01
2.328000000000e-10 6.747515328639e-01
2.428000000000e-10 5.993982850131e-01
2.528000000000e-10 4.678235295331e-01
2.628000000000e-10 2.811940191144e-01
2.728000000000e-10 5.749892092429e-02
2.828000000000e-10 -1.768703468756e-01
2.928000000000e-10 -3.894327299011e-01
3.028000000000e-10 -5.481462871223e-01
3.128000000000e-10 -6.476233959034e-01
3.228000000000e-10 -6.918267741740e-01
3.328000000000e-10 -6.759891610513e-01
3.428000000000e-10 -6.011477081233e-01
3.528000000000e-10 -4.695436066175e-01
3.628000000000e-10 -2.830251877311e-01
3.728000000000e-10 -5.907673776650e-02
3.828000000000e-10 1.753349861707e-01
3.928000000000e-10 3.883274219019e-01
4.028000000000e-10 5.473035177189e-01
4.128000000000e-10 6.472356324664e-01
4.228000000000e-10 6.916308158427e-01
4.328000000000e-10 6.762268077787e-01
4.428000000000e-10 6.014684070962e-01
4.528000000000e-10 4.700895666681e-01
4.628000000000e-10 2.834862741746e-01
4.728000000000e-10 5.964855757083e-02
4.828000000000e-10 -1.749274761915e-01
4.928000000000e-10 -3.878897710558e-01
5.028000000000e-10 -5.470986037433e-01
5.128000000000e-10 -6.470272164409e-01
5.228000000000e-10 -6.916322065746e-01
5.328000000000e-10 -6.762158687864e-01
5.428000000000e-10 -6.016311330158e-01
5.528000000000e-10 -4.701782346337e-01
5.628000000000e-10 -2.836941639082e-01
5.728000000000e-10 -5.974768838544e-02
5.828000000000e-10 1.747352099095e-01
5.928000000000e-10 3.878245260251e-01
6.028000000000e-10 5.469715931678e-01
6.128000000000e-10 6.470284806517e-01
6.228000000000e-10 6.915679621080e-01
6.328000000000e-10 6.762768333485e-01
6.428000000000e-10 6.016163496453e-01
6.528000000000e-10 4.702674812943e-01
6.628000000000e-10 2.836938506434e-01
6.728000000000e-10 5.983990401354e-02
6.828000000000e-10 -1.747391664584e-01
6.928000000000e-10 -3.877472828580e-01
7.028000000000e-10 -5.469903889528e-01
7.128000000000e-10 -6.469730360721e-01
7.228000000000e-10 -6.916047287716e-01
7.328000000000e-10 -6.762386026180e-01
7.428000000000e-10 -6.016669907082e-01
7.528000000000e-10 -4.702390118128e-01
7.628000000000e-10 -2.837481181728e-01
7.728000000000e-10 -5.981248689037e-02
7.828000000000e-10 1.746867337354e-01
7.928000000000e-10 3.877749638679e-01
8.028000000000e-10 5.469462314077e-01
8.128000000000e-10 6.470055622974e-01
8.228000000000e-10 6.915665740520e-01
8.328000000000e-10 6.762766371031e-01
8.428000000000e-10 6.016337946720e-01
8.528000000000e-10 4.702787360349e-01
8.628000000000e-10 2.837166478210e-01
8.728000000000e-10 5.985233152723e-02
8.828000000000e-10 -1.747180248353e-01
8.928000000000e-10 -3.877389392165e-01
9.028000000000e-10 -5.469764940938e-01
9.128000000000e-10 -6.469724949526e-01
9.228000000000e-10 -6.915980610397e-01
9.328000000000e-10 -6.762447762615e-01
9.428000000000e-10 -6.016660865709e-01
9.528000000000e-10 -4.702484057793e-01
9.628000000000e-10 -2.837489236123e-01
9.728000000000e-10 -5.982216431619e-02
9.828000000000e-10 1.746862818107e-01
9.928000000000e-10 3.877670239311e-01
1.000000000000e-09 5.084292112944e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 3
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03
temperature: '27'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 27
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb_4.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.482257947455e-01
1.728000000000e-10 -3.259266550035e-02
1.828000000000e-10 1.930322087844e-01
1.928000000000e-10 3.960886599474e-01
2.028000000000e-10 5.450058997505e-01
2.128000000000e-10 6.360387116800e-01
2.228000000000e-10 6.712975422190e-01
2.328000000000e-10 6.474938983982e-01
2.428000000000e-10 5.679706274704e-01
2.528000000000e-10 4.364781736218e-01
2.628000000000e-10 2.536409133725e-01
2.728000000000e-10 3.555786929817e-02
2.828000000000e-10 -1.919150168478e-01
2.928000000000e-10 -3.960490843585e-01
3.028000000000e-10 -5.456465197220e-01
3.128000000000e-10 -6.367232933250e-01
3.228000000000e-10 -6.725166925877e-01
3.328000000000e-10 -6.491812984547e-01
3.428000000000e-10 -5.701612342484e-01
3.528000000000e-10 -4.386195239579e-01
3.628000000000e-10 -2.558666299298e-01
3.728000000000e-10 -3.750940439386e-02
3.828000000000e-10 1.900731677010e-01
3.928000000000e-10 3.947279065049e-01
4.028000000000e-10 5.446879536498e-01
4.128000000000e-10 6.362937598492e-01
4.228000000000e-10 6.723764816130e-01
4.328000000000e-10 6.495551727740e-01
4.428000000000e-10 5.706690754638e-01
4.528000000000e-10 4.393690386281e-01
4.628000000000e-10 2.565445890136e-01
4.728000000000e-10 3.828939038748e-02
4.828000000000e-10 -1.894747026650e-01
4.928000000000e-10 -3.941469427019e-01
5.028000000000e-10 -5.443881652157e-01
5.128000000000e-10 -6.360424686566e-01
5.228000000000e-10 -6.723795425302e-01
5.328000000000e-10 -6.495951074105e-01
5.428000000000e-10 -5.709049111673e-01
5.528000000000e-10 -4.395480856777e-01
5.628000000000e-10 -2.568451405700e-01
5.728000000000e-10 -3.848386295174e-02
5.828000000000e-10 1.891998017504e-01
5.928000000000e-10 3.940128253458e-01
6.028000000000e-10 5.442195759360e-01
6.128000000000e-10 6.360190076123e-01
6.228000000000e-10 6.723154692419e-01
6.328000000000e-10 6.496722035130e-01
6.428000000000e-10 5.709215560836e-01
6.528000000000e-10 4.396716365902e-01
6.628000000000e-10 2.568848555761e-01
6.728000000000e-10 3.861258812938e-02
6.828000000000e-10 -1.891673406027e-01
6.928000000000e-10 -3.939096487469e-01
7.028000000000e-10 -5.442185154541e-01
7.128000000000e-10 -6.359555029215e-01
7.228000000000e-10 -6.723494769467e-01
7.328000000000e-10 -6.496420384079e-01
7.428000000000e-10 -5.709822816025e-01
7.528000000000e-10 -4.396582995671e-01
7.628000000000e-10 -2.569529185106e-01
7.728000000000e-10 -3.860128053097e-02
7.828000000000e-10 1.891028165048e-01
7.928000000000e-10 3.939252197739e-01
8.028000000000e-10 5.441685861906e-01
8.128000000000e-10 6.359828023137e-01
8.228000000000e-10 6.723118712615e-01
8.328000000000e-10 6.496812709937e-01
8.428000000000e-10 5.709544657577e-01
8.528000000000e-10 4.397022527784e-01
8.628000000000e-10 2.569280980597e-01
8.728000000000e-10 3.864565597286e-02
8.828000000000e-10 -1.891278298806e-01
8.928000000000e-10 -3.938862165142e-01
9.028000000000e-10 -5.441949734698e-01
9.128000000000e-10 -6.359493781265e-01
9.228000000000e-10 -6.723420888760e-01
9.328000000000e-10 -6.496512561522e-01
9.428000000000e-10 -5.709874488604e-01
9.528000000000e-10 -4.396746422576e-01
9.628000000000e-10 -2.569616958772e-01
9.728000000000e-10 -3.861839939192e-02
9.828000000000e-10 1.890951489097e-01
9.928000000000e-10 3.939119089870e-01
1.000000000000e-09 5.081084039478e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 4
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ff
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04
temperature: '27'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 27
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb_5.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -3.026592886865e-01
1.728000000000e-10 -8.046058591213e-02
1.828000000000e-10 1.560684489845e-01
1.928000000000e-10 3.758215815324e-01
2.028000000000e-10 5.441825187720e-01
2.128000000000e-10 6.527787402061e-01
2.228000000000e-10 7.054162779080e-01
2.328000000000e-10 6.966940307878e-01
2.428000000000e-10 6.251719997267e-01
2.528000000000e-10 4.948986245243e-01
2.628000000000e-10 3.088338841037e-01
2.728000000000e-10 8.463582249819e-02
2.828000000000e-10 -1.534379373390e-01
2.928000000000e-10 -3.742382678981e-01
3.028000000000e-10 -5.437587344983e-01
3.128000000000e-10 -6.527795869025e-01
3.228000000000e-10 -7.060578401775e-01
3.328000000000e-10 -6.977288800308e-01
3.428000000000e-10 -6.267241220561e-01
3.528000000000e-10 -4.964034573067e-01
3.628000000000e-10 -3.104523257846e-01
3.728000000000e-10 -8.599843693100e-02
3.828000000000e-10 1.520614001089e-01
3.928000000000e-10 3.732327292359e-01
4.028000000000e-10 5.429530946109e-01
4.128000000000e-10 6.523997728799e-01
4.228000000000e-10 7.058202145507e-01
4.328000000000e-10 6.979022558405e-01
4.428000000000e-10 6.269588593419e-01
4.528000000000e-10 4.968624227466e-01
4.628000000000e-10 3.108132149603e-01
4.728000000000e-10 8.648038785746e-02
4.828000000000e-10 -1.517384677919e-01
4.928000000000e-10 -3.728474794484e-01
5.028000000000e-10 -5.427866011842e-01
5.128000000000e-10 -6.522022614009e-01
5.228000000000e-10 -7.058208822479e-01
5.328000000000e-10 -6.978651082200e-01
5.428000000000e-10 -6.270935668997e-01
5.528000000000e-10 -4.969096569281e-01
5.628000000000e-10 -3.109835748750e-01
5.728000000000e-10 -8.653572716924e-02
5.828000000000e-10 1.515778681972e-01
5.928000000000e-10 3.728127447205e-01
6.028000000000e-10 5.426739415091e-01
6.128000000000e-10 6.522162007318e-01
6.228000000000e-10 7.057544179932e-01
6.328000000000e-10 6.979224304337e-01
6.428000000000e-10 6.270641898671e-01
6.528000000000e-10 4.969874144680e-01
6.628000000000e-10 3.109648292365e-01
6.728000000000e-10 8.661535651254e-02
6.828000000000e-10 -1.515990397030e-01
6.928000000000e-10 -3.727433125293e-01
7.028000000000e-10 -5.427028559119e-01
7.128000000000e-10 -6.521615488134e-01
7.228000000000e-10 -7.057946841560e-01
7.328000000000e-10 -6.978790263426e-01
7.428000000000e-10 -6.271133848792e-01
7.528000000000e-10 -4.969513861012e-01
7.628000000000e-10 -3.110159233563e-01
7.728000000000e-10 -8.658006676818e-02
7.828000000000e-10 1.515487071721e-01
7.928000000000e-10 3.727772980737e-01
8.028000000000e-10 5.426589701450e-01
8.128000000000e-10 6.521979789832e-01
8.228000000000e-10 7.057547305503e-01
8.328000000000e-10 6.979187185021e-01
8.428000000000e-10 6.270767072939e-01
8.528000000000e-10 4.969913946096e-01
8.628000000000e-10 3.109805885282e-01
8.728000000000e-10 8.662004567696e-02
8.828000000000e-10 -1.515841004471e-01
8.928000000000e-10 -3.727405314049e-01
9.028000000000e-10 -5.426922302859e-01
9.128000000000e-10 -6.521632231968e-01
9.228000000000e-10 -7.057882763540e-01
9.328000000000e-10 -6.978845659833e-01
9.428000000000e-10 -6.271103709374e-01
9.528000000000e-10 -4.969587868574e-01
9.628000000000e-10 -3.110138943909e-01
9.728000000000e-10 -8.658760475646e-02
9.828000000000e-10 1.515508999036e-01
9.928000000000e-10 3.727707590510e-01
1.000000000000e-09 5.012730784879e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 5
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ss
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05
temperature: '27'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 80
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb_6.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.658991355482e-01
1.728000000000e-10 -5.658971746101e-02
1.828000000000e-10 1.665652322471e-01
1.928000000000e-10 3.726189743475e-01
2.028000000000e-10 5.303705116758e-01
2.128000000000e-10 6.287796796090e-01
2.228000000000e-10 6.685380236864e-01
2.328000000000e-10 6.490234756137e-01
2.428000000000e-10 5.737092070140e-01
2.528000000000e-10 4.474825535463e-01
2.628000000000e-10 2.725242795062e-01
2.728000000000e-10 6.117177433707e-02
2.828000000000e-10 -1.637031734923e-01
2.928000000000e-10 -3.708935568747e-01
3.028000000000e-10 -5.297756369707e-01
3.128000000000e-10 -6.287017384995e-01
3.228000000000e-10 -6.693265533929e-01
3.328000000000e-10 -6.504570398323e-01
3.428000000000e-10 -5.758168078022e-01
3.528000000000e-10 -4.496242973413e-01
3.628000000000e-10 -2.747981275605e-01
3.728000000000e-10 -6.319393908833e-02
3.828000000000e-10 1.617439470913e-01
3.928000000000e-10 3.694169588634e-01
4.028000000000e-10 5.286499307585e-01
4.128000000000e-10 6.281722098808e-01
4.228000000000e-10 6.691184385543e-01
4.328000000000e-10 6.507901751637e-01
4.428000000000e-10 5.762974118946e-01
4.528000000000e-10 4.503608294114e-01
4.628000000000e-10 2.754522690623e-01
4.728000000000e-10 6.396306731359e-02
4.828000000000e-10 -1.611542650007e-01
4.928000000000e-10 -3.688169747432e-01
5.028000000000e-10 -5.283292872594e-01
5.128000000000e-10 -6.279003852563e-01
5.228000000000e-10 -6.691136918962e-01
5.328000000000e-10 -6.508124831570e-01
5.428000000000e-10 -5.765249280825e-01
5.528000000000e-10 -4.505225248069e-01
5.628000000000e-10 -2.757393848954e-01
5.728000000000e-10 -6.413835118523e-02
5.828000000000e-10 1.608879015274e-01
5.928000000000e-10 3.686909867212e-01
6.028000000000e-10 5.281558224884e-01
6.128000000000e-10 6.278785795680e-01
6.228000000000e-10 6.690442760911e-01
6.328000000000e-10 6.508870303825e-01
6.428000000000e-10 5.765321271449e-01
6.528000000000e-10 4.506407637839e-01
6.628000000000e-10 2.757670228304e-01
6.728000000000e-10 6.426080532693e-02
6.828000000000e-10 -1.608659404084e-01
6.928000000000e-10 -3.685888330346e-01
7.028000000000e-10 -5.281591419234e-01
7.128000000000e-10 -6.278127091451e-01
7.228000000000e-10 -6.690805910819e-01
7.328000000000e-10 -6.508520944992e-01
7.428000000000e-10 -5.765925476372e-01
7.528000000000e-10 -4.506215704207e-01
7.628000000000e-10 -2.758332595929e-01
7.728000000000e-10 -6.424327491403e-02
7.828000000000e-10 1.608024320318e-01
7.928000000000e-10 3.686091606456e-01
8.028000000000e-10 5.281080947303e-01
8.128000000000e-10 6.278426474070e-01
8.228000000000e-10 6.690409470235e-01
8.328000000000e-10 6.508923982303e-01
8.428000000000e-10 5.765614162070e-01
8.528000000000e-10 4.506656063053e-01
8.628000000000e-10 2.758047260180e-01
8.728000000000e-10 6.428762429922e-02
8.828000000000e-10 -1.608310872580e-01
8.928000000000e-10 -3.685690211775e-01
9.028000000000e-10 -5.281370864240e-01
9.128000000000e-10 -6.278075066251e-01
9.228000000000e-10 -6.690730291835e-01
9.328000000000e-10 -6.508603444096e-01
9.428000000000e-10 -5.765956636587e-01
9.528000000000e-10 -4.506359555730e-01
9.628000000000e-10 -2.758391852585e-01
9.728000000000e-10 -6.425829353036e-02
9.828000000000e-10 1.607973448132e-01
9.928000000000e-10 3.685968285070e-01
1.000000000000e-09 4.894958047088e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_divider.sym Normal file
View File

@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 6
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06
temperature: '80'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 80
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb_7.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.411371086013e-01
1.728000000000e-10 -3.745255924116e-02
1.828000000000e-10 1.789428987452e-01
1.928000000000e-10 3.769558934840e-01
2.028000000000e-10 5.255858783541e-01
2.128000000000e-10 6.150086513683e-01
2.228000000000e-10 6.463506095909e-01
2.328000000000e-10 6.202014565113e-01
2.428000000000e-10 5.417075102450e-01
2.528000000000e-10 4.161519970610e-01
2.628000000000e-10 2.448960905686e-01
2.728000000000e-10 3.892968213965e-02
2.828000000000e-10 -1.791505445505e-01
2.928000000000e-10 -3.778686664383e-01
3.028000000000e-10 -5.268093330033e-01
3.128000000000e-10 -6.159877416348e-01
3.228000000000e-10 -6.476195951568e-01
3.328000000000e-10 -6.216667221790e-01
3.428000000000e-10 -5.435382878554e-01
3.528000000000e-10 -4.178448923887e-01
3.628000000000e-10 -2.466531390426e-01
3.728000000000e-10 -4.041876256606e-02
3.828000000000e-10 1.777092594525e-01
3.928000000000e-10 3.768542192180e-01
4.028000000000e-10 5.260351926041e-01
4.128000000000e-10 6.156923491854e-01
4.228000000000e-10 6.475364165656e-01
4.328000000000e-10 6.220253224816e-01
4.428000000000e-10 5.439681165412e-01
4.528000000000e-10 4.184919515643e-01
4.628000000000e-10 2.472032785778e-01
4.728000000000e-10 4.108392377197e-02
4.828000000000e-10 -1.772209974541e-01
4.928000000000e-10 -3.763464849454e-01
5.028000000000e-10 -5.257893585276e-01
5.128000000000e-10 -6.154751208437e-01
5.228000000000e-10 -6.475677164184e-01
5.328000000000e-10 -6.220637777790e-01
5.428000000000e-10 -5.441970040997e-01
5.528000000000e-10 -4.186454653208e-01
5.628000000000e-10 -2.474812841152e-01
5.728000000000e-10 -4.124875776275e-02
5.828000000000e-10 1.769646369358e-01
5.928000000000e-10 3.762321495571e-01
6.028000000000e-10 5.256270530622e-01
6.128000000000e-10 6.154644314175e-01
6.228000000000e-10 6.475079392204e-01
6.328000000000e-10 6.221477255403e-01
6.428000000000e-10 5.442104878297e-01
6.528000000000e-10 4.187701859554e-01
6.628000000000e-10 2.475138621783e-01
6.728000000000e-10 4.137738638918e-02
6.828000000000e-10 -1.769383615791e-01
6.928000000000e-10 -3.761265802968e-01
7.028000000000e-10 -5.256298366366e-01
7.128000000000e-10 -6.153992750277e-01
7.228000000000e-10 -6.475476374408e-01
7.328000000000e-10 -6.221164421539e-01
7.428000000000e-10 -5.442762390873e-01
7.528000000000e-10 -4.187551150856e-01
7.628000000000e-10 -2.475858208222e-01
7.728000000000e-10 -4.136415856981e-02
7.828000000000e-10 1.768699557901e-01
7.928000000000e-10 3.761440347995e-01
8.028000000000e-10 5.255765528630e-01
8.128000000000e-10 6.154291154928e-01
8.228000000000e-10 6.475082015932e-01
8.328000000000e-10 6.221591874056e-01
8.428000000000e-10 5.442468649409e-01
8.528000000000e-10 4.188025713318e-01
8.628000000000e-10 2.475593730203e-01
8.728000000000e-10 4.141194467582e-02
8.828000000000e-10 -1.768965906206e-01
8.928000000000e-10 -3.761014263264e-01
9.028000000000e-10 -5.256047249426e-01
9.128000000000e-10 -6.153930400649e-01
9.228000000000e-10 -6.475410523019e-01
9.328000000000e-10 -6.221273229309e-01
9.428000000000e-10 -5.442828742825e-01
9.528000000000e-10 -4.187734552047e-01
9.628000000000e-10 -2.475958588134e-01
9.728000000000e-10 -4.138326223977e-02
9.828000000000e-10 1.768611473522e-01
9.928000000000e-10 3.761288017358e-01
1.000000000000e-09 4.898465656484e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 7
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ff
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07
temperature: '80'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 80
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb_8.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -2.915574653990e-01
1.728000000000e-10 -8.207206468644e-02
1.828000000000e-10 1.443140454917e-01
1.928000000000e-10 3.578501059917e-01
2.028000000000e-10 5.264102614641e-01
2.128000000000e-10 6.356033847750e-01
2.228000000000e-10 6.852124516173e-01
2.328000000000e-10 6.731697751231e-01
2.428000000000e-10 6.014680860110e-01
2.528000000000e-10 4.762934940598e-01
2.628000000000e-10 3.019743151843e-01
2.728000000000e-10 9.052768843264e-02
2.828000000000e-10 -1.376882496508e-01
2.928000000000e-10 -3.528073773591e-01
3.028000000000e-10 -5.234244166185e-01
3.128000000000e-10 -6.340851318675e-01
3.228000000000e-10 -6.854084589569e-01
3.328000000000e-10 -6.747695956588e-01
3.428000000000e-10 -6.042844418494e-01
3.528000000000e-10 -4.793995649692e-01
3.628000000000e-10 -3.052822644166e-01
3.728000000000e-10 -9.358407685982e-02
3.828000000000e-10 1.347194202511e-01
3.928000000000e-10 3.504174847188e-01
4.028000000000e-10 5.215924623562e-01
4.128000000000e-10 6.330900225454e-01
4.228000000000e-10 6.849701135730e-01
4.328000000000e-10 6.751037342439e-01
4.428000000000e-10 6.049384750133e-01
4.528000000000e-10 4.803914109079e-01
4.628000000000e-10 3.062148923158e-01
4.728000000000e-10 9.463220881739e-02
4.828000000000e-10 -1.338572933423e-01
4.928000000000e-10 -3.495689260045e-01
5.028000000000e-10 -5.210792449240e-01
5.128000000000e-10 -6.326887195405e-01
5.228000000000e-10 -6.848983576670e-01
5.328000000000e-10 -6.751198274713e-01
5.428000000000e-10 -6.052060952211e-01
5.528000000000e-10 -4.806148207689e-01
5.628000000000e-10 -3.065686575138e-01
5.728000000000e-10 -9.487468231530e-02
5.828000000000e-10 1.335246601606e-01
5.928000000000e-10 3.493821792388e-01
6.028000000000e-10 5.208575371198e-01
6.128000000000e-10 6.326338805716e-01
6.228000000000e-10 6.848108600046e-01
6.328000000000e-10 6.751907109187e-01
6.428000000000e-10 6.052214841565e-01
6.528000000000e-10 4.807458450129e-01
6.628000000000e-10 3.066111422989e-01
6.728000000000e-10 9.501122064621e-02
6.828000000000e-10 -1.334882175614e-01
6.928000000000e-10 -3.492660352924e-01
7.028000000000e-10 -5.208495294585e-01
7.128000000000e-10 -6.325598499367e-01
7.228000000000e-10 -6.848421004985e-01
7.328000000000e-10 -6.751543080912e-01
7.428000000000e-10 -6.052828258645e-01
7.528000000000e-10 -4.807293659120e-01
7.628000000000e-10 -3.066794924108e-01
7.728000000000e-10 -9.499664108150e-02
7.828000000000e-10 1.334220275121e-01
7.928000000000e-10 3.492835018463e-01
8.028000000000e-10 5.207961769649e-01
8.128000000000e-10 6.325876998525e-01
8.228000000000e-10 6.848014468222e-01
8.328000000000e-10 6.751935994962e-01
8.428000000000e-10 6.052518981308e-01
8.528000000000e-10 4.807729857688e-01
8.628000000000e-10 3.066516205185e-01
8.728000000000e-10 9.504068447267e-02
8.828000000000e-10 -1.334502935734e-01
8.928000000000e-10 -3.492430994753e-01
9.028000000000e-10 -5.208246106410e-01
9.128000000000e-10 -6.325523513325e-01
9.228000000000e-10 -6.848328984481e-01
9.328000000000e-10 -6.751615848536e-01
9.428000000000e-10 -6.052856721640e-01
9.528000000000e-10 -4.807436971446e-01
9.628000000000e-10 -3.066854569150e-01
9.728000000000e-10 -9.501170247959e-02
9.828000000000e-10 1.334168358063e-01
9.928000000000e-10 3.492707284922e-01
1.000000000000e-09 4.787459694615e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_divider.sym Normal file
View File

@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 8
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ss
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08
temperature: '80'
vdd: '0.8'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb_9.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -5.397443385003e-01
1.728000000000e-10 -2.045536352810e-01
1.828000000000e-10 1.313863393294e-01
1.928000000000e-10 3.838209275603e-01
2.028000000000e-10 5.347375940933e-01
2.128000000000e-10 6.276591932156e-01
2.228000000000e-10 7.115621702194e-01
2.328000000000e-10 7.798611559065e-01
2.428000000000e-10 8.066497785728e-01
2.528000000000e-10 7.447444131165e-01
2.628000000000e-10 5.331798214247e-01
2.728000000000e-10 1.991243487461e-01
2.828000000000e-10 -1.352153251063e-01
2.928000000000e-10 -3.864762984078e-01
3.028000000000e-10 -5.369168929595e-01
3.128000000000e-10 -6.290603792866e-01
3.228000000000e-10 -7.126196515736e-01
3.328000000000e-10 -7.804415576126e-01
3.428000000000e-10 -8.071911048716e-01
3.528000000000e-10 -7.450481751688e-01
3.628000000000e-10 -5.336055963763e-01
3.728000000000e-10 -1.993198332358e-01
3.828000000000e-10 1.349559401886e-01
3.928000000000e-10 3.864112742700e-01
4.028000000000e-10 5.367351878370e-01
4.128000000000e-10 6.290489992071e-01
4.228000000000e-10 7.124864782962e-01
4.328000000000e-10 7.804750739895e-01
4.428000000000e-10 8.070933947437e-01
4.528000000000e-10 7.451033689318e-01
4.628000000000e-10 5.335168975820e-01
4.728000000000e-10 1.993807368925e-01
4.828000000000e-10 -1.350304895400e-01
4.928000000000e-10 -3.863532554681e-01
5.028000000000e-10 -5.368040585560e-01
5.128000000000e-10 -6.289909078772e-01
5.228000000000e-10 -7.125533448218e-01
5.328000000000e-10 -7.804160897110e-01
5.428000000000e-10 -8.071554863663e-01
5.528000000000e-10 -7.450422465689e-01
5.628000000000e-10 -5.335838460974e-01
5.728000000000e-10 -1.993167730115e-01
5.828000000000e-10 1.349726890253e-01
5.928000000000e-10 3.864109858256e-01
6.028000000000e-10 5.367479691018e-01
6.128000000000e-10 6.290476980128e-01
6.228000000000e-10 7.124950121919e-01
6.328000000000e-10 7.804717191606e-01
6.428000000000e-10 8.070994779138e-01
6.528000000000e-10 7.450975613250e-01
6.628000000000e-10 5.335259065522e-01
6.728000000000e-10 1.993734548210e-01
6.828000000000e-10 -1.350242777574e-01
6.928000000000e-10 -3.863605033303e-01
7.028000000000e-10 -5.367975294074e-01
7.128000000000e-10 -6.289982763959e-01
7.228000000000e-10 -7.125455111440e-01
7.328000000000e-10 -7.804238043085e-01
7.428000000000e-10 -8.071473680780e-01
7.528000000000e-10 -7.450494772754e-01
7.628000000000e-10 -5.335773499054e-01
7.728000000000e-10 -1.993230348361e-01
7.828000000000e-10 1.349793746975e-01
7.928000000000e-10 3.864055722387e-01
8.028000000000e-10 5.367539279153e-01
8.128000000000e-10 6.290427569852e-01
8.228000000000e-10 7.125002063044e-01
8.328000000000e-10 7.804668926767e-01
8.428000000000e-10 8.071042297758e-01
8.528000000000e-10 7.450922570276e-01
8.628000000000e-10 5.335323457615e-01
8.728000000000e-10 1.993673584870e-01
8.828000000000e-10 -1.350193573750e-01
8.928000000000e-10 -3.863660901230e-01
9.028000000000e-10 -5.367925035482e-01
9.128000000000e-10 -6.290039875175e-01
9.228000000000e-10 -7.125398122704e-01
9.328000000000e-10 -7.804294363608e-01
9.428000000000e-10 -8.071416857778e-01
9.528000000000e-10 -7.450548065452e-01
9.628000000000e-10 -5.335722743766e-01
9.728000000000e-10 -1.993280329539e-01
9.828000000000e-10 1.349843549639e-01
9.928000000000e-10 3.864011317450e-01
1.000000000000e-09 5.028020863733e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 9
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09
temperature: '-40'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb_10.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -5.293189432094e-01
1.728000000000e-10 -2.034299929592e-01
1.828000000000e-10 1.254532736892e-01
1.928000000000e-10 3.744603520131e-01
2.028000000000e-10 5.220595086358e-01
2.128000000000e-10 6.139346231694e-01
2.228000000000e-10 6.977077768020e-01
2.328000000000e-10 7.638951530454e-01
2.428000000000e-10 7.881008470503e-01
2.528000000000e-10 7.271434956617e-01
2.628000000000e-10 5.227259392947e-01
2.728000000000e-10 1.977807095317e-01
2.828000000000e-10 -1.296557480667e-01
2.928000000000e-10 -3.774966254092e-01
3.028000000000e-10 -5.245506032311e-01
3.128000000000e-10 -6.155925798862e-01
3.228000000000e-10 -6.989490114600e-01
3.328000000000e-10 -7.646204924296e-01
3.428000000000e-10 -7.887093478172e-01
3.528000000000e-10 -7.274783648153e-01
3.628000000000e-10 -5.231513423786e-01
3.728000000000e-10 -1.979863018154e-01
3.828000000000e-10 1.294013660930e-01
3.928000000000e-10 3.774276121382e-01
4.028000000000e-10 5.243833105689e-01
4.128000000000e-10 6.155813660155e-01
4.228000000000e-10 6.988272077165e-01
4.328000000000e-10 7.646509984988e-01
4.428000000000e-10 7.886185007607e-01
4.528000000000e-10 7.275266613790e-01
4.628000000000e-10 5.230676681296e-01
4.728000000000e-10 1.980405747385e-01
4.828000000000e-10 -1.294713662253e-01
4.928000000000e-10 -3.773761496757e-01
5.028000000000e-10 -5.244469821379e-01
5.128000000000e-10 -6.155294307936e-01
5.228000000000e-10 -6.988887956355e-01
5.328000000000e-10 -7.645972449904e-01
5.428000000000e-10 -7.886754254295e-01
5.528000000000e-10 -7.274706677122e-01
5.628000000000e-10 -5.231295350854e-01
5.728000000000e-10 -1.979806299381e-01
5.828000000000e-10 1.294187696545e-01
5.928000000000e-10 3.774292707563e-01
6.028000000000e-10 5.243961595933e-01
6.128000000000e-10 6.155814701559e-01
6.228000000000e-10 6.988355515168e-01
6.328000000000e-10 7.646484599731e-01
6.428000000000e-10 7.886243100181e-01
6.528000000000e-10 7.275215569265e-01
6.628000000000e-10 5.230764840752e-01
6.728000000000e-10 1.980332799823e-01
6.828000000000e-10 -1.294660192513e-01
6.928000000000e-10 -3.773827405650e-01
7.028000000000e-10 -5.244413520748e-01
7.128000000000e-10 -6.155361997798e-01
7.228000000000e-10 -6.988817029216e-01
7.328000000000e-10 -7.646043204444e-01
7.428000000000e-10 -7.886680576572e-01
7.528000000000e-10 -7.274772120684e-01
7.628000000000e-10 -5.231238849653e-01
7.728000000000e-10 -1.979860775160e-01
7.828000000000e-10 1.294249237809e-01
7.928000000000e-10 3.774244918330e-01
8.028000000000e-10 5.244015690321e-01
8.128000000000e-10 6.155771739165e-01
8.228000000000e-10 6.988402156207e-01
8.328000000000e-10 7.646441380646e-01
8.428000000000e-10 7.886285892332e-01
8.528000000000e-10 7.275167248781e-01
8.628000000000e-10 5.230825202638e-01
8.728000000000e-10 1.980273627479e-01
8.828000000000e-10 -1.294617038455e-01
8.928000000000e-10 -3.773878907236e-01
9.028000000000e-10 -5.244369215985e-01
9.128000000000e-10 -6.155414802599e-01
9.228000000000e-10 -6.988765421320e-01
9.328000000000e-10 -7.646094975483e-01
9.428000000000e-10 -7.886629049186e-01
9.528000000000e-10 -7.274820443091e-01
9.628000000000e-10 -5.231193961018e-01
9.728000000000e-10 -1.979905037884e-01
9.828000000000e-10 1.294294922144e-01
9.928000000000e-10 3.774205018001e-01
1.000000000000e-09 4.912603506308e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 10
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ff
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10
temperature: '-40'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb_11.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -5.473675478550e-01
1.728000000000e-10 -2.087893101739e-01
1.828000000000e-10 1.310494751476e-01
1.928000000000e-10 3.871555645678e-01
2.028000000000e-10 5.437689230363e-01
2.128000000000e-10 6.391330299748e-01
2.228000000000e-10 7.213082317981e-01
2.328000000000e-10 7.903248370025e-01
2.428000000000e-10 8.187618792919e-01
2.528000000000e-10 7.555729663838e-01
2.628000000000e-10 5.409345054541e-01
2.728000000000e-10 2.036912835862e-01
2.828000000000e-10 -1.345140506878e-01
2.928000000000e-10 -3.895370892644e-01
3.028000000000e-10 -5.457400052530e-01
3.128000000000e-10 -6.403498057265e-01
3.228000000000e-10 -7.222286336937e-01
3.328000000000e-10 -7.907911780827e-01
3.428000000000e-10 -8.192361080664e-01
3.528000000000e-10 -7.558198978931e-01
3.628000000000e-10 -5.413206307136e-01
3.728000000000e-10 -2.038438399825e-01
3.828000000000e-10 1.342763346632e-01
3.928000000000e-10 3.894921044587e-01
4.028000000000e-10 5.455616788274e-01
4.128000000000e-10 6.403489734683e-01
4.228000000000e-10 7.220944352324e-01
4.328000000000e-10 7.908322596821e-01
4.428000000000e-10 8.191363162855e-01
4.528000000000e-10 7.558824803046e-01
4.628000000000e-10 5.412307821184e-01
4.728000000000e-10 2.039121351986e-01
4.828000000000e-10 -1.343528713892e-01
4.928000000000e-10 -3.894290190191e-01
5.028000000000e-10 -5.456335562174e-01
5.128000000000e-10 -6.402860869065e-01
5.228000000000e-10 -7.221652152444e-01
5.328000000000e-10 -7.907686614943e-01
5.428000000000e-10 -8.192023796026e-01
5.528000000000e-10 -7.558173441778e-01
5.628000000000e-10 -5.413004970284e-01
5.728000000000e-10 -2.038447386050e-01
5.828000000000e-10 1.342913524064e-01
5.928000000000e-10 3.894897157728e-01
6.028000000000e-10 5.455737058766e-01
6.128000000000e-10 6.403462778603e-01
6.228000000000e-10 7.221032530671e-01
6.328000000000e-10 7.908278354740e-01
6.428000000000e-10 8.191430293573e-01
6.528000000000e-10 7.558759446864e-01
6.628000000000e-10 5.412396296665e-01
6.728000000000e-10 2.039046702204e-01
6.828000000000e-10 -1.343459163903e-01
6.928000000000e-10 -3.894366779769e-01
7.028000000000e-10 -5.456262483653e-01
7.128000000000e-10 -6.402940065215e-01
7.228000000000e-10 -7.221570137640e-01
7.328000000000e-10 -7.907769448806e-01
7.428000000000e-10 -8.191938542033e-01
7.528000000000e-10 -7.558251320231e-01
7.628000000000e-10 -5.412933191298e-01
7.728000000000e-10 -2.038518419443e-01
7.828000000000e-10 1.342982918430e-01
7.928000000000e-10 3.894837914532e-01
8.028000000000e-10 5.455799247329e-01
8.128000000000e-10 6.403408689327e-01
8.228000000000e-10 7.221089932485e-01
8.328000000000e-10 7.908225333386e-01
8.428000000000e-10 8.191482615363e-01
8.528000000000e-10 7.558702665648e-01
8.628000000000e-10 5.412462517638e-01
8.728000000000e-10 2.038984202104e-01
8.828000000000e-10 -1.343404705774e-01
8.928000000000e-10 -3.894425333092e-01
9.028000000000e-10 -5.456206778041e-01
9.128000000000e-10 -6.403000729433e-01
9.228000000000e-10 -7.221509667404e-01
9.328000000000e-10 -7.907829740936e-01
9.428000000000e-10 -8.191877974471e-01
9.528000000000e-10 -7.558308764830e-01
9.628000000000e-10 -5.412878201925e-01
9.728000000000e-10 -2.038573569097e-01
9.828000000000e-10 1.343035264203e-01
9.928000000000e-10 3.894790170617e-01
1.000000000000e-09 5.100069898815e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 11
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ss
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11
temperature: '-40'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 27
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb_12.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -5.049557277618e-01
1.728000000000e-10 -1.958466480437e-01
1.828000000000e-10 1.196319367700e-01
1.928000000000e-10 3.700244189406e-01
2.028000000000e-10 5.308067637731e-01
2.128000000000e-10 6.311299202315e-01
2.228000000000e-10 7.086540860403e-01
2.328000000000e-10 7.625529356493e-01
2.428000000000e-10 7.708473475114e-01
2.528000000000e-10 6.980446990655e-01
2.628000000000e-10 4.981026307256e-01
2.728000000000e-10 1.904449044265e-01
2.828000000000e-10 -1.236510258628e-01
2.928000000000e-10 -3.730975798774e-01
3.028000000000e-10 -5.333436235403e-01
3.128000000000e-10 -6.328422885796e-01
3.228000000000e-10 -7.099622515515e-01
3.328000000000e-10 -7.633093670089e-01
3.428000000000e-10 -7.714462858000e-01
3.528000000000e-10 -6.983543456334e-01
3.628000000000e-10 -4.984830350414e-01
3.728000000000e-10 -1.906133898346e-01
3.828000000000e-10 1.234140438752e-01
3.928000000000e-10 3.730258572177e-01
4.028000000000e-10 5.331667972487e-01
4.128000000000e-10 6.328214645319e-01
4.228000000000e-10 7.098336990067e-01
4.328000000000e-10 7.633335528675e-01
4.428000000000e-10 7.713603033543e-01
4.528000000000e-10 6.984040906368e-01
4.628000000000e-10 4.984087981115e-01
4.728000000000e-10 1.906698925098e-01
4.828000000000e-10 -1.234792426423e-01
4.928000000000e-10 -3.729733539485e-01
5.028000000000e-10 -5.332277682129e-01
5.128000000000e-10 -6.327690017914e-01
5.228000000000e-10 -7.098933602520e-01
5.328000000000e-10 -7.632805035294e-01
5.428000000000e-10 -7.714147767047e-01
5.528000000000e-10 -6.983493927960e-01
5.628000000000e-10 -4.984657326360e-01
5.728000000000e-10 -1.906133403657e-01
5.828000000000e-10 1.234275058651e-01
5.928000000000e-10 3.730246636548e-01
6.028000000000e-10 5.331775888699e-01
6.128000000000e-10 6.328197652536e-01
6.228000000000e-10 7.098419058182e-01
6.328000000000e-10 7.633301342197e-01
6.428000000000e-10 7.713661487972e-01
6.528000000000e-10 6.983986251010e-01
6.628000000000e-10 4.984160910452e-01
6.728000000000e-10 1.906635868460e-01
6.828000000000e-10 -1.234734747225e-01
6.928000000000e-10 -3.729797013887e-01
7.028000000000e-10 -5.332215969565e-01
7.128000000000e-10 -6.327757131741e-01
7.228000000000e-10 -7.098865351622e-01
7.328000000000e-10 -7.632871392149e-01
7.428000000000e-10 -7.714081948986e-01
7.528000000000e-10 -6.983555969606e-01
7.628000000000e-10 -4.984601688237e-01
7.728000000000e-10 -1.906192454806e-01
7.828000000000e-10 1.234332321656e-01
7.928000000000e-10 3.730195983111e-01
8.028000000000e-10 5.331826746949e-01
8.128000000000e-10 6.328151783475e-01
8.228000000000e-10 7.098466992587e-01
8.328000000000e-10 7.633256332241e-01
8.428000000000e-10 7.713705417094e-01
8.528000000000e-10 6.983937777920e-01
8.628000000000e-10 4.984215072239e-01
8.728000000000e-10 1.906583322627e-01
8.828000000000e-10 -1.234689419945e-01
8.928000000000e-10 -3.729845695752e-01
9.028000000000e-10 -5.332169477613e-01
9.128000000000e-10 -6.327807857544e-01
9.228000000000e-10 -7.098815617208e-01
9.328000000000e-10 -7.632920474235e-01
9.428000000000e-10 -7.714033753149e-01
9.528000000000e-10 -6.983602366678e-01
9.628000000000e-10 -4.984557776243e-01
9.728000000000e-10 -1.906237729891e-01
9.828000000000e-10 1.234375916302e-01
9.928000000000e-10 3.730155682884e-01
1.000000000000e-09 4.959193237551e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 12
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12
temperature: '27'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 27
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb_13.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -4.935497259980e-01
1.728000000000e-10 -1.928633983658e-01
1.828000000000e-10 1.160949240371e-01
1.928000000000e-10 3.619360857197e-01
2.028000000000e-10 5.185143131218e-01
2.128000000000e-10 6.170086772416e-01
2.228000000000e-10 6.939063598865e-01
2.328000000000e-10 7.457993341265e-01
2.428000000000e-10 7.520509596304e-01
2.528000000000e-10 6.804739824857e-01
2.628000000000e-10 4.870426149481e-01
2.728000000000e-10 1.875308246798e-01
2.828000000000e-10 -1.202389208092e-01
2.928000000000e-10 -3.651754434827e-01
3.028000000000e-10 -5.211918880427e-01
3.128000000000e-10 -6.188469707889e-01
3.228000000000e-10 -6.953072467312e-01
3.328000000000e-10 -7.466129151979e-01
3.428000000000e-10 -7.526565311823e-01
3.528000000000e-10 -6.807675409917e-01
3.628000000000e-10 -4.873945801883e-01
3.728000000000e-10 -1.876809763872e-01
3.828000000000e-10 1.200199744899e-01
3.928000000000e-10 3.651151173578e-01
4.028000000000e-10 5.210322421793e-01
4.128000000000e-10 6.188330192958e-01
4.228000000000e-10 6.951893716680e-01
4.328000000000e-10 7.466394998986e-01
4.428000000000e-10 7.525773069027e-01
4.528000000000e-10 6.808165070916e-01
4.628000000000e-10 4.873248087716e-01
4.728000000000e-10 1.877358679741e-01
4.828000000000e-10 -1.200819840902e-01
4.928000000000e-10 -3.650646413699e-01
5.028000000000e-10 -5.210903047408e-01
5.128000000000e-10 -6.187830156405e-01
5.228000000000e-10 -6.952462050643e-01
5.328000000000e-10 -7.465883056072e-01
5.428000000000e-10 -7.526293067125e-01
5.528000000000e-10 -6.807638103361e-01
5.628000000000e-10 -4.873795115625e-01
5.728000000000e-10 -1.876807689254e-01
5.828000000000e-10 1.200326256254e-01
5.928000000000e-10 3.651139754788e-01
6.028000000000e-10 5.210426454606e-01
6.128000000000e-10 6.188315227579e-01
6.228000000000e-10 6.951972695911e-01
6.328000000000e-10 7.466359762403e-01
6.428000000000e-10 7.525829976005e-01
6.528000000000e-10 6.808110143898e-01
6.628000000000e-10 4.873318873720e-01
6.728000000000e-10 1.877292356433e-01
6.828000000000e-10 -1.200767202072e-01
6.928000000000e-10 -3.650706499628e-01
7.028000000000e-10 -5.210847183857e-01
7.128000000000e-10 -6.187893543189e-01
7.228000000000e-10 -6.952399017798e-01
7.328000000000e-10 -7.465944604664e-01
7.428000000000e-10 -7.526232942576e-01
7.528000000000e-10 -6.807695137827e-01
7.628000000000e-10 -4.873744121182e-01
7.728000000000e-10 -1.876860880622e-01
7.828000000000e-10 1.200380835632e-01
7.928000000000e-10 3.651091778387e-01
8.028000000000e-10 5.210475167171e-01
8.128000000000e-10 6.188272213187e-01
8.228000000000e-10 6.952018279574e-01
8.328000000000e-10 7.466316140292e-01
8.428000000000e-10 7.525872528114e-01
8.528000000000e-10 6.808063071094e-01
8.628000000000e-10 4.873371355126e-01
8.728000000000e-10 1.877239857571e-01
8.828000000000e-10 -1.200724809112e-01
8.928000000000e-10 -3.650752679165e-01
9.028000000000e-10 -5.210804068397e-01
9.128000000000e-10 -6.187941569931e-01
9.228000000000e-10 -6.952352466105e-01
9.328000000000e-10 -7.465990720366e-01
9.428000000000e-10 -7.526188226163e-01
9.528000000000e-10 -6.807738360998e-01
9.628000000000e-10 -4.873703126609e-01
9.728000000000e-10 -1.876902725775e-01
9.828000000000e-10 1.200422409457e-01
9.928000000000e-10 3.651053453859e-01
1.000000000000e-09 4.847952698035e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 13
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ff
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13
temperature: '27'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 27
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb_14.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -5.133282675634e-01
1.728000000000e-10 -2.031582081928e-01
1.828000000000e-10 1.144804838339e-01
1.928000000000e-10 3.698591588516e-01
2.028000000000e-10 5.380258146680e-01
2.128000000000e-10 6.422542980920e-01
2.228000000000e-10 7.191574927620e-01
2.328000000000e-10 7.734390216007e-01
2.428000000000e-10 7.823512104827e-01
2.528000000000e-10 7.081342613122e-01
2.628000000000e-10 5.065809773945e-01
2.728000000000e-10 1.980707374060e-01
2.828000000000e-10 -1.181831896095e-01
2.928000000000e-10 -3.727163876319e-01
3.028000000000e-10 -5.404428949084e-01
3.128000000000e-10 -6.438704305572e-01
3.228000000000e-10 -7.204145434420e-01
3.328000000000e-10 -7.741471374370e-01
3.428000000000e-10 -7.829309638154e-01
3.528000000000e-10 -7.084110972821e-01
3.628000000000e-10 -5.069426471107e-01
3.728000000000e-10 -1.982066720174e-01
3.828000000000e-10 1.179564926067e-01
3.928000000000e-10 3.726621714283e-01
4.028000000000e-10 5.402630628674e-01
4.128000000000e-10 6.438601752956e-01
4.228000000000e-10 7.202791375194e-01
4.328000000000e-10 7.741793827377e-01
4.428000000000e-10 7.828380754967e-01
4.528000000000e-10 7.084693803333e-01
4.628000000000e-10 5.068627667504e-01
4.728000000000e-10 1.982719515445e-01
4.828000000000e-10 -1.180275895897e-01
4.928000000000e-10 -3.726028735362e-01
5.028000000000e-10 -5.403301024789e-01
5.128000000000e-10 -6.438008084190e-01
5.228000000000e-10 -7.203455420725e-01
5.328000000000e-10 -7.741198297783e-01
5.428000000000e-10 -7.828987326701e-01
5.528000000000e-10 -7.084084859242e-01
5.628000000000e-10 -5.069251044876e-01
5.728000000000e-10 -1.982094732584e-01
5.828000000000e-10 1.179697981212e-01
5.928000000000e-10 3.726595322461e-01
6.028000000000e-10 5.402739437431e-01
6.128000000000e-10 6.438573026479e-01
6.228000000000e-10 7.202880216174e-01
6.328000000000e-10 7.741750830136e-01
6.428000000000e-10 7.828445699494e-01
6.528000000000e-10 7.084631989914e-01
6.628000000000e-10 5.068703543607e-01
6.728000000000e-10 1.982651160797e-01
6.828000000000e-10 -1.180209524418e-01
6.928000000000e-10 -3.726100259571e-01
7.028000000000e-10 -5.403229404029e-01
7.128000000000e-10 -6.438083895554e-01
7.228000000000e-10 -7.203378638829e-01
7.328000000000e-10 -7.741273273776e-01
7.428000000000e-10 -7.828912312659e-01
7.528000000000e-10 -7.084155733246e-01
7.628000000000e-10 -5.069185371484e-01
7.728000000000e-10 -1.982163796445e-01
7.828000000000e-10 1.179761824049e-01
7.928000000000e-10 3.726538824343e-01
8.028000000000e-10 5.402795684719e-01
8.128000000000e-10 6.438520994328e-01
8.228000000000e-10 7.202935093188e-01
8.328000000000e-10 7.741699689895e-01
8.428000000000e-10 7.828494756723e-01
8.528000000000e-10 7.084578188073e-01
8.628000000000e-10 5.068761410729e-01
8.728000000000e-10 1.982594122387e-01
8.828000000000e-10 -1.180157633845e-01
8.928000000000e-10 -3.726154653834e-01
9.028000000000e-10 -5.403175771302e-01
9.128000000000e-10 -6.438140825829e-01
9.228000000000e-10 -7.203322576361e-01
9.328000000000e-10 -7.741328388949e-01
9.428000000000e-10 -7.828857350121e-01
9.528000000000e-10 -7.084208512479e-01
9.628000000000e-10 -5.069134738545e-01
9.728000000000e-10 -1.982215797151e-01
9.828000000000e-10 1.179810466336e-01
9.928000000000e-10 3.726493985613e-01
1.000000000000e-09 5.010433738758e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 14
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ss
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14
temperature: '27'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 80
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb_15.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -4.764925698370e-01
1.728000000000e-10 -1.934019301872e-01
1.828000000000e-10 1.027850457497e-01
1.928000000000e-10 3.499528968595e-01
2.028000000000e-10 5.186059326128e-01
2.128000000000e-10 6.254912177700e-01
2.228000000000e-10 6.994356057335e-01
2.328000000000e-10 7.419604616039e-01
2.428000000000e-10 7.366001230119e-01
2.528000000000e-10 6.575586826882e-01
2.628000000000e-10 4.703480039804e-01
2.728000000000e-10 1.887311437228e-01
2.828000000000e-10 -1.064955609068e-01
2.928000000000e-10 -3.530674432656e-01
3.028000000000e-10 -5.214103928852e-01
3.128000000000e-10 -6.276329249236e-01
3.228000000000e-10 -7.010919569868e-01
3.328000000000e-10 -7.428528846984e-01
3.428000000000e-10 -7.371070425945e-01
3.528000000000e-10 -6.576931102984e-01
3.628000000000e-10 -4.705213908487e-01
3.728000000000e-10 -1.887451417089e-01
3.828000000000e-10 1.063771169054e-01
3.928000000000e-10 3.530644558224e-01
4.028000000000e-10 5.212882945537e-01
4.128000000000e-10 6.276273956697e-01
4.228000000000e-10 7.009872983885e-01
4.328000000000e-10 7.428850006835e-01
4.428000000000e-10 7.370483197885e-01
4.528000000000e-10 6.577532995019e-01
4.628000000000e-10 4.704734311564e-01
4.728000000000e-10 1.888066765622e-01
4.828000000000e-10 -1.064251900033e-01
4.928000000000e-10 -3.530110058012e-01
5.028000000000e-10 -5.213363794122e-01
5.128000000000e-10 -6.275779961821e-01
5.228000000000e-10 -7.010367362436e-01
5.328000000000e-10 -7.428359180794e-01
5.428000000000e-10 -7.370946234404e-01
5.528000000000e-10 -6.577041924295e-01
5.628000000000e-10 -4.705211118057e-01
5.728000000000e-10 -1.887571402743e-01
5.828000000000e-10 1.063798390696e-01
5.928000000000e-10 3.530562876751e-01
6.028000000000e-10 5.212929538773e-01
6.128000000000e-10 6.276223718978e-01
6.228000000000e-10 7.009927681762e-01
6.328000000000e-10 7.428797293753e-01
6.428000000000e-10 7.370526578677e-01
6.528000000000e-10 6.577470674825e-01
6.628000000000e-10 4.704784998901e-01
6.728000000000e-10 1.888003575241e-01
6.828000000000e-10 -1.064204487643e-01
6.928000000000e-10 -3.530168946500e-01
7.028000000000e-10 -5.213312567329e-01
7.128000000000e-10 -6.275838929681e-01
7.228000000000e-10 -7.010312441909e-01
7.328000000000e-10 -7.428415937954e-01
7.428000000000e-10 -7.370893810626e-01
7.528000000000e-10 -6.577094889087e-01
7.628000000000e-10 -4.705162397262e-01
7.728000000000e-10 -1.887623115300e-01
7.828000000000e-10 1.063847513579e-01
7.928000000000e-10 3.530516705381e-01
8.028000000000e-10 5.212973590939e-01
8.128000000000e-10 6.276181223045e-01
8.228000000000e-10 7.009970786285e-01
8.328000000000e-10 7.428754735512e-01
8.428000000000e-10 7.370567570344e-01
8.528000000000e-10 6.577427030952e-01
8.628000000000e-10 4.704830497474e-01
8.728000000000e-10 1.887958404937e-01
8.828000000000e-10 -1.064163174914e-01
8.928000000000e-10 -3.530210908451e-01
9.028000000000e-10 -5.213271590930e-01
9.128000000000e-10 -6.275881896870e-01
9.228000000000e-10 -7.010270518598e-01
9.328000000000e-10 -7.428457852801e-01
9.428000000000e-10 -7.370853633469e-01
9.528000000000e-10 -6.577134719194e-01
9.628000000000e-10 -4.705123783357e-01
9.728000000000e-10 -1.887662540331e-01
9.828000000000e-10 1.063885555413e-01
9.928000000000e-10 3.530480784075e-01
1.000000000000e-09 4.814572085440e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_divider.sym Normal file
View File

@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 15
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15
temperature: '80'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 80
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb_16.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -4.643042367579e-01
1.728000000000e-10 -1.889536448800e-01
1.828000000000e-10 1.011027156160e-01
1.928000000000e-10 3.431119917378e-01
2.028000000000e-10 5.070519088353e-01
2.128000000000e-10 6.112991757094e-01
2.228000000000e-10 6.838020209744e-01
2.328000000000e-10 7.242864479517e-01
2.428000000000e-10 7.174167448313e-01
2.528000000000e-10 6.398083866093e-01
2.628000000000e-10 4.585166519927e-01
2.728000000000e-10 1.844271573483e-01
2.828000000000e-10 -1.048019054065e-01
2.928000000000e-10 -3.462317584687e-01
3.028000000000e-10 -5.098344721858e-01
3.128000000000e-10 -6.133899227371e-01
3.228000000000e-10 -6.853968517792e-01
3.328000000000e-10 -7.251059393871e-01
3.428000000000e-10 -7.178642533065e-01
3.528000000000e-10 -6.398898931720e-01
3.628000000000e-10 -4.586473976402e-01
3.728000000000e-10 -1.843989570585e-01
3.828000000000e-10 1.047140758745e-01
3.928000000000e-10 3.462576483703e-01
4.028000000000e-10 5.097333770465e-01
4.128000000000e-10 6.134023110554e-01
4.228000000000e-10 6.853047053340e-01
4.328000000000e-10 7.251501511308e-01
4.428000000000e-10 7.178117501486e-01
4.528000000000e-10 6.399568281317e-01
4.628000000000e-10 4.586017943502e-01
4.728000000000e-10 1.844658494373e-01
4.828000000000e-10 -1.047609876408e-01
4.928000000000e-10 -3.462003104379e-01
5.028000000000e-10 -5.097813732572e-01
5.128000000000e-10 -6.133504189098e-01
5.228000000000e-10 -6.853547602223e-01
5.328000000000e-10 -7.250985458364e-01
5.428000000000e-10 -7.178593251267e-01
5.528000000000e-10 -6.399055102013e-01
5.628000000000e-10 -4.586511534755e-01
5.728000000000e-10 -1.844138975484e-01
5.828000000000e-10 1.047143295024e-01
5.928000000000e-10 3.462472486482e-01
6.028000000000e-10 5.097369504642e-01
6.128000000000e-10 6.133959963639e-01
6.228000000000e-10 6.853096740322e-01
6.328000000000e-10 7.251438129543e-01
6.428000000000e-10 7.178160816468e-01
6.528000000000e-10 6.399498616471e-01
6.628000000000e-10 4.586069220749e-01
6.728000000000e-10 1.844588245643e-01
6.828000000000e-10 -1.047563687876e-01
6.928000000000e-10 -3.462063328010e-01
7.028000000000e-10 -5.097765086741e-01
7.128000000000e-10 -6.133562893232e-01
7.228000000000e-10 -6.853494321266e-01
7.328000000000e-10 -7.251041291885e-01
7.428000000000e-10 -7.178542203751e-01
7.528000000000e-10 -6.399107355976e-01
7.628000000000e-10 -4.586462738291e-01
7.728000000000e-10 -1.844190131957e-01
7.828000000000e-10 1.047193339603e-01
7.928000000000e-10 3.462424630766e-01
8.028000000000e-10 5.097415276109e-01
8.128000000000e-10 6.133915881396e-01
8.228000000000e-10 6.853141467162e-01
8.328000000000e-10 7.251393167662e-01
8.428000000000e-10 7.178204152808e-01
8.528000000000e-10 6.399452651751e-01
8.628000000000e-10 4.586116651576e-01
8.728000000000e-10 1.844540563551e-01
8.828000000000e-10 -1.047521530128e-01
8.928000000000e-10 -3.462105768541e-01
9.028000000000e-10 -5.097724238353e-01
9.128000000000e-10 -6.133605792288e-01
9.228000000000e-10 -6.853452315529e-01
9.328000000000e-10 -7.251083207568e-01
9.428000000000e-10 -7.178502144615e-01
9.528000000000e-10 -6.399147306347e-01
9.628000000000e-10 -4.586423495280e-01
9.728000000000e-10 -1.844229988419e-01
9.828000000000e-10 1.047232268776e-01
9.928000000000e-10 3.462387497741e-01
1.000000000000e-09 4.710752262880e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 16
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ff
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16
temperature: '80'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp 80
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb_17.data Normal file
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@ -0,0 +1,85 @@
1.628000000000e-10 -4.852886719505e-01
1.728000000000e-10 -2.023606658915e-01
1.828000000000e-10 9.500407548716e-02
1.928000000000e-10 3.473018630854e-01
2.028000000000e-10 5.238539974445e-01
2.128000000000e-10 6.356942626004e-01
2.228000000000e-10 7.106560719901e-01
2.328000000000e-10 7.539243132234e-01
2.428000000000e-10 7.486736309564e-01
2.528000000000e-10 6.681985082542e-01
2.628000000000e-10 4.800908099257e-01
2.728000000000e-10 1.985903293754e-01
2.828000000000e-10 -9.801965724844e-02
2.928000000000e-10 -3.499456539083e-01
3.028000000000e-10 -5.264166063204e-01
3.128000000000e-10 -6.377599985577e-01
3.228000000000e-10 -7.123258227204e-01
3.328000000000e-10 -7.548386637736e-01
3.428000000000e-10 -7.491646196322e-01
3.528000000000e-10 -6.682802381819e-01
3.628000000000e-10 -4.802044877583e-01
3.728000000000e-10 -1.985554586747e-01
3.828000000000e-10 9.793570714348e-02
3.928000000000e-10 3.499705083814e-01
4.028000000000e-10 5.263126851869e-01
4.128000000000e-10 6.377668221774e-01
4.228000000000e-10 7.122256281615e-01
4.328000000000e-10 7.548735616237e-01
4.428000000000e-10 7.491068615558e-01
4.528000000000e-10 6.683430307676e-01
4.628000000000e-10 4.801581700099e-01
4.728000000000e-10 1.986186025664e-01
4.828000000000e-10 -9.798359332438e-02
4.928000000000e-10 -3.499159407959e-01
5.028000000000e-10 -5.263605524234e-01
5.128000000000e-10 -6.377159898188e-01
5.228000000000e-10 -7.122753084256e-01
5.328000000000e-10 -7.548237332543e-01
5.428000000000e-10 -7.491535548765e-01
5.528000000000e-10 -6.682936663178e-01
5.628000000000e-10 -4.802057994081e-01
5.728000000000e-10 -1.985692377738e-01
5.828000000000e-10 9.793754425938e-02
5.928000000000e-10 3.499612594703e-01
6.028000000000e-10 5.263165540334e-01
6.128000000000e-10 6.377608692391e-01
6.228000000000e-10 7.122309292959e-01
6.328000000000e-10 7.548679483739e-01
6.428000000000e-10 7.491113260135e-01
6.528000000000e-10 6.683367510584e-01
6.628000000000e-10 4.801631540398e-01
6.728000000000e-10 1.986123746205e-01
6.828000000000e-10 -9.797860547701e-02
6.928000000000e-10 -3.499219086015e-01
7.028000000000e-10 -5.263552271330e-01
7.128000000000e-10 -6.377219921840e-01
7.228000000000e-10 -7.122696952774e-01
7.328000000000e-10 -7.548295298651e-01
7.428000000000e-10 -7.491481908175e-01
7.528000000000e-10 -6.682991221138e-01
7.628000000000e-10 -4.802006967346e-01
7.728000000000e-10 -1.985745887274e-01
7.828000000000e-10 9.794256695295e-02
7.928000000000e-10 3.499565849765e-01
8.028000000000e-10 5.263210489698e-01
8.128000000000e-10 6.377564579322e-01
8.228000000000e-10 7.122353719246e-01
8.328000000000e-10 7.548635649925e-01
8.428000000000e-10 7.491155123701e-01
8.528000000000e-10 6.683323549155e-01
8.628000000000e-10 4.801676539865e-01
8.728000000000e-10 1.986078923136e-01
8.828000000000e-10 -9.797434132868e-02
8.928000000000e-10 -3.499261582655e-01
9.028000000000e-10 -5.263510069851e-01
9.128000000000e-10 -6.377263524572e-01
9.228000000000e-10 -7.122654282965e-01
9.328000000000e-10 -7.548337908470e-01
9.428000000000e-10 -7.491440991364e-01
9.528000000000e-10 -6.683032069827e-01
9.628000000000e-10 -4.801967157057e-01
9.728000000000e-10 -1.985786291727e-01
9.828000000000e-10 9.794644208878e-02
9.928000000000e-10 3.499529545785e-01
1.000000000000e-09 4.843355885316e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 17
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: ss
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17
temperature: '80'
vdd: '1.2'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

85
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb_18.data Normal file
View File

@ -0,0 +1,85 @@
1.628000000000e-10 5.747244840755e-01
1.728000000000e-10 2.031348680811e-01
1.828000000000e-10 -1.640358346053e-01
1.928000000000e-10 -4.121983890365e-01
2.028000000000e-10 -5.403960481430e-01
2.128000000000e-10 -6.175267008304e-01
2.228000000000e-10 -7.185181164841e-01
2.328000000000e-10 -8.111835866476e-01
2.428000000000e-10 -8.505757111821e-01
2.528000000000e-10 -7.941523888433e-01
2.628000000000e-10 -5.697557803605e-01
2.728000000000e-10 -1.993901761575e-01
2.828000000000e-10 1.667454340744e-01
2.928000000000e-10 4.143424459307e-01
3.028000000000e-10 5.421310172268e-01
3.128000000000e-10 6.189024162340e-01
3.228000000000e-10 7.194369498053e-01
3.328000000000e-10 8.117600127730e-01
3.428000000000e-10 8.508336653308e-01
3.528000000000e-10 7.942656656211e-01
3.628000000000e-10 5.697751550033e-01
3.728000000000e-10 1.994135726672e-01
3.828000000000e-10 -1.667386419247e-01
3.928000000000e-10 -4.143148464313e-01
4.028000000000e-10 -5.421262038320e-01
4.128000000000e-10 -6.188832903749e-01
4.228000000000e-10 -7.194346712496e-01
4.328000000000e-10 -8.117442314974e-01
4.428000000000e-10 -8.508381039982e-01
4.528000000000e-10 -7.942559196005e-01
4.628000000000e-10 -5.697859373045e-01
4.728000000000e-10 -1.993975895742e-01
4.828000000000e-10 1.667322235508e-01
4.928000000000e-10 4.143280512458e-01
5.028000000000e-10 5.421195877560e-01
5.128000000000e-10 6.188968586913e-01
5.228000000000e-10 7.194236426239e-01
5.328000000000e-10 8.117540342679e-01
5.428000000000e-10 8.508266757829e-01
5.528000000000e-10 7.942652287581e-01
5.628000000000e-10 5.697754142960e-01
5.728000000000e-10 1.994033695962e-01
5.828000000000e-10 -1.667424669503e-01
5.928000000000e-10 -4.143216611718e-01
6.028000000000e-10 -5.421291067647e-01
6.128000000000e-10 -6.188909595847e-01
6.228000000000e-10 -7.194310352535e-01
6.328000000000e-10 -8.117467342350e-01
6.428000000000e-10 -8.508333273630e-01
6.528000000000e-10 -7.942577903765e-01
6.628000000000e-10 -5.697836419865e-01
6.728000000000e-10 -1.993929431350e-01
6.828000000000e-10 1.667361734044e-01
6.928000000000e-10 4.143307053824e-01
7.028000000000e-10 5.421226813799e-01
7.128000000000e-10 6.189001833416e-01
7.228000000000e-10 7.194227358993e-01
7.328000000000e-10 8.117542266055e-01
7.428000000000e-10 8.508251070290e-01
7.528000000000e-10 7.942649966766e-01
7.628000000000e-10 5.697756363247e-01
7.728000000000e-10 1.993989977467e-01
7.828000000000e-10 -1.667434615441e-01
7.928000000000e-10 -4.143248161746e-01
8.028000000000e-10 -5.421295610790e-01
8.128000000000e-10 -6.188945163710e-01
8.228000000000e-10 -7.194289229798e-01
8.328000000000e-10 -8.117483413843e-01
8.428000000000e-10 -8.508308647988e-01
8.528000000000e-10 -7.942590780393e-01
8.628000000000e-10 -5.697822347435e-01
8.728000000000e-10 -1.993917000580e-01
8.828000000000e-10 1.667380255271e-01
8.928000000000e-10 4.143314131245e-01
9.028000000000e-10 5.421241182927e-01
9.128000000000e-10 6.189011822630e-01
9.228000000000e-10 7.194226089303e-01
9.328000000000e-10 8.117540798381e-01
9.428000000000e-10 8.508247577722e-01
9.528000000000e-10 7.942646412254e-01
9.628000000000e-10 5.697760282588e-01
9.728000000000e-10 1.993969946892e-01
9.828000000000e-10 -1.667434796269e-01
9.928000000000e-10 -4.143264352220e-01
1.000000000000e-09 -5.150731751424e-01

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_divider.sym Normal file
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@ -0,0 +1,30 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -120 -20 -100 -20 {}
L 4 -120 20 -100 20 {}
L 4 100 -20 120 -20 {}
L 4 100 20 120 20 {}
L 7 0 -60 0 -40 {}
L 7 0 40 0 60 {}
B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
T {@symname} -44 -6 0 0 0.3 0.3 {}
T {@name} 45 -52 0 0 0.2 0.2 {}
T {Vo+} -95 -24 0 0 0.2 0.2 {}
T {Vo-} -95 16 0 0 0.2 0.2 {}
T {Vi+} 95 -16 2 0 0.2 0.2 {}
T {Vi-} 95 24 2 0 0.2 0.2 {}
T {vdd} 10 -39 0 1 0.2 0.2 {}
T {gnd} -10 34 2 1 0.2 0.2 {}

9
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/conditions.yaml Normal file
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@ -0,0 +1,9 @@
DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
N: 18
PDK: ihp-sg13g2
PDK_ROOT: /home/pedersen/IHP-Open-PDK
corner: tt
filename: CML_core_tb
simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18
temperature: '-40'
vdd: '1.6'

30
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/.spiceinit Normal file
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@ -0,0 +1,30 @@
* a custom spiceinit file for IHP-Open-PDK
* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
* export PDK=ihp-sg13g2
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
setcs sourcepath = ( $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
*echo $sourcepath
*option tnom=28
*option list
* KLU solver still do not work correctly for every simulation
*option klu
*option node
*option opts
*option warn=1
*option maxwarns=10
*option savecurrents
*set ngbehavior=hsa
*set noinit
* add OSDI
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
osdi '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'

71
modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb.sch Normal file
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@ -0,0 +1,71 @@
v {xschem version=3.4.6 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 740 -940 740 -920 {lab=GND}
N 740 -1090 740 -1060 {lab=VDD}
N 600 -1020 620 -1020 {lab=Vinplus}
N 600 -980 620 -980 {lab=Vinminus}
N 860 -1020 880 -1020 {lab=Voplus}
N 860 -980 880 -980 {lab=Vominus}
N 1150 -850 1150 -820 {lab=VDD}
N 1150 -760 1150 -730 {lab=GND}
N 930 -850 930 -820 {lab=Vinminus}
N 930 -760 930 -730 {lab=GND}
N 720 -850 720 -820 {lab=Vinplus}
N 720 -760 720 -730 {lab=GND}
C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
value="
.ic V(Voplus)=1.2
.control
set noaskquit
set numdgt=12
* Save & simulate
save all
op
write CML_core_tb.raw
set appendwrite
tran 10p 1n 160p
* Explicit vectors
let vo_p = v(Voplus)
let vo_m = v(Vominus)
let vo_diff = vo_p - vo_m
set wr_singlescale
wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff
quit
.endc
"}
C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
format="tcleval( @value )"
value="
.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
.temp -40
"
}
C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
C {CML_divider.sym} 740 -1000 0 1 {name=x1}
C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}

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