diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-312.pyc b/modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-312.pyc
new file mode 100644
index 00000000..9966062b
Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/cace/scripts/__pycache__/freq.cpython-312.pyc differ
diff --git a/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch
index 48f6f0bb..0f707234 100644
--- a/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch
+++ b/modules/module_4_type_2_PLL/CML_divider/cace/templates/CML_core_tb.sch
@@ -1,8 +1,9 @@
-v {xschem version=3.4.6 file_version=1.2}
+v {xschem version=3.4.8RC file_version=1.3}
 G {}
 K {}
 V {}
 S {}
+F {}
 E {}
 N 740 -940 740 -920 {lab=GND}
 N 740 -1090 740 -1060 {lab=VDD}
@@ -19,6 +20,7 @@ N 720 -760 720 -730 {lab=GND}
 C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
 value="
 .ic V(Voplus)=1.2
+.param A=0
 .control
 set noaskquit
 set numdgt=12
@@ -62,10 +64,10 @@ C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
 C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
 C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
 C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
-C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
 C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
 value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
 C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
 value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
-C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
 C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/CML_core_tb.sch
new file mode 100644
index 00000000..48f6f0bb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb.sch
new file mode 100644
index 00000000..9edf23c9
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb_0.data
new file mode 100644
index 00000000..6e5c755c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_core_tb_0.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.952325246460e-01 
+ 1.728000000000e-10 -6.043942197180e-02 
+ 1.828000000000e-10  1.817064006720e-01 
+ 1.928000000000e-10  3.985392356515e-01 
+ 2.028000000000e-10  5.562505249699e-01 
+ 2.128000000000e-10  6.572874178466e-01 
+ 2.228000000000e-10  7.087352858161e-01 
+ 2.328000000000e-10  7.029522511861e-01 
+ 2.428000000000e-10  6.344368312078e-01 
+ 2.528000000000e-10  5.013241237787e-01 
+ 2.628000000000e-10  3.030080742176e-01 
+ 2.728000000000e-10  6.578821975767e-02 
+ 2.828000000000e-10 -1.781586778972e-01 
+ 2.928000000000e-10 -3.964040373443e-01 
+ 3.028000000000e-10 -5.555461653242e-01 
+ 3.128000000000e-10 -6.571022283471e-01 
+ 3.228000000000e-10 -7.092808909864e-01 
+ 3.328000000000e-10 -7.040843150938e-01 
+ 3.428000000000e-10 -6.362469325195e-01 
+ 3.528000000000e-10 -5.032364212786e-01 
+ 3.628000000000e-10 -3.051350358226e-01 
+ 3.728000000000e-10 -6.762904380973e-02 
+ 3.828000000000e-10  1.763878132349e-01 
+ 3.928000000000e-10  3.951284969670e-01 
+ 4.028000000000e-10  5.545978983505e-01 
+ 4.128000000000e-10  6.566315830069e-01 
+ 4.228000000000e-10  7.089962487465e-01 
+ 4.328000000000e-10  7.042633111532e-01 
+ 4.428000000000e-10  6.365365170049e-01 
+ 4.528000000000e-10  5.037912579488e-01 
+ 4.628000000000e-10  3.056253251435e-01 
+ 4.728000000000e-10  6.823087043489e-02 
+ 4.828000000000e-10 -1.759620590786e-01 
+ 4.928000000000e-10 -3.946766675460e-01 
+ 5.028000000000e-10 -5.543918551335e-01 
+ 5.128000000000e-10 -6.564106038653e-01 
+ 5.228000000000e-10 -7.089804674794e-01 
+ 5.328000000000e-10 -7.042284637667e-01 
+ 5.428000000000e-10 -6.366831677063e-01 
+ 5.528000000000e-10 -5.038654128054e-01 
+ 5.628000000000e-10 -3.058301627321e-01 
+ 5.728000000000e-10 -6.832081314378e-02 
+ 5.828000000000e-10  1.757744687450e-01 
+ 5.928000000000e-10  3.946207346164e-01 
+ 6.028000000000e-10  5.542681653143e-01 
+ 6.128000000000e-10  6.564162326939e-01 
+ 6.228000000000e-10  7.089102158365e-01 
+ 6.328000000000e-10  7.042850183822e-01 
+ 6.428000000000e-10  6.366586213363e-01 
+ 6.528000000000e-10  5.039505543903e-01 
+ 6.628000000000e-10  3.058219717524e-01 
+ 6.728000000000e-10  6.840961740524e-02 
+ 6.828000000000e-10 -1.757862033444e-01 
+ 6.928000000000e-10 -3.945467987447e-01 
+ 7.028000000000e-10 -5.542929102277e-01 
+ 7.128000000000e-10 -6.563603422698e-01 
+ 7.228000000000e-10 -7.089481650220e-01 
+ 7.328000000000e-10 -7.042424683005e-01 
+ 7.428000000000e-10 -6.367078290897e-01 
+ 7.528000000000e-10 -5.039165471509e-01 
+ 7.628000000000e-10 -3.058753018579e-01 
+ 7.728000000000e-10 -6.837707225292e-02 
+ 7.828000000000e-10  1.757345833407e-01 
+ 7.928000000000e-10  3.945785215449e-01 
+ 8.028000000000e-10  5.542482652542e-01 
+ 8.128000000000e-10  6.563959408481e-01 
+ 8.228000000000e-10  7.089082113076e-01 
+ 8.328000000000e-10  7.042817797830e-01 
+ 8.428000000000e-10  6.366719399828e-01 
+ 8.528000000000e-10  5.039573608246e-01 
+ 8.628000000000e-10  3.058408732486e-01 
+ 8.728000000000e-10  6.841772818469e-02 
+ 8.828000000000e-10 -1.757686495942e-01 
+ 8.928000000000e-10 -3.945419964750e-01 
+ 9.028000000000e-10 -5.542809328797e-01 
+ 9.128000000000e-10 -6.563614885531e-01 
+ 9.228000000000e-10 -7.089411806967e-01 
+ 9.328000000000e-10 -7.042479976407e-01 
+ 9.428000000000e-10 -6.367051444468e-01 
+ 9.528000000000e-10 -5.039245834310e-01 
+ 9.628000000000e-10 -3.058742220339e-01 
+ 9.728000000000e-10 -6.838526492007e-02 
+ 9.828000000000e-10  1.757358039920e-01 
+ 9.928000000000e-10  3.945718167364e-01 
+ 1.000000000000e-09  5.155910006549e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/conditions.yaml
new file mode 100644
index 00000000..ea54f39e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 0
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_00
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb.sch
new file mode 100644
index 00000000..0181912f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb_1.data
new file mode 100644
index 00000000..94a2849c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_core_tb_1.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.647956442563e-01 
+ 1.728000000000e-10 -3.672466403620e-02 
+ 1.828000000000e-10  1.978055322165e-01 
+ 1.928000000000e-10  4.056017943518e-01 
+ 2.028000000000e-10  5.547344088879e-01 
+ 2.128000000000e-10  6.487490848065e-01 
+ 2.228000000000e-10  6.923653634957e-01 
+ 2.328000000000e-10  6.780886353961e-01 
+ 2.428000000000e-10  6.039598047192e-01 
+ 2.528000000000e-10  4.698168410475e-01 
+ 2.628000000000e-10  2.751260896566e-01 
+ 2.728000000000e-10  4.430157580526e-02 
+ 2.828000000000e-10 -1.925038311834e-01 
+ 2.928000000000e-10 -4.023301580756e-01 
+ 3.028000000000e-10 -5.533152551340e-01 
+ 3.128000000000e-10 -6.481954476962e-01 
+ 3.228000000000e-10 -6.930655672739e-01 
+ 3.328000000000e-10 -6.800540209913e-01 
+ 3.428000000000e-10 -6.070129146880e-01 
+ 3.528000000000e-10 -4.732295235615e-01 
+ 3.628000000000e-10 -2.788311309623e-01 
+ 3.728000000000e-10 -4.769207273318e-02 
+ 3.828000000000e-10  1.893739393663e-01 
+ 3.928000000000e-10  3.999895682405e-01 
+ 4.028000000000e-10  5.516914161753e-01 
+ 4.128000000000e-10  6.473194453459e-01 
+ 4.228000000000e-10  6.926967113745e-01 
+ 4.328000000000e-10  6.804409619078e-01 
+ 4.428000000000e-10  6.077344291363e-01 
+ 4.528000000000e-10  4.743209278754e-01 
+ 4.628000000000e-10  2.799315218230e-01 
+ 4.728000000000e-10  4.887682675205e-02 
+ 4.828000000000e-10 -1.884058832182e-01 
+ 4.928000000000e-10 -3.991237321070e-01 
+ 5.028000000000e-10 -5.511979674959e-01 
+ 5.128000000000e-10 -6.469402879887e-01 
+ 5.228000000000e-10 -6.926225993557e-01 
+ 5.328000000000e-10 -6.804805060919e-01 
+ 5.428000000000e-10 -6.080204415279e-01 
+ 5.528000000000e-10 -4.745961817340e-01 
+ 5.628000000000e-10 -2.803459413605e-01 
+ 5.728000000000e-10 -4.918721233066e-02 
+ 5.828000000000e-10  1.880320213273e-01 
+ 5.928000000000e-10  3.989072784961e-01 
+ 6.028000000000e-10  5.509784832100e-01 
+ 6.128000000000e-10  6.468776696433e-01 
+ 6.228000000000e-10  6.925382949500e-01 
+ 6.328000000000e-10  6.805520167761e-01 
+ 6.428000000000e-10  6.080522625696e-01 
+ 6.528000000000e-10  4.747422384222e-01 
+ 6.628000000000e-10  2.804194075907e-01 
+ 6.728000000000e-10  4.934414267879e-02 
+ 6.828000000000e-10 -1.879699706397e-01 
+ 6.928000000000e-10 -3.987854446736e-01 
+ 7.028000000000e-10 -5.509613139230e-01 
+ 7.128000000000e-10 -6.468062697707e-01 
+ 7.228000000000e-10 -6.925630874809e-01 
+ 7.328000000000e-10 -6.805223964692e-01 
+ 7.428000000000e-10 -6.081132322697e-01 
+ 7.528000000000e-10 -4.747366406660e-01 
+ 7.628000000000e-10 -2.804933490724e-01 
+ 7.728000000000e-10 -4.934235519722e-02 
+ 7.828000000000e-10  1.879006367827e-01 
+ 7.928000000000e-10  3.987938070562e-01 
+ 8.028000000000e-10  5.509093463144e-01 
+ 8.128000000000e-10  6.468293959909e-01 
+ 8.228000000000e-10  6.925252291894e-01 
+ 8.328000000000e-10  6.805590879185e-01 
+ 8.428000000000e-10  6.080875904937e-01 
+ 8.528000000000e-10  4.747803907956e-01 
+ 8.628000000000e-10  2.804721530083e-01 
+ 8.728000000000e-10  4.938687520288e-02 
+ 8.828000000000e-10 -1.879222775604e-01 
+ 8.928000000000e-10 -3.987554695640e-01 
+ 9.028000000000e-10 -5.509333914335e-01 
+ 9.128000000000e-10 -6.467969990881e-01 
+ 9.228000000000e-10 -6.925530415231e-01 
+ 9.328000000000e-10 -6.805304150604e-01 
+ 9.428000000000e-10 -6.081187600045e-01 
+ 9.528000000000e-10 -4.747542418837e-01 
+ 9.628000000000e-10 -2.805045225794e-01 
+ 9.728000000000e-10 -4.936125388638e-02 
+ 9.828000000000e-10  1.878908530872e-01 
+ 9.928000000000e-10  3.987795364060e-01 
+ 1.000000000000e-09  5.142017254263e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/conditions.yaml
new file mode 100644
index 00000000..44209672
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 1
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_01
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb.sch
new file mode 100644
index 00000000..e77fc7fc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb_2.data
new file mode 100644
index 00000000..cdbb156b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_core_tb_2.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.226907107526e-01 
+ 1.728000000000e-10 -8.539968284410e-02 
+ 1.828000000000e-10  1.614480909662e-01 
+ 1.928000000000e-10  3.869191924745e-01 
+ 2.028000000000e-10  5.540483396157e-01 
+ 2.128000000000e-10  6.620167995175e-01 
+ 2.228000000000e-10  7.202634748901e-01 
+ 2.328000000000e-10  7.212523007105e-01 
+ 2.428000000000e-10  6.566979396260e-01 
+ 2.528000000000e-10  5.250303609426e-01 
+ 2.628000000000e-10  3.265092852166e-01 
+ 2.728000000000e-10  8.707604756770e-02 
+ 2.828000000000e-10 -1.611600424348e-01 
+ 2.928000000000e-10 -3.873238626333e-01 
+ 3.028000000000e-10 -5.550746884823e-01 
+ 3.128000000000e-10 -6.629366269634e-01 
+ 3.228000000000e-10 -7.212894794449e-01 
+ 3.328000000000e-10 -7.220878341254e-01 
+ 3.428000000000e-10 -6.576651735802e-01 
+ 3.528000000000e-10 -5.257535323793e-01 
+ 3.628000000000e-10 -3.273054874384e-01 
+ 3.728000000000e-10 -8.759901468451e-02 
+ 3.828000000000e-10  1.605580394287e-01 
+ 3.928000000000e-10  3.869863823107e-01 
+ 4.028000000000e-10  5.547303069787e-01 
+ 4.128000000000e-10  6.628461833305e-01 
+ 4.228000000000e-10  7.211466820779e-01 
+ 4.328000000000e-10  7.221995653822e-01 
+ 4.428000000000e-10  6.577128147927e-01 
+ 4.528000000000e-10  5.259884868760e-01 
+ 4.628000000000e-10  3.274163471898e-01 
+ 4.728000000000e-10  8.784541550780e-02 
+ 4.828000000000e-10 -1.604682108624e-01 
+ 4.928000000000e-10 -3.867888973241e-01 
+ 5.028000000000e-10 -5.547066546217e-01 
+ 5.128000000000e-10 -6.627253094524e-01 
+ 5.228000000000e-10 -7.211826888209e-01 
+ 5.328000000000e-10 -7.221369141817e-01 
+ 5.428000000000e-10 -6.577994031943e-01 
+ 5.528000000000e-10 -5.259620192587e-01 
+ 5.628000000000e-10 -3.275201865204e-01 
+ 5.728000000000e-10 -8.782404636233e-02 
+ 5.828000000000e-10  1.603689538405e-01 
+ 5.928000000000e-10  3.868153343854e-01 
+ 6.028000000000e-10  5.546284247412e-01 
+ 6.128000000000e-10  6.627691182366e-01 
+ 6.228000000000e-10  7.211205707397e-01 
+ 6.328000000000e-10  7.221945096033e-01 
+ 6.428000000000e-10  6.577508134366e-01 
+ 6.528000000000e-10  5.260261908485e-01 
+ 6.628000000000e-10  3.274760111912e-01 
+ 6.728000000000e-10  8.788851273295e-02 
+ 6.828000000000e-10 -1.604138329037e-01 
+ 6.928000000000e-10 -3.867579820075e-01 
+ 7.028000000000e-10 -5.546733587088e-01 
+ 7.128000000000e-10 -6.627166397254e-01 
+ 7.228000000000e-10 -7.211676696649e-01 
+ 7.328000000000e-10 -7.221448613305e-01 
+ 7.428000000000e-10 -6.577993970261e-01 
+ 7.528000000000e-10 -5.259796511606e-01 
+ 7.628000000000e-10 -3.275252420812e-01 
+ 7.728000000000e-10 -8.784270745333e-02 
+ 7.828000000000e-10  1.603648729372e-01 
+ 7.928000000000e-10  3.868003178892e-01 
+ 8.028000000000e-10  5.546284703905e-01 
+ 8.128000000000e-10  6.627594909397e-01 
+ 8.228000000000e-10  7.211247368625e-01 
+ 8.328000000000e-10  7.221884517678e-01 
+ 8.428000000000e-10  6.577581123739e-01 
+ 8.528000000000e-10  5.260226393584e-01 
+ 8.628000000000e-10  3.274844581735e-01 
+ 8.728000000000e-10  8.788515759553e-02 
+ 8.828000000000e-10 -1.604054537172e-01 
+ 8.928000000000e-10 -3.867616376768e-01 
+ 9.028000000000e-10 -5.546662826942e-01 
+ 9.128000000000e-10 -6.627215467888e-01 
+ 9.228000000000e-10 -7.211618152183e-01 
+ 9.328000000000e-10 -7.221504122635e-01 
+ 9.428000000000e-10 -6.577943183983e-01 
+ 9.528000000000e-10 -5.259856282734e-01 
+ 9.628000000000e-10 -3.275204867996e-01 
+ 9.728000000000e-10 -8.784851998896e-02 
+ 9.828000000000e-10  1.603694682536e-01 
+ 9.928000000000e-10  3.867951846118e-01 
+ 1.000000000000e-09  5.139507493642e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/conditions.yaml
new file mode 100644
index 00000000..41559501
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 2
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_02
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb.sch
new file mode 100644
index 00000000..c6e7129b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb_3.data
new file mode 100644
index 00000000..a5b707e1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_core_tb_3.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.752371518652e-01 
+ 1.728000000000e-10 -5.371376319542e-02 
+ 1.828000000000e-10  1.789877413053e-01 
+ 1.928000000000e-10  3.904548691103e-01 
+ 2.028000000000e-10  5.481842948229e-01 
+ 2.128000000000e-10  6.473880529986e-01 
+ 2.228000000000e-10  6.910106576952e-01 
+ 2.328000000000e-10  6.747515328639e-01 
+ 2.428000000000e-10  5.993982850131e-01 
+ 2.528000000000e-10  4.678235295331e-01 
+ 2.628000000000e-10  2.811940191144e-01 
+ 2.728000000000e-10  5.749892092429e-02 
+ 2.828000000000e-10 -1.768703468756e-01 
+ 2.928000000000e-10 -3.894327299011e-01 
+ 3.028000000000e-10 -5.481462871223e-01 
+ 3.128000000000e-10 -6.476233959034e-01 
+ 3.228000000000e-10 -6.918267741740e-01 
+ 3.328000000000e-10 -6.759891610513e-01 
+ 3.428000000000e-10 -6.011477081233e-01 
+ 3.528000000000e-10 -4.695436066175e-01 
+ 3.628000000000e-10 -2.830251877311e-01 
+ 3.728000000000e-10 -5.907673776650e-02 
+ 3.828000000000e-10  1.753349861707e-01 
+ 3.928000000000e-10  3.883274219019e-01 
+ 4.028000000000e-10  5.473035177189e-01 
+ 4.128000000000e-10  6.472356324664e-01 
+ 4.228000000000e-10  6.916308158427e-01 
+ 4.328000000000e-10  6.762268077787e-01 
+ 4.428000000000e-10  6.014684070962e-01 
+ 4.528000000000e-10  4.700895666681e-01 
+ 4.628000000000e-10  2.834862741746e-01 
+ 4.728000000000e-10  5.964855757083e-02 
+ 4.828000000000e-10 -1.749274761915e-01 
+ 4.928000000000e-10 -3.878897710558e-01 
+ 5.028000000000e-10 -5.470986037433e-01 
+ 5.128000000000e-10 -6.470272164409e-01 
+ 5.228000000000e-10 -6.916322065746e-01 
+ 5.328000000000e-10 -6.762158687864e-01 
+ 5.428000000000e-10 -6.016311330158e-01 
+ 5.528000000000e-10 -4.701782346337e-01 
+ 5.628000000000e-10 -2.836941639082e-01 
+ 5.728000000000e-10 -5.974768838544e-02 
+ 5.828000000000e-10  1.747352099095e-01 
+ 5.928000000000e-10  3.878245260251e-01 
+ 6.028000000000e-10  5.469715931678e-01 
+ 6.128000000000e-10  6.470284806517e-01 
+ 6.228000000000e-10  6.915679621080e-01 
+ 6.328000000000e-10  6.762768333485e-01 
+ 6.428000000000e-10  6.016163496453e-01 
+ 6.528000000000e-10  4.702674812943e-01 
+ 6.628000000000e-10  2.836938506434e-01 
+ 6.728000000000e-10  5.983990401354e-02 
+ 6.828000000000e-10 -1.747391664584e-01 
+ 6.928000000000e-10 -3.877472828580e-01 
+ 7.028000000000e-10 -5.469903889528e-01 
+ 7.128000000000e-10 -6.469730360721e-01 
+ 7.228000000000e-10 -6.916047287716e-01 
+ 7.328000000000e-10 -6.762386026180e-01 
+ 7.428000000000e-10 -6.016669907082e-01 
+ 7.528000000000e-10 -4.702390118128e-01 
+ 7.628000000000e-10 -2.837481181728e-01 
+ 7.728000000000e-10 -5.981248689037e-02 
+ 7.828000000000e-10  1.746867337354e-01 
+ 7.928000000000e-10  3.877749638679e-01 
+ 8.028000000000e-10  5.469462314077e-01 
+ 8.128000000000e-10  6.470055622974e-01 
+ 8.228000000000e-10  6.915665740520e-01 
+ 8.328000000000e-10  6.762766371031e-01 
+ 8.428000000000e-10  6.016337946720e-01 
+ 8.528000000000e-10  4.702787360349e-01 
+ 8.628000000000e-10  2.837166478210e-01 
+ 8.728000000000e-10  5.985233152723e-02 
+ 8.828000000000e-10 -1.747180248353e-01 
+ 8.928000000000e-10 -3.877389392165e-01 
+ 9.028000000000e-10 -5.469764940938e-01 
+ 9.128000000000e-10 -6.469724949526e-01 
+ 9.228000000000e-10 -6.915980610397e-01 
+ 9.328000000000e-10 -6.762447762615e-01 
+ 9.428000000000e-10 -6.016660865709e-01 
+ 9.528000000000e-10 -4.702484057793e-01 
+ 9.628000000000e-10 -2.837489236123e-01 
+ 9.728000000000e-10 -5.982216431619e-02 
+ 9.828000000000e-10  1.746862818107e-01 
+ 9.928000000000e-10  3.877670239311e-01 
+ 1.000000000000e-09  5.084292112944e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/conditions.yaml
new file mode 100644
index 00000000..4920501d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 3
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_03
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb.sch
new file mode 100644
index 00000000..ee385fcb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb_4.data
new file mode 100644
index 00000000..8dbaf881
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_core_tb_4.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.482257947455e-01 
+ 1.728000000000e-10 -3.259266550035e-02 
+ 1.828000000000e-10  1.930322087844e-01 
+ 1.928000000000e-10  3.960886599474e-01 
+ 2.028000000000e-10  5.450058997505e-01 
+ 2.128000000000e-10  6.360387116800e-01 
+ 2.228000000000e-10  6.712975422190e-01 
+ 2.328000000000e-10  6.474938983982e-01 
+ 2.428000000000e-10  5.679706274704e-01 
+ 2.528000000000e-10  4.364781736218e-01 
+ 2.628000000000e-10  2.536409133725e-01 
+ 2.728000000000e-10  3.555786929817e-02 
+ 2.828000000000e-10 -1.919150168478e-01 
+ 2.928000000000e-10 -3.960490843585e-01 
+ 3.028000000000e-10 -5.456465197220e-01 
+ 3.128000000000e-10 -6.367232933250e-01 
+ 3.228000000000e-10 -6.725166925877e-01 
+ 3.328000000000e-10 -6.491812984547e-01 
+ 3.428000000000e-10 -5.701612342484e-01 
+ 3.528000000000e-10 -4.386195239579e-01 
+ 3.628000000000e-10 -2.558666299298e-01 
+ 3.728000000000e-10 -3.750940439386e-02 
+ 3.828000000000e-10  1.900731677010e-01 
+ 3.928000000000e-10  3.947279065049e-01 
+ 4.028000000000e-10  5.446879536498e-01 
+ 4.128000000000e-10  6.362937598492e-01 
+ 4.228000000000e-10  6.723764816130e-01 
+ 4.328000000000e-10  6.495551727740e-01 
+ 4.428000000000e-10  5.706690754638e-01 
+ 4.528000000000e-10  4.393690386281e-01 
+ 4.628000000000e-10  2.565445890136e-01 
+ 4.728000000000e-10  3.828939038748e-02 
+ 4.828000000000e-10 -1.894747026650e-01 
+ 4.928000000000e-10 -3.941469427019e-01 
+ 5.028000000000e-10 -5.443881652157e-01 
+ 5.128000000000e-10 -6.360424686566e-01 
+ 5.228000000000e-10 -6.723795425302e-01 
+ 5.328000000000e-10 -6.495951074105e-01 
+ 5.428000000000e-10 -5.709049111673e-01 
+ 5.528000000000e-10 -4.395480856777e-01 
+ 5.628000000000e-10 -2.568451405700e-01 
+ 5.728000000000e-10 -3.848386295174e-02 
+ 5.828000000000e-10  1.891998017504e-01 
+ 5.928000000000e-10  3.940128253458e-01 
+ 6.028000000000e-10  5.442195759360e-01 
+ 6.128000000000e-10  6.360190076123e-01 
+ 6.228000000000e-10  6.723154692419e-01 
+ 6.328000000000e-10  6.496722035130e-01 
+ 6.428000000000e-10  5.709215560836e-01 
+ 6.528000000000e-10  4.396716365902e-01 
+ 6.628000000000e-10  2.568848555761e-01 
+ 6.728000000000e-10  3.861258812938e-02 
+ 6.828000000000e-10 -1.891673406027e-01 
+ 6.928000000000e-10 -3.939096487469e-01 
+ 7.028000000000e-10 -5.442185154541e-01 
+ 7.128000000000e-10 -6.359555029215e-01 
+ 7.228000000000e-10 -6.723494769467e-01 
+ 7.328000000000e-10 -6.496420384079e-01 
+ 7.428000000000e-10 -5.709822816025e-01 
+ 7.528000000000e-10 -4.396582995671e-01 
+ 7.628000000000e-10 -2.569529185106e-01 
+ 7.728000000000e-10 -3.860128053097e-02 
+ 7.828000000000e-10  1.891028165048e-01 
+ 7.928000000000e-10  3.939252197739e-01 
+ 8.028000000000e-10  5.441685861906e-01 
+ 8.128000000000e-10  6.359828023137e-01 
+ 8.228000000000e-10  6.723118712615e-01 
+ 8.328000000000e-10  6.496812709937e-01 
+ 8.428000000000e-10  5.709544657577e-01 
+ 8.528000000000e-10  4.397022527784e-01 
+ 8.628000000000e-10  2.569280980597e-01 
+ 8.728000000000e-10  3.864565597286e-02 
+ 8.828000000000e-10 -1.891278298806e-01 
+ 8.928000000000e-10 -3.938862165142e-01 
+ 9.028000000000e-10 -5.441949734698e-01 
+ 9.128000000000e-10 -6.359493781265e-01 
+ 9.228000000000e-10 -6.723420888760e-01 
+ 9.328000000000e-10 -6.496512561522e-01 
+ 9.428000000000e-10 -5.709874488604e-01 
+ 9.528000000000e-10 -4.396746422576e-01 
+ 9.628000000000e-10 -2.569616958772e-01 
+ 9.728000000000e-10 -3.861839939192e-02 
+ 9.828000000000e-10  1.890951489097e-01 
+ 9.928000000000e-10  3.939119089870e-01 
+ 1.000000000000e-09  5.081084039478e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/conditions.yaml
new file mode 100644
index 00000000..9430aa5d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 4
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_04
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb.sch
new file mode 100644
index 00000000..0ca73f35
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb_5.data
new file mode 100644
index 00000000..72d71163
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_core_tb_5.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.026592886865e-01 
+ 1.728000000000e-10 -8.046058591213e-02 
+ 1.828000000000e-10  1.560684489845e-01 
+ 1.928000000000e-10  3.758215815324e-01 
+ 2.028000000000e-10  5.441825187720e-01 
+ 2.128000000000e-10  6.527787402061e-01 
+ 2.228000000000e-10  7.054162779080e-01 
+ 2.328000000000e-10  6.966940307878e-01 
+ 2.428000000000e-10  6.251719997267e-01 
+ 2.528000000000e-10  4.948986245243e-01 
+ 2.628000000000e-10  3.088338841037e-01 
+ 2.728000000000e-10  8.463582249819e-02 
+ 2.828000000000e-10 -1.534379373390e-01 
+ 2.928000000000e-10 -3.742382678981e-01 
+ 3.028000000000e-10 -5.437587344983e-01 
+ 3.128000000000e-10 -6.527795869025e-01 
+ 3.228000000000e-10 -7.060578401775e-01 
+ 3.328000000000e-10 -6.977288800308e-01 
+ 3.428000000000e-10 -6.267241220561e-01 
+ 3.528000000000e-10 -4.964034573067e-01 
+ 3.628000000000e-10 -3.104523257846e-01 
+ 3.728000000000e-10 -8.599843693100e-02 
+ 3.828000000000e-10  1.520614001089e-01 
+ 3.928000000000e-10  3.732327292359e-01 
+ 4.028000000000e-10  5.429530946109e-01 
+ 4.128000000000e-10  6.523997728799e-01 
+ 4.228000000000e-10  7.058202145507e-01 
+ 4.328000000000e-10  6.979022558405e-01 
+ 4.428000000000e-10  6.269588593419e-01 
+ 4.528000000000e-10  4.968624227466e-01 
+ 4.628000000000e-10  3.108132149603e-01 
+ 4.728000000000e-10  8.648038785746e-02 
+ 4.828000000000e-10 -1.517384677919e-01 
+ 4.928000000000e-10 -3.728474794484e-01 
+ 5.028000000000e-10 -5.427866011842e-01 
+ 5.128000000000e-10 -6.522022614009e-01 
+ 5.228000000000e-10 -7.058208822479e-01 
+ 5.328000000000e-10 -6.978651082200e-01 
+ 5.428000000000e-10 -6.270935668997e-01 
+ 5.528000000000e-10 -4.969096569281e-01 
+ 5.628000000000e-10 -3.109835748750e-01 
+ 5.728000000000e-10 -8.653572716924e-02 
+ 5.828000000000e-10  1.515778681972e-01 
+ 5.928000000000e-10  3.728127447205e-01 
+ 6.028000000000e-10  5.426739415091e-01 
+ 6.128000000000e-10  6.522162007318e-01 
+ 6.228000000000e-10  7.057544179932e-01 
+ 6.328000000000e-10  6.979224304337e-01 
+ 6.428000000000e-10  6.270641898671e-01 
+ 6.528000000000e-10  4.969874144680e-01 
+ 6.628000000000e-10  3.109648292365e-01 
+ 6.728000000000e-10  8.661535651254e-02 
+ 6.828000000000e-10 -1.515990397030e-01 
+ 6.928000000000e-10 -3.727433125293e-01 
+ 7.028000000000e-10 -5.427028559119e-01 
+ 7.128000000000e-10 -6.521615488134e-01 
+ 7.228000000000e-10 -7.057946841560e-01 
+ 7.328000000000e-10 -6.978790263426e-01 
+ 7.428000000000e-10 -6.271133848792e-01 
+ 7.528000000000e-10 -4.969513861012e-01 
+ 7.628000000000e-10 -3.110159233563e-01 
+ 7.728000000000e-10 -8.658006676818e-02 
+ 7.828000000000e-10  1.515487071721e-01 
+ 7.928000000000e-10  3.727772980737e-01 
+ 8.028000000000e-10  5.426589701450e-01 
+ 8.128000000000e-10  6.521979789832e-01 
+ 8.228000000000e-10  7.057547305503e-01 
+ 8.328000000000e-10  6.979187185021e-01 
+ 8.428000000000e-10  6.270767072939e-01 
+ 8.528000000000e-10  4.969913946096e-01 
+ 8.628000000000e-10  3.109805885282e-01 
+ 8.728000000000e-10  8.662004567696e-02 
+ 8.828000000000e-10 -1.515841004471e-01 
+ 8.928000000000e-10 -3.727405314049e-01 
+ 9.028000000000e-10 -5.426922302859e-01 
+ 9.128000000000e-10 -6.521632231968e-01 
+ 9.228000000000e-10 -7.057882763540e-01 
+ 9.328000000000e-10 -6.978845659833e-01 
+ 9.428000000000e-10 -6.271103709374e-01 
+ 9.528000000000e-10 -4.969587868574e-01 
+ 9.628000000000e-10 -3.110138943909e-01 
+ 9.728000000000e-10 -8.658760475646e-02 
+ 9.828000000000e-10  1.515508999036e-01 
+ 9.928000000000e-10  3.727707590510e-01 
+ 1.000000000000e-09  5.012730784879e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/conditions.yaml
new file mode 100644
index 00000000..194e56a1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 5
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_05
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb.sch
new file mode 100644
index 00000000..35464db0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb_6.data
new file mode 100644
index 00000000..2ac25b32
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_core_tb_6.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.658991355482e-01 
+ 1.728000000000e-10 -5.658971746101e-02 
+ 1.828000000000e-10  1.665652322471e-01 
+ 1.928000000000e-10  3.726189743475e-01 
+ 2.028000000000e-10  5.303705116758e-01 
+ 2.128000000000e-10  6.287796796090e-01 
+ 2.228000000000e-10  6.685380236864e-01 
+ 2.328000000000e-10  6.490234756137e-01 
+ 2.428000000000e-10  5.737092070140e-01 
+ 2.528000000000e-10  4.474825535463e-01 
+ 2.628000000000e-10  2.725242795062e-01 
+ 2.728000000000e-10  6.117177433707e-02 
+ 2.828000000000e-10 -1.637031734923e-01 
+ 2.928000000000e-10 -3.708935568747e-01 
+ 3.028000000000e-10 -5.297756369707e-01 
+ 3.128000000000e-10 -6.287017384995e-01 
+ 3.228000000000e-10 -6.693265533929e-01 
+ 3.328000000000e-10 -6.504570398323e-01 
+ 3.428000000000e-10 -5.758168078022e-01 
+ 3.528000000000e-10 -4.496242973413e-01 
+ 3.628000000000e-10 -2.747981275605e-01 
+ 3.728000000000e-10 -6.319393908833e-02 
+ 3.828000000000e-10  1.617439470913e-01 
+ 3.928000000000e-10  3.694169588634e-01 
+ 4.028000000000e-10  5.286499307585e-01 
+ 4.128000000000e-10  6.281722098808e-01 
+ 4.228000000000e-10  6.691184385543e-01 
+ 4.328000000000e-10  6.507901751637e-01 
+ 4.428000000000e-10  5.762974118946e-01 
+ 4.528000000000e-10  4.503608294114e-01 
+ 4.628000000000e-10  2.754522690623e-01 
+ 4.728000000000e-10  6.396306731359e-02 
+ 4.828000000000e-10 -1.611542650007e-01 
+ 4.928000000000e-10 -3.688169747432e-01 
+ 5.028000000000e-10 -5.283292872594e-01 
+ 5.128000000000e-10 -6.279003852563e-01 
+ 5.228000000000e-10 -6.691136918962e-01 
+ 5.328000000000e-10 -6.508124831570e-01 
+ 5.428000000000e-10 -5.765249280825e-01 
+ 5.528000000000e-10 -4.505225248069e-01 
+ 5.628000000000e-10 -2.757393848954e-01 
+ 5.728000000000e-10 -6.413835118523e-02 
+ 5.828000000000e-10  1.608879015274e-01 
+ 5.928000000000e-10  3.686909867212e-01 
+ 6.028000000000e-10  5.281558224884e-01 
+ 6.128000000000e-10  6.278785795680e-01 
+ 6.228000000000e-10  6.690442760911e-01 
+ 6.328000000000e-10  6.508870303825e-01 
+ 6.428000000000e-10  5.765321271449e-01 
+ 6.528000000000e-10  4.506407637839e-01 
+ 6.628000000000e-10  2.757670228304e-01 
+ 6.728000000000e-10  6.426080532693e-02 
+ 6.828000000000e-10 -1.608659404084e-01 
+ 6.928000000000e-10 -3.685888330346e-01 
+ 7.028000000000e-10 -5.281591419234e-01 
+ 7.128000000000e-10 -6.278127091451e-01 
+ 7.228000000000e-10 -6.690805910819e-01 
+ 7.328000000000e-10 -6.508520944992e-01 
+ 7.428000000000e-10 -5.765925476372e-01 
+ 7.528000000000e-10 -4.506215704207e-01 
+ 7.628000000000e-10 -2.758332595929e-01 
+ 7.728000000000e-10 -6.424327491403e-02 
+ 7.828000000000e-10  1.608024320318e-01 
+ 7.928000000000e-10  3.686091606456e-01 
+ 8.028000000000e-10  5.281080947303e-01 
+ 8.128000000000e-10  6.278426474070e-01 
+ 8.228000000000e-10  6.690409470235e-01 
+ 8.328000000000e-10  6.508923982303e-01 
+ 8.428000000000e-10  5.765614162070e-01 
+ 8.528000000000e-10  4.506656063053e-01 
+ 8.628000000000e-10  2.758047260180e-01 
+ 8.728000000000e-10  6.428762429922e-02 
+ 8.828000000000e-10 -1.608310872580e-01 
+ 8.928000000000e-10 -3.685690211775e-01 
+ 9.028000000000e-10 -5.281370864240e-01 
+ 9.128000000000e-10 -6.278075066251e-01 
+ 9.228000000000e-10 -6.690730291835e-01 
+ 9.328000000000e-10 -6.508603444096e-01 
+ 9.428000000000e-10 -5.765956636587e-01 
+ 9.528000000000e-10 -4.506359555730e-01 
+ 9.628000000000e-10 -2.758391852585e-01 
+ 9.728000000000e-10 -6.425829353036e-02 
+ 9.828000000000e-10  1.607973448132e-01 
+ 9.928000000000e-10  3.685968285070e-01 
+ 1.000000000000e-09  4.894958047088e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/conditions.yaml
new file mode 100644
index 00000000..95070641
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 6
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_06
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb.sch
new file mode 100644
index 00000000..17e8588a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb_7.data
new file mode 100644
index 00000000..8cc8eec2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_core_tb_7.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.411371086013e-01 
+ 1.728000000000e-10 -3.745255924116e-02 
+ 1.828000000000e-10  1.789428987452e-01 
+ 1.928000000000e-10  3.769558934840e-01 
+ 2.028000000000e-10  5.255858783541e-01 
+ 2.128000000000e-10  6.150086513683e-01 
+ 2.228000000000e-10  6.463506095909e-01 
+ 2.328000000000e-10  6.202014565113e-01 
+ 2.428000000000e-10  5.417075102450e-01 
+ 2.528000000000e-10  4.161519970610e-01 
+ 2.628000000000e-10  2.448960905686e-01 
+ 2.728000000000e-10  3.892968213965e-02 
+ 2.828000000000e-10 -1.791505445505e-01 
+ 2.928000000000e-10 -3.778686664383e-01 
+ 3.028000000000e-10 -5.268093330033e-01 
+ 3.128000000000e-10 -6.159877416348e-01 
+ 3.228000000000e-10 -6.476195951568e-01 
+ 3.328000000000e-10 -6.216667221790e-01 
+ 3.428000000000e-10 -5.435382878554e-01 
+ 3.528000000000e-10 -4.178448923887e-01 
+ 3.628000000000e-10 -2.466531390426e-01 
+ 3.728000000000e-10 -4.041876256606e-02 
+ 3.828000000000e-10  1.777092594525e-01 
+ 3.928000000000e-10  3.768542192180e-01 
+ 4.028000000000e-10  5.260351926041e-01 
+ 4.128000000000e-10  6.156923491854e-01 
+ 4.228000000000e-10  6.475364165656e-01 
+ 4.328000000000e-10  6.220253224816e-01 
+ 4.428000000000e-10  5.439681165412e-01 
+ 4.528000000000e-10  4.184919515643e-01 
+ 4.628000000000e-10  2.472032785778e-01 
+ 4.728000000000e-10  4.108392377197e-02 
+ 4.828000000000e-10 -1.772209974541e-01 
+ 4.928000000000e-10 -3.763464849454e-01 
+ 5.028000000000e-10 -5.257893585276e-01 
+ 5.128000000000e-10 -6.154751208437e-01 
+ 5.228000000000e-10 -6.475677164184e-01 
+ 5.328000000000e-10 -6.220637777790e-01 
+ 5.428000000000e-10 -5.441970040997e-01 
+ 5.528000000000e-10 -4.186454653208e-01 
+ 5.628000000000e-10 -2.474812841152e-01 
+ 5.728000000000e-10 -4.124875776275e-02 
+ 5.828000000000e-10  1.769646369358e-01 
+ 5.928000000000e-10  3.762321495571e-01 
+ 6.028000000000e-10  5.256270530622e-01 
+ 6.128000000000e-10  6.154644314175e-01 
+ 6.228000000000e-10  6.475079392204e-01 
+ 6.328000000000e-10  6.221477255403e-01 
+ 6.428000000000e-10  5.442104878297e-01 
+ 6.528000000000e-10  4.187701859554e-01 
+ 6.628000000000e-10  2.475138621783e-01 
+ 6.728000000000e-10  4.137738638918e-02 
+ 6.828000000000e-10 -1.769383615791e-01 
+ 6.928000000000e-10 -3.761265802968e-01 
+ 7.028000000000e-10 -5.256298366366e-01 
+ 7.128000000000e-10 -6.153992750277e-01 
+ 7.228000000000e-10 -6.475476374408e-01 
+ 7.328000000000e-10 -6.221164421539e-01 
+ 7.428000000000e-10 -5.442762390873e-01 
+ 7.528000000000e-10 -4.187551150856e-01 
+ 7.628000000000e-10 -2.475858208222e-01 
+ 7.728000000000e-10 -4.136415856981e-02 
+ 7.828000000000e-10  1.768699557901e-01 
+ 7.928000000000e-10  3.761440347995e-01 
+ 8.028000000000e-10  5.255765528630e-01 
+ 8.128000000000e-10  6.154291154928e-01 
+ 8.228000000000e-10  6.475082015932e-01 
+ 8.328000000000e-10  6.221591874056e-01 
+ 8.428000000000e-10  5.442468649409e-01 
+ 8.528000000000e-10  4.188025713318e-01 
+ 8.628000000000e-10  2.475593730203e-01 
+ 8.728000000000e-10  4.141194467582e-02 
+ 8.828000000000e-10 -1.768965906206e-01 
+ 8.928000000000e-10 -3.761014263264e-01 
+ 9.028000000000e-10 -5.256047249426e-01 
+ 9.128000000000e-10 -6.153930400649e-01 
+ 9.228000000000e-10 -6.475410523019e-01 
+ 9.328000000000e-10 -6.221273229309e-01 
+ 9.428000000000e-10 -5.442828742825e-01 
+ 9.528000000000e-10 -4.187734552047e-01 
+ 9.628000000000e-10 -2.475958588134e-01 
+ 9.728000000000e-10 -4.138326223977e-02 
+ 9.828000000000e-10  1.768611473522e-01 
+ 9.928000000000e-10  3.761288017358e-01 
+ 1.000000000000e-09  4.898465656484e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/conditions.yaml
new file mode 100644
index 00000000..97a487a6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 7
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_07
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb.sch
new file mode 100644
index 00000000..c7d695d3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb_8.data
new file mode 100644
index 00000000..2ec9911e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_core_tb_8.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.915574653990e-01 
+ 1.728000000000e-10 -8.207206468644e-02 
+ 1.828000000000e-10  1.443140454917e-01 
+ 1.928000000000e-10  3.578501059917e-01 
+ 2.028000000000e-10  5.264102614641e-01 
+ 2.128000000000e-10  6.356033847750e-01 
+ 2.228000000000e-10  6.852124516173e-01 
+ 2.328000000000e-10  6.731697751231e-01 
+ 2.428000000000e-10  6.014680860110e-01 
+ 2.528000000000e-10  4.762934940598e-01 
+ 2.628000000000e-10  3.019743151843e-01 
+ 2.728000000000e-10  9.052768843264e-02 
+ 2.828000000000e-10 -1.376882496508e-01 
+ 2.928000000000e-10 -3.528073773591e-01 
+ 3.028000000000e-10 -5.234244166185e-01 
+ 3.128000000000e-10 -6.340851318675e-01 
+ 3.228000000000e-10 -6.854084589569e-01 
+ 3.328000000000e-10 -6.747695956588e-01 
+ 3.428000000000e-10 -6.042844418494e-01 
+ 3.528000000000e-10 -4.793995649692e-01 
+ 3.628000000000e-10 -3.052822644166e-01 
+ 3.728000000000e-10 -9.358407685982e-02 
+ 3.828000000000e-10  1.347194202511e-01 
+ 3.928000000000e-10  3.504174847188e-01 
+ 4.028000000000e-10  5.215924623562e-01 
+ 4.128000000000e-10  6.330900225454e-01 
+ 4.228000000000e-10  6.849701135730e-01 
+ 4.328000000000e-10  6.751037342439e-01 
+ 4.428000000000e-10  6.049384750133e-01 
+ 4.528000000000e-10  4.803914109079e-01 
+ 4.628000000000e-10  3.062148923158e-01 
+ 4.728000000000e-10  9.463220881739e-02 
+ 4.828000000000e-10 -1.338572933423e-01 
+ 4.928000000000e-10 -3.495689260045e-01 
+ 5.028000000000e-10 -5.210792449240e-01 
+ 5.128000000000e-10 -6.326887195405e-01 
+ 5.228000000000e-10 -6.848983576670e-01 
+ 5.328000000000e-10 -6.751198274713e-01 
+ 5.428000000000e-10 -6.052060952211e-01 
+ 5.528000000000e-10 -4.806148207689e-01 
+ 5.628000000000e-10 -3.065686575138e-01 
+ 5.728000000000e-10 -9.487468231530e-02 
+ 5.828000000000e-10  1.335246601606e-01 
+ 5.928000000000e-10  3.493821792388e-01 
+ 6.028000000000e-10  5.208575371198e-01 
+ 6.128000000000e-10  6.326338805716e-01 
+ 6.228000000000e-10  6.848108600046e-01 
+ 6.328000000000e-10  6.751907109187e-01 
+ 6.428000000000e-10  6.052214841565e-01 
+ 6.528000000000e-10  4.807458450129e-01 
+ 6.628000000000e-10  3.066111422989e-01 
+ 6.728000000000e-10  9.501122064621e-02 
+ 6.828000000000e-10 -1.334882175614e-01 
+ 6.928000000000e-10 -3.492660352924e-01 
+ 7.028000000000e-10 -5.208495294585e-01 
+ 7.128000000000e-10 -6.325598499367e-01 
+ 7.228000000000e-10 -6.848421004985e-01 
+ 7.328000000000e-10 -6.751543080912e-01 
+ 7.428000000000e-10 -6.052828258645e-01 
+ 7.528000000000e-10 -4.807293659120e-01 
+ 7.628000000000e-10 -3.066794924108e-01 
+ 7.728000000000e-10 -9.499664108150e-02 
+ 7.828000000000e-10  1.334220275121e-01 
+ 7.928000000000e-10  3.492835018463e-01 
+ 8.028000000000e-10  5.207961769649e-01 
+ 8.128000000000e-10  6.325876998525e-01 
+ 8.228000000000e-10  6.848014468222e-01 
+ 8.328000000000e-10  6.751935994962e-01 
+ 8.428000000000e-10  6.052518981308e-01 
+ 8.528000000000e-10  4.807729857688e-01 
+ 8.628000000000e-10  3.066516205185e-01 
+ 8.728000000000e-10  9.504068447267e-02 
+ 8.828000000000e-10 -1.334502935734e-01 
+ 8.928000000000e-10 -3.492430994753e-01 
+ 9.028000000000e-10 -5.208246106410e-01 
+ 9.128000000000e-10 -6.325523513325e-01 
+ 9.228000000000e-10 -6.848328984481e-01 
+ 9.328000000000e-10 -6.751615848536e-01 
+ 9.428000000000e-10 -6.052856721640e-01 
+ 9.528000000000e-10 -4.807436971446e-01 
+ 9.628000000000e-10 -3.066854569150e-01 
+ 9.728000000000e-10 -9.501170247959e-02 
+ 9.828000000000e-10  1.334168358063e-01 
+ 9.928000000000e-10  3.492707284922e-01 
+ 1.000000000000e-09  4.787459694615e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/conditions.yaml
new file mode 100644
index 00000000..04700952
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 8
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_08
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb.sch
new file mode 100644
index 00000000..ef7cb693
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb_9.data
new file mode 100644
index 00000000..1eb23e09
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_core_tb_9.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.397443385003e-01 
+ 1.728000000000e-10 -2.045536352810e-01 
+ 1.828000000000e-10  1.313863393294e-01 
+ 1.928000000000e-10  3.838209275603e-01 
+ 2.028000000000e-10  5.347375940933e-01 
+ 2.128000000000e-10  6.276591932156e-01 
+ 2.228000000000e-10  7.115621702194e-01 
+ 2.328000000000e-10  7.798611559065e-01 
+ 2.428000000000e-10  8.066497785728e-01 
+ 2.528000000000e-10  7.447444131165e-01 
+ 2.628000000000e-10  5.331798214247e-01 
+ 2.728000000000e-10  1.991243487461e-01 
+ 2.828000000000e-10 -1.352153251063e-01 
+ 2.928000000000e-10 -3.864762984078e-01 
+ 3.028000000000e-10 -5.369168929595e-01 
+ 3.128000000000e-10 -6.290603792866e-01 
+ 3.228000000000e-10 -7.126196515736e-01 
+ 3.328000000000e-10 -7.804415576126e-01 
+ 3.428000000000e-10 -8.071911048716e-01 
+ 3.528000000000e-10 -7.450481751688e-01 
+ 3.628000000000e-10 -5.336055963763e-01 
+ 3.728000000000e-10 -1.993198332358e-01 
+ 3.828000000000e-10  1.349559401886e-01 
+ 3.928000000000e-10  3.864112742700e-01 
+ 4.028000000000e-10  5.367351878370e-01 
+ 4.128000000000e-10  6.290489992071e-01 
+ 4.228000000000e-10  7.124864782962e-01 
+ 4.328000000000e-10  7.804750739895e-01 
+ 4.428000000000e-10  8.070933947437e-01 
+ 4.528000000000e-10  7.451033689318e-01 
+ 4.628000000000e-10  5.335168975820e-01 
+ 4.728000000000e-10  1.993807368925e-01 
+ 4.828000000000e-10 -1.350304895400e-01 
+ 4.928000000000e-10 -3.863532554681e-01 
+ 5.028000000000e-10 -5.368040585560e-01 
+ 5.128000000000e-10 -6.289909078772e-01 
+ 5.228000000000e-10 -7.125533448218e-01 
+ 5.328000000000e-10 -7.804160897110e-01 
+ 5.428000000000e-10 -8.071554863663e-01 
+ 5.528000000000e-10 -7.450422465689e-01 
+ 5.628000000000e-10 -5.335838460974e-01 
+ 5.728000000000e-10 -1.993167730115e-01 
+ 5.828000000000e-10  1.349726890253e-01 
+ 5.928000000000e-10  3.864109858256e-01 
+ 6.028000000000e-10  5.367479691018e-01 
+ 6.128000000000e-10  6.290476980128e-01 
+ 6.228000000000e-10  7.124950121919e-01 
+ 6.328000000000e-10  7.804717191606e-01 
+ 6.428000000000e-10  8.070994779138e-01 
+ 6.528000000000e-10  7.450975613250e-01 
+ 6.628000000000e-10  5.335259065522e-01 
+ 6.728000000000e-10  1.993734548210e-01 
+ 6.828000000000e-10 -1.350242777574e-01 
+ 6.928000000000e-10 -3.863605033303e-01 
+ 7.028000000000e-10 -5.367975294074e-01 
+ 7.128000000000e-10 -6.289982763959e-01 
+ 7.228000000000e-10 -7.125455111440e-01 
+ 7.328000000000e-10 -7.804238043085e-01 
+ 7.428000000000e-10 -8.071473680780e-01 
+ 7.528000000000e-10 -7.450494772754e-01 
+ 7.628000000000e-10 -5.335773499054e-01 
+ 7.728000000000e-10 -1.993230348361e-01 
+ 7.828000000000e-10  1.349793746975e-01 
+ 7.928000000000e-10  3.864055722387e-01 
+ 8.028000000000e-10  5.367539279153e-01 
+ 8.128000000000e-10  6.290427569852e-01 
+ 8.228000000000e-10  7.125002063044e-01 
+ 8.328000000000e-10  7.804668926767e-01 
+ 8.428000000000e-10  8.071042297758e-01 
+ 8.528000000000e-10  7.450922570276e-01 
+ 8.628000000000e-10  5.335323457615e-01 
+ 8.728000000000e-10  1.993673584870e-01 
+ 8.828000000000e-10 -1.350193573750e-01 
+ 8.928000000000e-10 -3.863660901230e-01 
+ 9.028000000000e-10 -5.367925035482e-01 
+ 9.128000000000e-10 -6.290039875175e-01 
+ 9.228000000000e-10 -7.125398122704e-01 
+ 9.328000000000e-10 -7.804294363608e-01 
+ 9.428000000000e-10 -8.071416857778e-01 
+ 9.528000000000e-10 -7.450548065452e-01 
+ 9.628000000000e-10 -5.335722743766e-01 
+ 9.728000000000e-10 -1.993280329539e-01 
+ 9.828000000000e-10  1.349843549639e-01 
+ 9.928000000000e-10  3.864011317450e-01 
+ 1.000000000000e-09  5.028020863733e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/conditions.yaml
new file mode 100644
index 00000000..ed692c0a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 9
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_09
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb.sch
new file mode 100644
index 00000000..db663a1f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb_10.data
new file mode 100644
index 00000000..973ede5e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_core_tb_10.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.293189432094e-01 
+ 1.728000000000e-10 -2.034299929592e-01 
+ 1.828000000000e-10  1.254532736892e-01 
+ 1.928000000000e-10  3.744603520131e-01 
+ 2.028000000000e-10  5.220595086358e-01 
+ 2.128000000000e-10  6.139346231694e-01 
+ 2.228000000000e-10  6.977077768020e-01 
+ 2.328000000000e-10  7.638951530454e-01 
+ 2.428000000000e-10  7.881008470503e-01 
+ 2.528000000000e-10  7.271434956617e-01 
+ 2.628000000000e-10  5.227259392947e-01 
+ 2.728000000000e-10  1.977807095317e-01 
+ 2.828000000000e-10 -1.296557480667e-01 
+ 2.928000000000e-10 -3.774966254092e-01 
+ 3.028000000000e-10 -5.245506032311e-01 
+ 3.128000000000e-10 -6.155925798862e-01 
+ 3.228000000000e-10 -6.989490114600e-01 
+ 3.328000000000e-10 -7.646204924296e-01 
+ 3.428000000000e-10 -7.887093478172e-01 
+ 3.528000000000e-10 -7.274783648153e-01 
+ 3.628000000000e-10 -5.231513423786e-01 
+ 3.728000000000e-10 -1.979863018154e-01 
+ 3.828000000000e-10  1.294013660930e-01 
+ 3.928000000000e-10  3.774276121382e-01 
+ 4.028000000000e-10  5.243833105689e-01 
+ 4.128000000000e-10  6.155813660155e-01 
+ 4.228000000000e-10  6.988272077165e-01 
+ 4.328000000000e-10  7.646509984988e-01 
+ 4.428000000000e-10  7.886185007607e-01 
+ 4.528000000000e-10  7.275266613790e-01 
+ 4.628000000000e-10  5.230676681296e-01 
+ 4.728000000000e-10  1.980405747385e-01 
+ 4.828000000000e-10 -1.294713662253e-01 
+ 4.928000000000e-10 -3.773761496757e-01 
+ 5.028000000000e-10 -5.244469821379e-01 
+ 5.128000000000e-10 -6.155294307936e-01 
+ 5.228000000000e-10 -6.988887956355e-01 
+ 5.328000000000e-10 -7.645972449904e-01 
+ 5.428000000000e-10 -7.886754254295e-01 
+ 5.528000000000e-10 -7.274706677122e-01 
+ 5.628000000000e-10 -5.231295350854e-01 
+ 5.728000000000e-10 -1.979806299381e-01 
+ 5.828000000000e-10  1.294187696545e-01 
+ 5.928000000000e-10  3.774292707563e-01 
+ 6.028000000000e-10  5.243961595933e-01 
+ 6.128000000000e-10  6.155814701559e-01 
+ 6.228000000000e-10  6.988355515168e-01 
+ 6.328000000000e-10  7.646484599731e-01 
+ 6.428000000000e-10  7.886243100181e-01 
+ 6.528000000000e-10  7.275215569265e-01 
+ 6.628000000000e-10  5.230764840752e-01 
+ 6.728000000000e-10  1.980332799823e-01 
+ 6.828000000000e-10 -1.294660192513e-01 
+ 6.928000000000e-10 -3.773827405650e-01 
+ 7.028000000000e-10 -5.244413520748e-01 
+ 7.128000000000e-10 -6.155361997798e-01 
+ 7.228000000000e-10 -6.988817029216e-01 
+ 7.328000000000e-10 -7.646043204444e-01 
+ 7.428000000000e-10 -7.886680576572e-01 
+ 7.528000000000e-10 -7.274772120684e-01 
+ 7.628000000000e-10 -5.231238849653e-01 
+ 7.728000000000e-10 -1.979860775160e-01 
+ 7.828000000000e-10  1.294249237809e-01 
+ 7.928000000000e-10  3.774244918330e-01 
+ 8.028000000000e-10  5.244015690321e-01 
+ 8.128000000000e-10  6.155771739165e-01 
+ 8.228000000000e-10  6.988402156207e-01 
+ 8.328000000000e-10  7.646441380646e-01 
+ 8.428000000000e-10  7.886285892332e-01 
+ 8.528000000000e-10  7.275167248781e-01 
+ 8.628000000000e-10  5.230825202638e-01 
+ 8.728000000000e-10  1.980273627479e-01 
+ 8.828000000000e-10 -1.294617038455e-01 
+ 8.928000000000e-10 -3.773878907236e-01 
+ 9.028000000000e-10 -5.244369215985e-01 
+ 9.128000000000e-10 -6.155414802599e-01 
+ 9.228000000000e-10 -6.988765421320e-01 
+ 9.328000000000e-10 -7.646094975483e-01 
+ 9.428000000000e-10 -7.886629049186e-01 
+ 9.528000000000e-10 -7.274820443091e-01 
+ 9.628000000000e-10 -5.231193961018e-01 
+ 9.728000000000e-10 -1.979905037884e-01 
+ 9.828000000000e-10  1.294294922144e-01 
+ 9.928000000000e-10  3.774205018001e-01 
+ 1.000000000000e-09  4.912603506308e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/conditions.yaml
new file mode 100644
index 00000000..9564492a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 10
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_10
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb.sch
new file mode 100644
index 00000000..fa5a1fa8
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb_11.data
new file mode 100644
index 00000000..799f8459
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_core_tb_11.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.473675478550e-01 
+ 1.728000000000e-10 -2.087893101739e-01 
+ 1.828000000000e-10  1.310494751476e-01 
+ 1.928000000000e-10  3.871555645678e-01 
+ 2.028000000000e-10  5.437689230363e-01 
+ 2.128000000000e-10  6.391330299748e-01 
+ 2.228000000000e-10  7.213082317981e-01 
+ 2.328000000000e-10  7.903248370025e-01 
+ 2.428000000000e-10  8.187618792919e-01 
+ 2.528000000000e-10  7.555729663838e-01 
+ 2.628000000000e-10  5.409345054541e-01 
+ 2.728000000000e-10  2.036912835862e-01 
+ 2.828000000000e-10 -1.345140506878e-01 
+ 2.928000000000e-10 -3.895370892644e-01 
+ 3.028000000000e-10 -5.457400052530e-01 
+ 3.128000000000e-10 -6.403498057265e-01 
+ 3.228000000000e-10 -7.222286336937e-01 
+ 3.328000000000e-10 -7.907911780827e-01 
+ 3.428000000000e-10 -8.192361080664e-01 
+ 3.528000000000e-10 -7.558198978931e-01 
+ 3.628000000000e-10 -5.413206307136e-01 
+ 3.728000000000e-10 -2.038438399825e-01 
+ 3.828000000000e-10  1.342763346632e-01 
+ 3.928000000000e-10  3.894921044587e-01 
+ 4.028000000000e-10  5.455616788274e-01 
+ 4.128000000000e-10  6.403489734683e-01 
+ 4.228000000000e-10  7.220944352324e-01 
+ 4.328000000000e-10  7.908322596821e-01 
+ 4.428000000000e-10  8.191363162855e-01 
+ 4.528000000000e-10  7.558824803046e-01 
+ 4.628000000000e-10  5.412307821184e-01 
+ 4.728000000000e-10  2.039121351986e-01 
+ 4.828000000000e-10 -1.343528713892e-01 
+ 4.928000000000e-10 -3.894290190191e-01 
+ 5.028000000000e-10 -5.456335562174e-01 
+ 5.128000000000e-10 -6.402860869065e-01 
+ 5.228000000000e-10 -7.221652152444e-01 
+ 5.328000000000e-10 -7.907686614943e-01 
+ 5.428000000000e-10 -8.192023796026e-01 
+ 5.528000000000e-10 -7.558173441778e-01 
+ 5.628000000000e-10 -5.413004970284e-01 
+ 5.728000000000e-10 -2.038447386050e-01 
+ 5.828000000000e-10  1.342913524064e-01 
+ 5.928000000000e-10  3.894897157728e-01 
+ 6.028000000000e-10  5.455737058766e-01 
+ 6.128000000000e-10  6.403462778603e-01 
+ 6.228000000000e-10  7.221032530671e-01 
+ 6.328000000000e-10  7.908278354740e-01 
+ 6.428000000000e-10  8.191430293573e-01 
+ 6.528000000000e-10  7.558759446864e-01 
+ 6.628000000000e-10  5.412396296665e-01 
+ 6.728000000000e-10  2.039046702204e-01 
+ 6.828000000000e-10 -1.343459163903e-01 
+ 6.928000000000e-10 -3.894366779769e-01 
+ 7.028000000000e-10 -5.456262483653e-01 
+ 7.128000000000e-10 -6.402940065215e-01 
+ 7.228000000000e-10 -7.221570137640e-01 
+ 7.328000000000e-10 -7.907769448806e-01 
+ 7.428000000000e-10 -8.191938542033e-01 
+ 7.528000000000e-10 -7.558251320231e-01 
+ 7.628000000000e-10 -5.412933191298e-01 
+ 7.728000000000e-10 -2.038518419443e-01 
+ 7.828000000000e-10  1.342982918430e-01 
+ 7.928000000000e-10  3.894837914532e-01 
+ 8.028000000000e-10  5.455799247329e-01 
+ 8.128000000000e-10  6.403408689327e-01 
+ 8.228000000000e-10  7.221089932485e-01 
+ 8.328000000000e-10  7.908225333386e-01 
+ 8.428000000000e-10  8.191482615363e-01 
+ 8.528000000000e-10  7.558702665648e-01 
+ 8.628000000000e-10  5.412462517638e-01 
+ 8.728000000000e-10  2.038984202104e-01 
+ 8.828000000000e-10 -1.343404705774e-01 
+ 8.928000000000e-10 -3.894425333092e-01 
+ 9.028000000000e-10 -5.456206778041e-01 
+ 9.128000000000e-10 -6.403000729433e-01 
+ 9.228000000000e-10 -7.221509667404e-01 
+ 9.328000000000e-10 -7.907829740936e-01 
+ 9.428000000000e-10 -8.191877974471e-01 
+ 9.528000000000e-10 -7.558308764830e-01 
+ 9.628000000000e-10 -5.412878201925e-01 
+ 9.728000000000e-10 -2.038573569097e-01 
+ 9.828000000000e-10  1.343035264203e-01 
+ 9.928000000000e-10  3.894790170617e-01 
+ 1.000000000000e-09  5.100069898815e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/conditions.yaml
new file mode 100644
index 00000000..18507a3d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 11
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_11
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb.sch
new file mode 100644
index 00000000..c0d8e471
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb_12.data
new file mode 100644
index 00000000..db4e4cce
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_core_tb_12.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.049557277618e-01 
+ 1.728000000000e-10 -1.958466480437e-01 
+ 1.828000000000e-10  1.196319367700e-01 
+ 1.928000000000e-10  3.700244189406e-01 
+ 2.028000000000e-10  5.308067637731e-01 
+ 2.128000000000e-10  6.311299202315e-01 
+ 2.228000000000e-10  7.086540860403e-01 
+ 2.328000000000e-10  7.625529356493e-01 
+ 2.428000000000e-10  7.708473475114e-01 
+ 2.528000000000e-10  6.980446990655e-01 
+ 2.628000000000e-10  4.981026307256e-01 
+ 2.728000000000e-10  1.904449044265e-01 
+ 2.828000000000e-10 -1.236510258628e-01 
+ 2.928000000000e-10 -3.730975798774e-01 
+ 3.028000000000e-10 -5.333436235403e-01 
+ 3.128000000000e-10 -6.328422885796e-01 
+ 3.228000000000e-10 -7.099622515515e-01 
+ 3.328000000000e-10 -7.633093670089e-01 
+ 3.428000000000e-10 -7.714462858000e-01 
+ 3.528000000000e-10 -6.983543456334e-01 
+ 3.628000000000e-10 -4.984830350414e-01 
+ 3.728000000000e-10 -1.906133898346e-01 
+ 3.828000000000e-10  1.234140438752e-01 
+ 3.928000000000e-10  3.730258572177e-01 
+ 4.028000000000e-10  5.331667972487e-01 
+ 4.128000000000e-10  6.328214645319e-01 
+ 4.228000000000e-10  7.098336990067e-01 
+ 4.328000000000e-10  7.633335528675e-01 
+ 4.428000000000e-10  7.713603033543e-01 
+ 4.528000000000e-10  6.984040906368e-01 
+ 4.628000000000e-10  4.984087981115e-01 
+ 4.728000000000e-10  1.906698925098e-01 
+ 4.828000000000e-10 -1.234792426423e-01 
+ 4.928000000000e-10 -3.729733539485e-01 
+ 5.028000000000e-10 -5.332277682129e-01 
+ 5.128000000000e-10 -6.327690017914e-01 
+ 5.228000000000e-10 -7.098933602520e-01 
+ 5.328000000000e-10 -7.632805035294e-01 
+ 5.428000000000e-10 -7.714147767047e-01 
+ 5.528000000000e-10 -6.983493927960e-01 
+ 5.628000000000e-10 -4.984657326360e-01 
+ 5.728000000000e-10 -1.906133403657e-01 
+ 5.828000000000e-10  1.234275058651e-01 
+ 5.928000000000e-10  3.730246636548e-01 
+ 6.028000000000e-10  5.331775888699e-01 
+ 6.128000000000e-10  6.328197652536e-01 
+ 6.228000000000e-10  7.098419058182e-01 
+ 6.328000000000e-10  7.633301342197e-01 
+ 6.428000000000e-10  7.713661487972e-01 
+ 6.528000000000e-10  6.983986251010e-01 
+ 6.628000000000e-10  4.984160910452e-01 
+ 6.728000000000e-10  1.906635868460e-01 
+ 6.828000000000e-10 -1.234734747225e-01 
+ 6.928000000000e-10 -3.729797013887e-01 
+ 7.028000000000e-10 -5.332215969565e-01 
+ 7.128000000000e-10 -6.327757131741e-01 
+ 7.228000000000e-10 -7.098865351622e-01 
+ 7.328000000000e-10 -7.632871392149e-01 
+ 7.428000000000e-10 -7.714081948986e-01 
+ 7.528000000000e-10 -6.983555969606e-01 
+ 7.628000000000e-10 -4.984601688237e-01 
+ 7.728000000000e-10 -1.906192454806e-01 
+ 7.828000000000e-10  1.234332321656e-01 
+ 7.928000000000e-10  3.730195983111e-01 
+ 8.028000000000e-10  5.331826746949e-01 
+ 8.128000000000e-10  6.328151783475e-01 
+ 8.228000000000e-10  7.098466992587e-01 
+ 8.328000000000e-10  7.633256332241e-01 
+ 8.428000000000e-10  7.713705417094e-01 
+ 8.528000000000e-10  6.983937777920e-01 
+ 8.628000000000e-10  4.984215072239e-01 
+ 8.728000000000e-10  1.906583322627e-01 
+ 8.828000000000e-10 -1.234689419945e-01 
+ 8.928000000000e-10 -3.729845695752e-01 
+ 9.028000000000e-10 -5.332169477613e-01 
+ 9.128000000000e-10 -6.327807857544e-01 
+ 9.228000000000e-10 -7.098815617208e-01 
+ 9.328000000000e-10 -7.632920474235e-01 
+ 9.428000000000e-10 -7.714033753149e-01 
+ 9.528000000000e-10 -6.983602366678e-01 
+ 9.628000000000e-10 -4.984557776243e-01 
+ 9.728000000000e-10 -1.906237729891e-01 
+ 9.828000000000e-10  1.234375916302e-01 
+ 9.928000000000e-10  3.730155682884e-01 
+ 1.000000000000e-09  4.959193237551e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/conditions.yaml
new file mode 100644
index 00000000..ba5a292d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 12
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_12
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb.sch
new file mode 100644
index 00000000..e4f89ede
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb_13.data
new file mode 100644
index 00000000..abbd3617
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_core_tb_13.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.935497259980e-01 
+ 1.728000000000e-10 -1.928633983658e-01 
+ 1.828000000000e-10  1.160949240371e-01 
+ 1.928000000000e-10  3.619360857197e-01 
+ 2.028000000000e-10  5.185143131218e-01 
+ 2.128000000000e-10  6.170086772416e-01 
+ 2.228000000000e-10  6.939063598865e-01 
+ 2.328000000000e-10  7.457993341265e-01 
+ 2.428000000000e-10  7.520509596304e-01 
+ 2.528000000000e-10  6.804739824857e-01 
+ 2.628000000000e-10  4.870426149481e-01 
+ 2.728000000000e-10  1.875308246798e-01 
+ 2.828000000000e-10 -1.202389208092e-01 
+ 2.928000000000e-10 -3.651754434827e-01 
+ 3.028000000000e-10 -5.211918880427e-01 
+ 3.128000000000e-10 -6.188469707889e-01 
+ 3.228000000000e-10 -6.953072467312e-01 
+ 3.328000000000e-10 -7.466129151979e-01 
+ 3.428000000000e-10 -7.526565311823e-01 
+ 3.528000000000e-10 -6.807675409917e-01 
+ 3.628000000000e-10 -4.873945801883e-01 
+ 3.728000000000e-10 -1.876809763872e-01 
+ 3.828000000000e-10  1.200199744899e-01 
+ 3.928000000000e-10  3.651151173578e-01 
+ 4.028000000000e-10  5.210322421793e-01 
+ 4.128000000000e-10  6.188330192958e-01 
+ 4.228000000000e-10  6.951893716680e-01 
+ 4.328000000000e-10  7.466394998986e-01 
+ 4.428000000000e-10  7.525773069027e-01 
+ 4.528000000000e-10  6.808165070916e-01 
+ 4.628000000000e-10  4.873248087716e-01 
+ 4.728000000000e-10  1.877358679741e-01 
+ 4.828000000000e-10 -1.200819840902e-01 
+ 4.928000000000e-10 -3.650646413699e-01 
+ 5.028000000000e-10 -5.210903047408e-01 
+ 5.128000000000e-10 -6.187830156405e-01 
+ 5.228000000000e-10 -6.952462050643e-01 
+ 5.328000000000e-10 -7.465883056072e-01 
+ 5.428000000000e-10 -7.526293067125e-01 
+ 5.528000000000e-10 -6.807638103361e-01 
+ 5.628000000000e-10 -4.873795115625e-01 
+ 5.728000000000e-10 -1.876807689254e-01 
+ 5.828000000000e-10  1.200326256254e-01 
+ 5.928000000000e-10  3.651139754788e-01 
+ 6.028000000000e-10  5.210426454606e-01 
+ 6.128000000000e-10  6.188315227579e-01 
+ 6.228000000000e-10  6.951972695911e-01 
+ 6.328000000000e-10  7.466359762403e-01 
+ 6.428000000000e-10  7.525829976005e-01 
+ 6.528000000000e-10  6.808110143898e-01 
+ 6.628000000000e-10  4.873318873720e-01 
+ 6.728000000000e-10  1.877292356433e-01 
+ 6.828000000000e-10 -1.200767202072e-01 
+ 6.928000000000e-10 -3.650706499628e-01 
+ 7.028000000000e-10 -5.210847183857e-01 
+ 7.128000000000e-10 -6.187893543189e-01 
+ 7.228000000000e-10 -6.952399017798e-01 
+ 7.328000000000e-10 -7.465944604664e-01 
+ 7.428000000000e-10 -7.526232942576e-01 
+ 7.528000000000e-10 -6.807695137827e-01 
+ 7.628000000000e-10 -4.873744121182e-01 
+ 7.728000000000e-10 -1.876860880622e-01 
+ 7.828000000000e-10  1.200380835632e-01 
+ 7.928000000000e-10  3.651091778387e-01 
+ 8.028000000000e-10  5.210475167171e-01 
+ 8.128000000000e-10  6.188272213187e-01 
+ 8.228000000000e-10  6.952018279574e-01 
+ 8.328000000000e-10  7.466316140292e-01 
+ 8.428000000000e-10  7.525872528114e-01 
+ 8.528000000000e-10  6.808063071094e-01 
+ 8.628000000000e-10  4.873371355126e-01 
+ 8.728000000000e-10  1.877239857571e-01 
+ 8.828000000000e-10 -1.200724809112e-01 
+ 8.928000000000e-10 -3.650752679165e-01 
+ 9.028000000000e-10 -5.210804068397e-01 
+ 9.128000000000e-10 -6.187941569931e-01 
+ 9.228000000000e-10 -6.952352466105e-01 
+ 9.328000000000e-10 -7.465990720366e-01 
+ 9.428000000000e-10 -7.526188226163e-01 
+ 9.528000000000e-10 -6.807738360998e-01 
+ 9.628000000000e-10 -4.873703126609e-01 
+ 9.728000000000e-10 -1.876902725775e-01 
+ 9.828000000000e-10  1.200422409457e-01 
+ 9.928000000000e-10  3.651053453859e-01 
+ 1.000000000000e-09  4.847952698035e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/conditions.yaml
new file mode 100644
index 00000000..71d8574d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 13
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_13
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb.sch
new file mode 100644
index 00000000..735ac191
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb_14.data
new file mode 100644
index 00000000..3796cea3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_core_tb_14.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.133282675634e-01 
+ 1.728000000000e-10 -2.031582081928e-01 
+ 1.828000000000e-10  1.144804838339e-01 
+ 1.928000000000e-10  3.698591588516e-01 
+ 2.028000000000e-10  5.380258146680e-01 
+ 2.128000000000e-10  6.422542980920e-01 
+ 2.228000000000e-10  7.191574927620e-01 
+ 2.328000000000e-10  7.734390216007e-01 
+ 2.428000000000e-10  7.823512104827e-01 
+ 2.528000000000e-10  7.081342613122e-01 
+ 2.628000000000e-10  5.065809773945e-01 
+ 2.728000000000e-10  1.980707374060e-01 
+ 2.828000000000e-10 -1.181831896095e-01 
+ 2.928000000000e-10 -3.727163876319e-01 
+ 3.028000000000e-10 -5.404428949084e-01 
+ 3.128000000000e-10 -6.438704305572e-01 
+ 3.228000000000e-10 -7.204145434420e-01 
+ 3.328000000000e-10 -7.741471374370e-01 
+ 3.428000000000e-10 -7.829309638154e-01 
+ 3.528000000000e-10 -7.084110972821e-01 
+ 3.628000000000e-10 -5.069426471107e-01 
+ 3.728000000000e-10 -1.982066720174e-01 
+ 3.828000000000e-10  1.179564926067e-01 
+ 3.928000000000e-10  3.726621714283e-01 
+ 4.028000000000e-10  5.402630628674e-01 
+ 4.128000000000e-10  6.438601752956e-01 
+ 4.228000000000e-10  7.202791375194e-01 
+ 4.328000000000e-10  7.741793827377e-01 
+ 4.428000000000e-10  7.828380754967e-01 
+ 4.528000000000e-10  7.084693803333e-01 
+ 4.628000000000e-10  5.068627667504e-01 
+ 4.728000000000e-10  1.982719515445e-01 
+ 4.828000000000e-10 -1.180275895897e-01 
+ 4.928000000000e-10 -3.726028735362e-01 
+ 5.028000000000e-10 -5.403301024789e-01 
+ 5.128000000000e-10 -6.438008084190e-01 
+ 5.228000000000e-10 -7.203455420725e-01 
+ 5.328000000000e-10 -7.741198297783e-01 
+ 5.428000000000e-10 -7.828987326701e-01 
+ 5.528000000000e-10 -7.084084859242e-01 
+ 5.628000000000e-10 -5.069251044876e-01 
+ 5.728000000000e-10 -1.982094732584e-01 
+ 5.828000000000e-10  1.179697981212e-01 
+ 5.928000000000e-10  3.726595322461e-01 
+ 6.028000000000e-10  5.402739437431e-01 
+ 6.128000000000e-10  6.438573026479e-01 
+ 6.228000000000e-10  7.202880216174e-01 
+ 6.328000000000e-10  7.741750830136e-01 
+ 6.428000000000e-10  7.828445699494e-01 
+ 6.528000000000e-10  7.084631989914e-01 
+ 6.628000000000e-10  5.068703543607e-01 
+ 6.728000000000e-10  1.982651160797e-01 
+ 6.828000000000e-10 -1.180209524418e-01 
+ 6.928000000000e-10 -3.726100259571e-01 
+ 7.028000000000e-10 -5.403229404029e-01 
+ 7.128000000000e-10 -6.438083895554e-01 
+ 7.228000000000e-10 -7.203378638829e-01 
+ 7.328000000000e-10 -7.741273273776e-01 
+ 7.428000000000e-10 -7.828912312659e-01 
+ 7.528000000000e-10 -7.084155733246e-01 
+ 7.628000000000e-10 -5.069185371484e-01 
+ 7.728000000000e-10 -1.982163796445e-01 
+ 7.828000000000e-10  1.179761824049e-01 
+ 7.928000000000e-10  3.726538824343e-01 
+ 8.028000000000e-10  5.402795684719e-01 
+ 8.128000000000e-10  6.438520994328e-01 
+ 8.228000000000e-10  7.202935093188e-01 
+ 8.328000000000e-10  7.741699689895e-01 
+ 8.428000000000e-10  7.828494756723e-01 
+ 8.528000000000e-10  7.084578188073e-01 
+ 8.628000000000e-10  5.068761410729e-01 
+ 8.728000000000e-10  1.982594122387e-01 
+ 8.828000000000e-10 -1.180157633845e-01 
+ 8.928000000000e-10 -3.726154653834e-01 
+ 9.028000000000e-10 -5.403175771302e-01 
+ 9.128000000000e-10 -6.438140825829e-01 
+ 9.228000000000e-10 -7.203322576361e-01 
+ 9.328000000000e-10 -7.741328388949e-01 
+ 9.428000000000e-10 -7.828857350121e-01 
+ 9.528000000000e-10 -7.084208512479e-01 
+ 9.628000000000e-10 -5.069134738545e-01 
+ 9.728000000000e-10 -1.982215797151e-01 
+ 9.828000000000e-10  1.179810466336e-01 
+ 9.928000000000e-10  3.726493985613e-01 
+ 1.000000000000e-09  5.010433738758e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/conditions.yaml
new file mode 100644
index 00000000..13aeb15d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 14
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_14
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb.sch
new file mode 100644
index 00000000..4d031f0e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb_15.data
new file mode 100644
index 00000000..a18684b0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_core_tb_15.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.764925698370e-01 
+ 1.728000000000e-10 -1.934019301872e-01 
+ 1.828000000000e-10  1.027850457497e-01 
+ 1.928000000000e-10  3.499528968595e-01 
+ 2.028000000000e-10  5.186059326128e-01 
+ 2.128000000000e-10  6.254912177700e-01 
+ 2.228000000000e-10  6.994356057335e-01 
+ 2.328000000000e-10  7.419604616039e-01 
+ 2.428000000000e-10  7.366001230119e-01 
+ 2.528000000000e-10  6.575586826882e-01 
+ 2.628000000000e-10  4.703480039804e-01 
+ 2.728000000000e-10  1.887311437228e-01 
+ 2.828000000000e-10 -1.064955609068e-01 
+ 2.928000000000e-10 -3.530674432656e-01 
+ 3.028000000000e-10 -5.214103928852e-01 
+ 3.128000000000e-10 -6.276329249236e-01 
+ 3.228000000000e-10 -7.010919569868e-01 
+ 3.328000000000e-10 -7.428528846984e-01 
+ 3.428000000000e-10 -7.371070425945e-01 
+ 3.528000000000e-10 -6.576931102984e-01 
+ 3.628000000000e-10 -4.705213908487e-01 
+ 3.728000000000e-10 -1.887451417089e-01 
+ 3.828000000000e-10  1.063771169054e-01 
+ 3.928000000000e-10  3.530644558224e-01 
+ 4.028000000000e-10  5.212882945537e-01 
+ 4.128000000000e-10  6.276273956697e-01 
+ 4.228000000000e-10  7.009872983885e-01 
+ 4.328000000000e-10  7.428850006835e-01 
+ 4.428000000000e-10  7.370483197885e-01 
+ 4.528000000000e-10  6.577532995019e-01 
+ 4.628000000000e-10  4.704734311564e-01 
+ 4.728000000000e-10  1.888066765622e-01 
+ 4.828000000000e-10 -1.064251900033e-01 
+ 4.928000000000e-10 -3.530110058012e-01 
+ 5.028000000000e-10 -5.213363794122e-01 
+ 5.128000000000e-10 -6.275779961821e-01 
+ 5.228000000000e-10 -7.010367362436e-01 
+ 5.328000000000e-10 -7.428359180794e-01 
+ 5.428000000000e-10 -7.370946234404e-01 
+ 5.528000000000e-10 -6.577041924295e-01 
+ 5.628000000000e-10 -4.705211118057e-01 
+ 5.728000000000e-10 -1.887571402743e-01 
+ 5.828000000000e-10  1.063798390696e-01 
+ 5.928000000000e-10  3.530562876751e-01 
+ 6.028000000000e-10  5.212929538773e-01 
+ 6.128000000000e-10  6.276223718978e-01 
+ 6.228000000000e-10  7.009927681762e-01 
+ 6.328000000000e-10  7.428797293753e-01 
+ 6.428000000000e-10  7.370526578677e-01 
+ 6.528000000000e-10  6.577470674825e-01 
+ 6.628000000000e-10  4.704784998901e-01 
+ 6.728000000000e-10  1.888003575241e-01 
+ 6.828000000000e-10 -1.064204487643e-01 
+ 6.928000000000e-10 -3.530168946500e-01 
+ 7.028000000000e-10 -5.213312567329e-01 
+ 7.128000000000e-10 -6.275838929681e-01 
+ 7.228000000000e-10 -7.010312441909e-01 
+ 7.328000000000e-10 -7.428415937954e-01 
+ 7.428000000000e-10 -7.370893810626e-01 
+ 7.528000000000e-10 -6.577094889087e-01 
+ 7.628000000000e-10 -4.705162397262e-01 
+ 7.728000000000e-10 -1.887623115300e-01 
+ 7.828000000000e-10  1.063847513579e-01 
+ 7.928000000000e-10  3.530516705381e-01 
+ 8.028000000000e-10  5.212973590939e-01 
+ 8.128000000000e-10  6.276181223045e-01 
+ 8.228000000000e-10  7.009970786285e-01 
+ 8.328000000000e-10  7.428754735512e-01 
+ 8.428000000000e-10  7.370567570344e-01 
+ 8.528000000000e-10  6.577427030952e-01 
+ 8.628000000000e-10  4.704830497474e-01 
+ 8.728000000000e-10  1.887958404937e-01 
+ 8.828000000000e-10 -1.064163174914e-01 
+ 8.928000000000e-10 -3.530210908451e-01 
+ 9.028000000000e-10 -5.213271590930e-01 
+ 9.128000000000e-10 -6.275881896870e-01 
+ 9.228000000000e-10 -7.010270518598e-01 
+ 9.328000000000e-10 -7.428457852801e-01 
+ 9.428000000000e-10 -7.370853633469e-01 
+ 9.528000000000e-10 -6.577134719194e-01 
+ 9.628000000000e-10 -4.705123783357e-01 
+ 9.728000000000e-10 -1.887662540331e-01 
+ 9.828000000000e-10  1.063885555413e-01 
+ 9.928000000000e-10  3.530480784075e-01 
+ 1.000000000000e-09  4.814572085440e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/conditions.yaml
new file mode 100644
index 00000000..827a3bae
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 15
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_15
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb.sch
new file mode 100644
index 00000000..a8832cf1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb_16.data
new file mode 100644
index 00000000..5b9b7365
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_core_tb_16.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.643042367579e-01 
+ 1.728000000000e-10 -1.889536448800e-01 
+ 1.828000000000e-10  1.011027156160e-01 
+ 1.928000000000e-10  3.431119917378e-01 
+ 2.028000000000e-10  5.070519088353e-01 
+ 2.128000000000e-10  6.112991757094e-01 
+ 2.228000000000e-10  6.838020209744e-01 
+ 2.328000000000e-10  7.242864479517e-01 
+ 2.428000000000e-10  7.174167448313e-01 
+ 2.528000000000e-10  6.398083866093e-01 
+ 2.628000000000e-10  4.585166519927e-01 
+ 2.728000000000e-10  1.844271573483e-01 
+ 2.828000000000e-10 -1.048019054065e-01 
+ 2.928000000000e-10 -3.462317584687e-01 
+ 3.028000000000e-10 -5.098344721858e-01 
+ 3.128000000000e-10 -6.133899227371e-01 
+ 3.228000000000e-10 -6.853968517792e-01 
+ 3.328000000000e-10 -7.251059393871e-01 
+ 3.428000000000e-10 -7.178642533065e-01 
+ 3.528000000000e-10 -6.398898931720e-01 
+ 3.628000000000e-10 -4.586473976402e-01 
+ 3.728000000000e-10 -1.843989570585e-01 
+ 3.828000000000e-10  1.047140758745e-01 
+ 3.928000000000e-10  3.462576483703e-01 
+ 4.028000000000e-10  5.097333770465e-01 
+ 4.128000000000e-10  6.134023110554e-01 
+ 4.228000000000e-10  6.853047053340e-01 
+ 4.328000000000e-10  7.251501511308e-01 
+ 4.428000000000e-10  7.178117501486e-01 
+ 4.528000000000e-10  6.399568281317e-01 
+ 4.628000000000e-10  4.586017943502e-01 
+ 4.728000000000e-10  1.844658494373e-01 
+ 4.828000000000e-10 -1.047609876408e-01 
+ 4.928000000000e-10 -3.462003104379e-01 
+ 5.028000000000e-10 -5.097813732572e-01 
+ 5.128000000000e-10 -6.133504189098e-01 
+ 5.228000000000e-10 -6.853547602223e-01 
+ 5.328000000000e-10 -7.250985458364e-01 
+ 5.428000000000e-10 -7.178593251267e-01 
+ 5.528000000000e-10 -6.399055102013e-01 
+ 5.628000000000e-10 -4.586511534755e-01 
+ 5.728000000000e-10 -1.844138975484e-01 
+ 5.828000000000e-10  1.047143295024e-01 
+ 5.928000000000e-10  3.462472486482e-01 
+ 6.028000000000e-10  5.097369504642e-01 
+ 6.128000000000e-10  6.133959963639e-01 
+ 6.228000000000e-10  6.853096740322e-01 
+ 6.328000000000e-10  7.251438129543e-01 
+ 6.428000000000e-10  7.178160816468e-01 
+ 6.528000000000e-10  6.399498616471e-01 
+ 6.628000000000e-10  4.586069220749e-01 
+ 6.728000000000e-10  1.844588245643e-01 
+ 6.828000000000e-10 -1.047563687876e-01 
+ 6.928000000000e-10 -3.462063328010e-01 
+ 7.028000000000e-10 -5.097765086741e-01 
+ 7.128000000000e-10 -6.133562893232e-01 
+ 7.228000000000e-10 -6.853494321266e-01 
+ 7.328000000000e-10 -7.251041291885e-01 
+ 7.428000000000e-10 -7.178542203751e-01 
+ 7.528000000000e-10 -6.399107355976e-01 
+ 7.628000000000e-10 -4.586462738291e-01 
+ 7.728000000000e-10 -1.844190131957e-01 
+ 7.828000000000e-10  1.047193339603e-01 
+ 7.928000000000e-10  3.462424630766e-01 
+ 8.028000000000e-10  5.097415276109e-01 
+ 8.128000000000e-10  6.133915881396e-01 
+ 8.228000000000e-10  6.853141467162e-01 
+ 8.328000000000e-10  7.251393167662e-01 
+ 8.428000000000e-10  7.178204152808e-01 
+ 8.528000000000e-10  6.399452651751e-01 
+ 8.628000000000e-10  4.586116651576e-01 
+ 8.728000000000e-10  1.844540563551e-01 
+ 8.828000000000e-10 -1.047521530128e-01 
+ 8.928000000000e-10 -3.462105768541e-01 
+ 9.028000000000e-10 -5.097724238353e-01 
+ 9.128000000000e-10 -6.133605792288e-01 
+ 9.228000000000e-10 -6.853452315529e-01 
+ 9.328000000000e-10 -7.251083207568e-01 
+ 9.428000000000e-10 -7.178502144615e-01 
+ 9.528000000000e-10 -6.399147306347e-01 
+ 9.628000000000e-10 -4.586423495280e-01 
+ 9.728000000000e-10 -1.844229988419e-01 
+ 9.828000000000e-10  1.047232268776e-01 
+ 9.928000000000e-10  3.462387497741e-01 
+ 1.000000000000e-09  4.710752262880e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/conditions.yaml
new file mode 100644
index 00000000..645395ae
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 16
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_16
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb.sch
new file mode 100644
index 00000000..5764795e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb_17.data
new file mode 100644
index 00000000..15600382
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_core_tb_17.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.852886719505e-01 
+ 1.728000000000e-10 -2.023606658915e-01 
+ 1.828000000000e-10  9.500407548716e-02 
+ 1.928000000000e-10  3.473018630854e-01 
+ 2.028000000000e-10  5.238539974445e-01 
+ 2.128000000000e-10  6.356942626004e-01 
+ 2.228000000000e-10  7.106560719901e-01 
+ 2.328000000000e-10  7.539243132234e-01 
+ 2.428000000000e-10  7.486736309564e-01 
+ 2.528000000000e-10  6.681985082542e-01 
+ 2.628000000000e-10  4.800908099257e-01 
+ 2.728000000000e-10  1.985903293754e-01 
+ 2.828000000000e-10 -9.801965724844e-02 
+ 2.928000000000e-10 -3.499456539083e-01 
+ 3.028000000000e-10 -5.264166063204e-01 
+ 3.128000000000e-10 -6.377599985577e-01 
+ 3.228000000000e-10 -7.123258227204e-01 
+ 3.328000000000e-10 -7.548386637736e-01 
+ 3.428000000000e-10 -7.491646196322e-01 
+ 3.528000000000e-10 -6.682802381819e-01 
+ 3.628000000000e-10 -4.802044877583e-01 
+ 3.728000000000e-10 -1.985554586747e-01 
+ 3.828000000000e-10  9.793570714348e-02 
+ 3.928000000000e-10  3.499705083814e-01 
+ 4.028000000000e-10  5.263126851869e-01 
+ 4.128000000000e-10  6.377668221774e-01 
+ 4.228000000000e-10  7.122256281615e-01 
+ 4.328000000000e-10  7.548735616237e-01 
+ 4.428000000000e-10  7.491068615558e-01 
+ 4.528000000000e-10  6.683430307676e-01 
+ 4.628000000000e-10  4.801581700099e-01 
+ 4.728000000000e-10  1.986186025664e-01 
+ 4.828000000000e-10 -9.798359332438e-02 
+ 4.928000000000e-10 -3.499159407959e-01 
+ 5.028000000000e-10 -5.263605524234e-01 
+ 5.128000000000e-10 -6.377159898188e-01 
+ 5.228000000000e-10 -7.122753084256e-01 
+ 5.328000000000e-10 -7.548237332543e-01 
+ 5.428000000000e-10 -7.491535548765e-01 
+ 5.528000000000e-10 -6.682936663178e-01 
+ 5.628000000000e-10 -4.802057994081e-01 
+ 5.728000000000e-10 -1.985692377738e-01 
+ 5.828000000000e-10  9.793754425938e-02 
+ 5.928000000000e-10  3.499612594703e-01 
+ 6.028000000000e-10  5.263165540334e-01 
+ 6.128000000000e-10  6.377608692391e-01 
+ 6.228000000000e-10  7.122309292959e-01 
+ 6.328000000000e-10  7.548679483739e-01 
+ 6.428000000000e-10  7.491113260135e-01 
+ 6.528000000000e-10  6.683367510584e-01 
+ 6.628000000000e-10  4.801631540398e-01 
+ 6.728000000000e-10  1.986123746205e-01 
+ 6.828000000000e-10 -9.797860547701e-02 
+ 6.928000000000e-10 -3.499219086015e-01 
+ 7.028000000000e-10 -5.263552271330e-01 
+ 7.128000000000e-10 -6.377219921840e-01 
+ 7.228000000000e-10 -7.122696952774e-01 
+ 7.328000000000e-10 -7.548295298651e-01 
+ 7.428000000000e-10 -7.491481908175e-01 
+ 7.528000000000e-10 -6.682991221138e-01 
+ 7.628000000000e-10 -4.802006967346e-01 
+ 7.728000000000e-10 -1.985745887274e-01 
+ 7.828000000000e-10  9.794256695295e-02 
+ 7.928000000000e-10  3.499565849765e-01 
+ 8.028000000000e-10  5.263210489698e-01 
+ 8.128000000000e-10  6.377564579322e-01 
+ 8.228000000000e-10  7.122353719246e-01 
+ 8.328000000000e-10  7.548635649925e-01 
+ 8.428000000000e-10  7.491155123701e-01 
+ 8.528000000000e-10  6.683323549155e-01 
+ 8.628000000000e-10  4.801676539865e-01 
+ 8.728000000000e-10  1.986078923136e-01 
+ 8.828000000000e-10 -9.797434132868e-02 
+ 8.928000000000e-10 -3.499261582655e-01 
+ 9.028000000000e-10 -5.263510069851e-01 
+ 9.128000000000e-10 -6.377263524572e-01 
+ 9.228000000000e-10 -7.122654282965e-01 
+ 9.328000000000e-10 -7.548337908470e-01 
+ 9.428000000000e-10 -7.491440991364e-01 
+ 9.528000000000e-10 -6.683032069827e-01 
+ 9.628000000000e-10 -4.801967157057e-01 
+ 9.728000000000e-10 -1.985786291727e-01 
+ 9.828000000000e-10  9.794644208878e-02 
+ 9.928000000000e-10  3.499529545785e-01 
+ 1.000000000000e-09  4.843355885316e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/conditions.yaml
new file mode 100644
index 00000000..6dde0b42
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 17
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_17
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb.sch
new file mode 100644
index 00000000..dee2e392
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb_18.data
new file mode 100644
index 00000000..6bdb4a2e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_core_tb_18.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.747244840755e-01 
+ 1.728000000000e-10  2.031348680811e-01 
+ 1.828000000000e-10 -1.640358346053e-01 
+ 1.928000000000e-10 -4.121983890365e-01 
+ 2.028000000000e-10 -5.403960481430e-01 
+ 2.128000000000e-10 -6.175267008304e-01 
+ 2.228000000000e-10 -7.185181164841e-01 
+ 2.328000000000e-10 -8.111835866476e-01 
+ 2.428000000000e-10 -8.505757111821e-01 
+ 2.528000000000e-10 -7.941523888433e-01 
+ 2.628000000000e-10 -5.697557803605e-01 
+ 2.728000000000e-10 -1.993901761575e-01 
+ 2.828000000000e-10  1.667454340744e-01 
+ 2.928000000000e-10  4.143424459307e-01 
+ 3.028000000000e-10  5.421310172268e-01 
+ 3.128000000000e-10  6.189024162340e-01 
+ 3.228000000000e-10  7.194369498053e-01 
+ 3.328000000000e-10  8.117600127730e-01 
+ 3.428000000000e-10  8.508336653308e-01 
+ 3.528000000000e-10  7.942656656211e-01 
+ 3.628000000000e-10  5.697751550033e-01 
+ 3.728000000000e-10  1.994135726672e-01 
+ 3.828000000000e-10 -1.667386419247e-01 
+ 3.928000000000e-10 -4.143148464313e-01 
+ 4.028000000000e-10 -5.421262038320e-01 
+ 4.128000000000e-10 -6.188832903749e-01 
+ 4.228000000000e-10 -7.194346712496e-01 
+ 4.328000000000e-10 -8.117442314974e-01 
+ 4.428000000000e-10 -8.508381039982e-01 
+ 4.528000000000e-10 -7.942559196005e-01 
+ 4.628000000000e-10 -5.697859373045e-01 
+ 4.728000000000e-10 -1.993975895742e-01 
+ 4.828000000000e-10  1.667322235508e-01 
+ 4.928000000000e-10  4.143280512458e-01 
+ 5.028000000000e-10  5.421195877560e-01 
+ 5.128000000000e-10  6.188968586913e-01 
+ 5.228000000000e-10  7.194236426239e-01 
+ 5.328000000000e-10  8.117540342679e-01 
+ 5.428000000000e-10  8.508266757829e-01 
+ 5.528000000000e-10  7.942652287581e-01 
+ 5.628000000000e-10  5.697754142960e-01 
+ 5.728000000000e-10  1.994033695962e-01 
+ 5.828000000000e-10 -1.667424669503e-01 
+ 5.928000000000e-10 -4.143216611718e-01 
+ 6.028000000000e-10 -5.421291067647e-01 
+ 6.128000000000e-10 -6.188909595847e-01 
+ 6.228000000000e-10 -7.194310352535e-01 
+ 6.328000000000e-10 -8.117467342350e-01 
+ 6.428000000000e-10 -8.508333273630e-01 
+ 6.528000000000e-10 -7.942577903765e-01 
+ 6.628000000000e-10 -5.697836419865e-01 
+ 6.728000000000e-10 -1.993929431350e-01 
+ 6.828000000000e-10  1.667361734044e-01 
+ 6.928000000000e-10  4.143307053824e-01 
+ 7.028000000000e-10  5.421226813799e-01 
+ 7.128000000000e-10  6.189001833416e-01 
+ 7.228000000000e-10  7.194227358993e-01 
+ 7.328000000000e-10  8.117542266055e-01 
+ 7.428000000000e-10  8.508251070290e-01 
+ 7.528000000000e-10  7.942649966766e-01 
+ 7.628000000000e-10  5.697756363247e-01 
+ 7.728000000000e-10  1.993989977467e-01 
+ 7.828000000000e-10 -1.667434615441e-01 
+ 7.928000000000e-10 -4.143248161746e-01 
+ 8.028000000000e-10 -5.421295610790e-01 
+ 8.128000000000e-10 -6.188945163710e-01 
+ 8.228000000000e-10 -7.194289229798e-01 
+ 8.328000000000e-10 -8.117483413843e-01 
+ 8.428000000000e-10 -8.508308647988e-01 
+ 8.528000000000e-10 -7.942590780393e-01 
+ 8.628000000000e-10 -5.697822347435e-01 
+ 8.728000000000e-10 -1.993917000580e-01 
+ 8.828000000000e-10  1.667380255271e-01 
+ 8.928000000000e-10  4.143314131245e-01 
+ 9.028000000000e-10  5.421241182927e-01 
+ 9.128000000000e-10  6.189011822630e-01 
+ 9.228000000000e-10  7.194226089303e-01 
+ 9.328000000000e-10  8.117540798381e-01 
+ 9.428000000000e-10  8.508247577722e-01 
+ 9.528000000000e-10  7.942646412254e-01 
+ 9.628000000000e-10  5.697760282588e-01 
+ 9.728000000000e-10  1.993969946892e-01 
+ 9.828000000000e-10 -1.667434796269e-01 
+ 9.928000000000e-10 -4.143264352220e-01 
+ 1.000000000000e-09 -5.150731751424e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/conditions.yaml
new file mode 100644
index 00000000..76ef5491
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 18
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_18
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb.sch
new file mode 100644
index 00000000..258c6946
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb_19.data
new file mode 100644
index 00000000..cfa0d051
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_core_tb_19.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.707988120441e-01 
+ 1.728000000000e-10  2.050562196689e-01 
+ 1.828000000000e-10 -1.568083182045e-01 
+ 1.928000000000e-10 -4.020696229917e-01 
+ 2.028000000000e-10 -5.270997867267e-01 
+ 2.128000000000e-10 -6.030122328411e-01 
+ 2.228000000000e-10 -7.060404303518e-01 
+ 2.328000000000e-10 -7.977729548420e-01 
+ 2.428000000000e-10 -8.357087979117e-01 
+ 2.528000000000e-10 -7.823438332914e-01 
+ 2.628000000000e-10 -5.641015035384e-01 
+ 2.728000000000e-10 -1.996979729386e-01 
+ 2.828000000000e-10  1.605395493177e-01 
+ 2.928000000000e-10  4.049019788065e-01 
+ 3.028000000000e-10  5.293349858313e-01 
+ 3.128000000000e-10  6.047755538782e-01 
+ 3.228000000000e-10  7.072083327509e-01 
+ 3.328000000000e-10  7.985177439850e-01 
+ 3.428000000000e-10  8.360745897587e-01 
+ 3.528000000000e-10  7.825643018760e-01 
+ 3.628000000000e-10  5.642043953033e-01 
+ 3.728000000000e-10  1.998026918934e-01 
+ 3.828000000000e-10 -1.604858693758e-01 
+ 3.928000000000e-10 -4.048299316522e-01 
+ 4.028000000000e-10 -5.293048172022e-01 
+ 4.128000000000e-10 -6.047267733392e-01 
+ 4.228000000000e-10 -7.071932602489e-01 
+ 4.328000000000e-10 -7.984844304353e-01 
+ 4.428000000000e-10 -8.360789616419e-01 
+ 4.528000000000e-10 -7.825446968704e-01 
+ 4.628000000000e-10 -5.642205462461e-01 
+ 4.728000000000e-10 -1.997755595675e-01 
+ 4.828000000000e-10  1.604765943145e-01 
+ 4.928000000000e-10  4.048512691297e-01 
+ 5.028000000000e-10  5.292953655278e-01 
+ 5.128000000000e-10  6.047472585148e-01 
+ 5.228000000000e-10  7.071773753770e-01 
+ 5.328000000000e-10  7.985008103891e-01 
+ 5.428000000000e-10  8.360621173440e-01 
+ 5.528000000000e-10  7.825604957102e-01 
+ 5.628000000000e-10  5.642042607216e-01 
+ 5.728000000000e-10  1.997857962408e-01 
+ 5.828000000000e-10 -1.604926267251e-01 
+ 5.928000000000e-10 -4.048407079574e-01 
+ 6.028000000000e-10 -5.293103597207e-01 
+ 6.128000000000e-10 -6.047374718328e-01 
+ 6.228000000000e-10 -7.071895246392e-01 
+ 6.328000000000e-10 -7.984887922220e-01 
+ 6.428000000000e-10 -8.360735876941e-01 
+ 6.528000000000e-10 -7.825482507809e-01 
+ 6.628000000000e-10 -5.642183473935e-01 
+ 6.728000000000e-10 -1.997692084041e-01 
+ 6.828000000000e-10  1.604823178167e-01 
+ 6.928000000000e-10  4.048548923992e-01 
+ 7.028000000000e-10  5.293001528657e-01 
+ 7.128000000000e-10  6.047514904939e-01 
+ 7.228000000000e-10  7.071767775245e-01 
+ 7.328000000000e-10  7.985010886851e-01 
+ 7.428000000000e-10  8.360609061049e-01 
+ 7.528000000000e-10  7.825602391468e-01 
+ 7.628000000000e-10  5.642057995328e-01 
+ 7.728000000000e-10  1.997793833692e-01 
+ 7.828000000000e-10 -1.604939026989e-01 
+ 7.928000000000e-10 -4.048452814924e-01 
+ 8.028000000000e-10 -5.293110935611e-01 
+ 8.128000000000e-10 -6.047422910037e-01 
+ 8.228000000000e-10 -7.071868576548e-01 
+ 8.328000000000e-10 -7.984914661054e-01 
+ 8.428000000000e-10 -8.360704549701e-01 
+ 8.528000000000e-10 -7.825505283213e-01 
+ 8.628000000000e-10 -5.642168951425e-01 
+ 8.728000000000e-10 -1.997675829904e-01 
+ 8.828000000000e-10  1.604850893678e-01 
+ 8.928000000000e-10  4.048557791622e-01 
+ 9.028000000000e-10  5.293024006551e-01 
+ 9.128000000000e-10  6.047526676189e-01 
+ 9.228000000000e-10  7.071769813422e-01 
+ 9.328000000000e-10  7.985009240492e-01 
+ 9.428000000000e-10  8.360608174754e-01 
+ 9.528000000000e-10  7.825597625659e-01 
+ 9.628000000000e-10  5.642070937767e-01 
+ 9.728000000000e-10  1.997763618165e-01 
+ 9.828000000000e-10 -1.604938267743e-01 
+ 9.928000000000e-10 -4.048476936234e-01 
+ 1.000000000000e-09 -5.033604123532e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/conditions.yaml
new file mode 100644
index 00000000..2b63c838
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 19
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_19
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb.sch
new file mode 100644
index 00000000..91296918
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb_20.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb_20.data
new file mode 100644
index 00000000..696f2b8b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_core_tb_20.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.787258342535e-01 
+ 1.728000000000e-10  2.078017915173e-01 
+ 1.828000000000e-10 -1.622649468476e-01 
+ 1.928000000000e-10 -4.154784848215e-01 
+ 2.028000000000e-10 -5.503628241592e-01 
+ 2.128000000000e-10 -6.299323770996e-01 
+ 2.228000000000e-10 -7.254942323191e-01 
+ 2.328000000000e-10 -8.176578932007e-01 
+ 2.428000000000e-10 -8.600222409410e-01 
+ 2.528000000000e-10 -8.019093712422e-01 
+ 2.628000000000e-10 -5.756893793886e-01 
+ 2.728000000000e-10 -2.057606209176e-01 
+ 2.828000000000e-10  1.639197157563e-01 
+ 2.928000000000e-10  4.168841038800e-01 
+ 3.028000000000e-10  5.515424627408e-01 
+ 3.128000000000e-10  6.308336221978e-01 
+ 3.228000000000e-10  7.261208861559e-01 
+ 3.328000000000e-10  8.180354096547e-01 
+ 3.428000000000e-10  8.601969327831e-01 
+ 3.528000000000e-10  8.019450515145e-01 
+ 3.628000000000e-10  5.756806762770e-01 
+ 3.728000000000e-10  2.057351595047e-01 
+ 3.828000000000e-10 -1.639234125928e-01 
+ 3.928000000000e-10 -4.168916689126e-01 
+ 4.028000000000e-10 -5.515399403849e-01 
+ 4.128000000000e-10 -6.308421950132e-01 
+ 4.228000000000e-10 -7.261151591955e-01 
+ 4.328000000000e-10 -8.180409257235e-01 
+ 4.428000000000e-10 -8.601903753395e-01 
+ 4.528000000000e-10 -8.019506024478e-01 
+ 4.628000000000e-10 -5.756757498169e-01 
+ 4.728000000000e-10 -2.057370812605e-01 
+ 4.828000000000e-10  1.639284669376e-01 
+ 4.928000000000e-10  4.168895758092e-01 
+ 5.028000000000e-10  5.515444733402e-01 
+ 5.128000000000e-10  6.308408648378e-01 
+ 5.228000000000e-10  7.261175778597e-01 
+ 5.328000000000e-10  8.180376908128e-01 
+ 5.428000000000e-10  8.601923700088e-01 
+ 5.528000000000e-10  8.019470527506e-01 
+ 5.628000000000e-10  5.756789455974e-01 
+ 5.728000000000e-10  2.057316537746e-01 
+ 5.828000000000e-10 -1.639258645561e-01 
+ 5.928000000000e-10 -4.168940343704e-01 
+ 6.028000000000e-10 -5.515416140289e-01 
+ 6.128000000000e-10 -6.308456056710e-01 
+ 6.228000000000e-10 -7.261132930683e-01 
+ 6.328000000000e-10 -8.180415890619e-01 
+ 6.428000000000e-10 -8.601877913845e-01 
+ 6.528000000000e-10 -8.019507055326e-01 
+ 6.628000000000e-10 -5.756748223597e-01 
+ 6.728000000000e-10 -2.057339330851e-01 
+ 6.828000000000e-10  1.639294327626e-01 
+ 6.928000000000e-10  4.168918933453e-01 
+ 7.028000000000e-10  5.515448110547e-01 
+ 7.128000000000e-10  6.308438013344e-01 
+ 7.228000000000e-10  7.261156471026e-01 
+ 7.328000000000e-10  8.180389426729e-01 
+ 7.428000000000e-10  8.601899882644e-01 
+ 7.528000000000e-10  8.019478991926e-01 
+ 7.628000000000e-10  5.756775488816e-01 
+ 7.728000000000e-10  2.057303912125e-01 
+ 7.828000000000e-10 -1.639270777727e-01 
+ 7.928000000000e-10 -4.168949361223e-01 
+ 8.028000000000e-10 -5.515423789761e-01 
+ 8.128000000000e-10 -6.308469511551e-01 
+ 8.228000000000e-10 -7.261125857103e-01 
+ 8.328000000000e-10 -8.180418172660e-01 
+ 8.428000000000e-10 -8.601868536640e-01 
+ 8.528000000000e-10 -8.019506539776e-01 
+ 8.628000000000e-10 -5.756745040863e-01 
+ 8.728000000000e-10 -2.057325997968e-01 
+ 8.828000000000e-10  1.639296206310e-01 
+ 8.928000000000e-10  4.168929982528e-01 
+ 9.028000000000e-10  5.515447184418e-01 
+ 9.128000000000e-10  6.308451859194e-01 
+ 9.228000000000e-10  7.261146020976e-01 
+ 9.328000000000e-10  8.180396416883e-01 
+ 9.428000000000e-10  8.601888436252e-01 
+ 9.528000000000e-10  8.019484098509e-01 
+ 9.628000000000e-10  5.756767177581e-01 
+ 9.728000000000e-10  2.057300830001e-01 
+ 9.828000000000e-10 -1.639276725752e-01 
+ 9.928000000000e-10 -4.168951851932e-01 
+ 1.000000000000e-09 -5.223291820834e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/conditions.yaml
new file mode 100644
index 00000000..3c308a42
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 20
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_20
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb.sch
new file mode 100644
index 00000000..50f70f20
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb_21.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb_21.data
new file mode 100644
index 00000000..b199692b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_core_tb_21.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.573501255338e-01 
+ 1.728000000000e-10  2.075317226020e-01 
+ 1.828000000000e-10 -1.459750710281e-01 
+ 1.928000000000e-10 -3.981214724862e-01 
+ 2.028000000000e-10 -5.378144391949e-01 
+ 2.128000000000e-10 -6.222071778117e-01 
+ 2.228000000000e-10 -7.144656924256e-01 
+ 2.328000000000e-10 -7.957588475985e-01 
+ 2.428000000000e-10 -8.259944634024e-01 
+ 2.528000000000e-10 -7.639419051023e-01 
+ 2.628000000000e-10 -5.499582313836e-01 
+ 2.728000000000e-10 -2.015822705639e-01 
+ 2.828000000000e-10  1.503547149045e-01 
+ 2.928000000000e-10  4.016725871885e-01 
+ 3.028000000000e-10  5.406529598204e-01 
+ 3.128000000000e-10  6.244429748136e-01 
+ 3.228000000000e-10  7.159703736038e-01 
+ 3.328000000000e-10  7.967442303644e-01 
+ 3.428000000000e-10  8.264465978318e-01 
+ 3.528000000000e-10  7.642028659706e-01 
+ 3.628000000000e-10  5.500598536778e-01 
+ 3.728000000000e-10  2.017167809837e-01 
+ 3.828000000000e-10 -1.502994036069e-01 
+ 3.928000000000e-10 -4.015772846450e-01 
+ 4.028000000000e-10 -5.406194194587e-01 
+ 4.128000000000e-10 -6.243734224937e-01 
+ 4.228000000000e-10 -7.159615996115e-01 
+ 4.328000000000e-10 -7.966982014285e-01 
+ 4.428000000000e-10 -8.264613960108e-01 
+ 4.528000000000e-10 -7.641725666632e-01 
+ 4.628000000000e-10 -5.500862997678e-01 
+ 4.728000000000e-10 -2.016863380222e-01 
+ 4.828000000000e-10  1.502773228882e-01 
+ 4.928000000000e-10  4.016041852700e-01 
+ 5.028000000000e-10  5.405973091915e-01 
+ 5.128000000000e-10  6.243995261147e-01 
+ 5.228000000000e-10  7.159367954986e-01 
+ 5.328000000000e-10  7.967237369409e-01 
+ 5.428000000000e-10  8.264362767952e-01 
+ 5.528000000000e-10  7.641972989051e-01 
+ 5.628000000000e-10  5.500612169320e-01 
+ 5.728000000000e-10  2.017098008556e-01 
+ 5.828000000000e-10 -1.502994747055e-01 
+ 5.928000000000e-10 -4.015836624598e-01 
+ 6.028000000000e-10 -5.406181129288e-01 
+ 6.128000000000e-10 -6.243799299897e-01 
+ 6.228000000000e-10 -7.159574419629e-01 
+ 6.328000000000e-10 -7.967036557443e-01 
+ 6.428000000000e-10 -8.264562124237e-01 
+ 6.528000000000e-10 -7.641768324224e-01 
+ 6.628000000000e-10 -5.500832409355e-01 
+ 6.728000000000e-10 -2.016878835950e-01 
+ 6.828000000000e-10  1.502805147690e-01 
+ 6.928000000000e-10  4.016033959904e-01 
+ 7.028000000000e-10  5.405993862387e-01 
+ 7.128000000000e-10  6.243994053085e-01 
+ 7.228000000000e-10  7.159375001908e-01 
+ 7.328000000000e-10  7.967227911979e-01 
+ 7.428000000000e-10  8.264369695557e-01 
+ 7.528000000000e-10  7.641957504677e-01 
+ 7.628000000000e-10  5.500638388088e-01 
+ 7.728000000000e-10  2.017065810231e-01 
+ 7.828000000000e-10 -1.502977706940e-01 
+ 7.928000000000e-10 -4.015868518817e-01 
+ 8.028000000000e-10 -5.406159021220e-01 
+ 8.128000000000e-10 -6.243834226598e-01 
+ 8.228000000000e-10 -7.159542700032e-01 
+ 8.328000000000e-10 -7.967069113699e-01 
+ 8.428000000000e-10 -8.264528986398e-01 
+ 8.528000000000e-10 -7.641796598358e-01 
+ 8.628000000000e-10 -5.500810114131e-01 
+ 8.728000000000e-10 -2.016895461018e-01 
+ 8.828000000000e-10  1.502827695530e-01 
+ 8.928000000000e-10  4.016022282365e-01 
+ 9.028000000000e-10  5.406011687872e-01 
+ 9.128000000000e-10  6.243986267121e-01 
+ 9.228000000000e-10  7.159387803359e-01 
+ 9.328000000000e-10  7.967217157361e-01 
+ 9.428000000000e-10  8.264380732409e-01 
+ 9.528000000000e-10  7.641943142595e-01 
+ 9.628000000000e-10  5.500658668163e-01 
+ 9.728000000000e-10  2.017043552905e-01 
+ 9.828000000000e-10 -1.502962363926e-01 
+ 9.928000000000e-10 -4.015890294030e-01 
+ 1.000000000000e-09 -5.098048460363e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/conditions.yaml
new file mode 100644
index 00000000..9179713d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 21
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_21
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb.sch
new file mode 100644
index 00000000..85575ba5
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb_22.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb_22.data
new file mode 100644
index 00000000..60989baa
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_core_tb_22.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.539342660958e-01 
+ 1.728000000000e-10  2.092356958505e-01 
+ 1.828000000000e-10 -1.399589402437e-01 
+ 1.928000000000e-10 -3.887664135754e-01 
+ 2.028000000000e-10 -5.242925922458e-01 
+ 2.128000000000e-10 -6.069418933180e-01 
+ 2.228000000000e-10 -7.009344183633e-01 
+ 2.328000000000e-10 -7.819154973681e-01 
+ 2.428000000000e-10 -8.115011787752e-01 
+ 2.528000000000e-10 -7.528782125237e-01 
+ 2.628000000000e-10 -5.449881732974e-01 
+ 2.728000000000e-10 -2.018085669996e-01 
+ 2.828000000000e-10  1.453371294429e-01 
+ 2.928000000000e-10  3.930046196046e-01 
+ 3.028000000000e-10  5.275952350978e-01 
+ 3.128000000000e-10  6.094983923496e-01 
+ 3.228000000000e-10  7.026430994561e-01 
+ 3.328000000000e-10  7.830459101342e-01 
+ 3.428000000000e-10  8.120643124066e-01 
+ 3.528000000000e-10  7.532542388222e-01 
+ 3.628000000000e-10  5.451889146656e-01 
+ 3.728000000000e-10  2.020380161925e-01 
+ 3.828000000000e-10 -1.452202245966e-01 
+ 3.928000000000e-10 -3.928550396378e-01 
+ 4.028000000000e-10 -5.275272038156e-01 
+ 4.128000000000e-10 -6.093963788491e-01 
+ 4.228000000000e-10 -7.026185076638e-01 
+ 4.328000000000e-10 -7.829822343256e-01 
+ 4.428000000000e-10 -8.120760322925e-01 
+ 4.528000000000e-10 -7.532137307257e-01 
+ 4.628000000000e-10 -5.452168897181e-01 
+ 4.728000000000e-10 -2.019975663161e-01 
+ 4.828000000000e-10  1.451970774770e-01 
+ 4.928000000000e-10  3.928886426712e-01 
+ 5.028000000000e-10  5.275035947470e-01 
+ 5.128000000000e-10  6.094279224341e-01 
+ 5.228000000000e-10  7.025906785817e-01 
+ 5.328000000000e-10  7.830125874729e-01 
+ 5.428000000000e-10  8.120474298427e-01 
+ 5.528000000000e-10  7.532431353399e-01 
+ 5.628000000000e-10  5.451877569897e-01 
+ 5.728000000000e-10  2.020249691554e-01 
+ 5.828000000000e-10 -1.452230860448e-01 
+ 5.928000000000e-10 -3.928644448798e-01 
+ 6.028000000000e-10 -5.275279936983e-01 
+ 6.128000000000e-10 -6.094050782075e-01 
+ 6.228000000000e-10 -7.026148963104e-01 
+ 6.328000000000e-10 -7.829886841749e-01 
+ 6.428000000000e-10 -8.120708569069e-01 
+ 6.528000000000e-10 -7.532187757848e-01 
+ 6.628000000000e-10 -5.452139572157e-01 
+ 6.728000000000e-10 -2.019983459359e-01 
+ 6.828000000000e-10  1.452010057661e-01 
+ 6.928000000000e-10  3.928879698340e-01 
+ 7.028000000000e-10  5.275064479083e-01 
+ 7.128000000000e-10  6.094280990005e-01 
+ 7.228000000000e-10  7.025917879356e-01 
+ 7.328000000000e-10  7.830113821989e-01 
+ 7.428000000000e-10  8.120485256383e-01 
+ 7.528000000000e-10  7.532412367972e-01 
+ 7.628000000000e-10  5.451912171970e-01 
+ 7.728000000000e-10  2.020204953427e-01 
+ 7.828000000000e-10 -1.452213117732e-01 
+ 7.928000000000e-10 -3.928683087954e-01 
+ 8.028000000000e-10 -5.275257546899e-01 
+ 8.128000000000e-10 -6.094092443434e-01 
+ 8.228000000000e-10 -7.026114152643e-01 
+ 8.328000000000e-10 -7.829924127838e-01 
+ 8.428000000000e-10 -8.120671951794e-01 
+ 8.528000000000e-10 -7.532220607865e-01 
+ 8.628000000000e-10 -5.452116115033e-01 
+ 8.728000000000e-10 -2.019999026099e-01 
+ 8.828000000000e-10  1.452037268076e-01 
+ 8.928000000000e-10  3.928866787286e-01 
+ 9.028000000000e-10  5.275085793908e-01 
+ 9.128000000000e-10  6.094272189130e-01 
+ 9.228000000000e-10  7.025932924679e-01 
+ 9.328000000000e-10  7.830100596429e-01 
+ 9.428000000000e-10  8.120498613680e-01 
+ 9.528000000000e-10  7.532395420815e-01 
+ 9.628000000000e-10  5.451937902395e-01 
+ 9.728000000000e-10  2.020175827840e-01 
+ 9.828000000000e-10 -1.452196157349e-01 
+ 9.928000000000e-10 -3.928709378362e-01 
+ 1.000000000000e-09 -4.979849828547e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/conditions.yaml
new file mode 100644
index 00000000..244dbf1b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 22
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_22
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb.sch
new file mode 100644
index 00000000..36e2ceec
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb_23.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb_23.data
new file mode 100644
index 00000000..208aa09a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_core_tb_23.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.609932954578e-01 
+ 1.728000000000e-10  2.135803595156e-01 
+ 1.828000000000e-10 -1.406795105233e-01 
+ 1.928000000000e-10 -3.985242549940e-01 
+ 2.028000000000e-10 -5.467902250198e-01 
+ 2.128000000000e-10 -6.349197102047e-01 
+ 2.228000000000e-10 -7.225601155251e-01 
+ 2.328000000000e-10 -8.022847270862e-01 
+ 2.428000000000e-10 -8.341174139963e-01 
+ 2.528000000000e-10 -7.703472968512e-01 
+ 2.628000000000e-10 -5.554753546701e-01 
+ 2.728000000000e-10 -2.092959847468e-01 
+ 2.828000000000e-10  1.439827087572e-01 
+ 2.928000000000e-10  4.013409764958e-01 
+ 3.028000000000e-10  5.491103575815e-01 
+ 3.128000000000e-10  6.367736171292e-01 
+ 3.228000000000e-10  7.238327114492e-01 
+ 3.328000000000e-10  8.031250424519e-01 
+ 3.428000000000e-10  8.344898451807e-01 
+ 3.528000000000e-10  7.705288945959e-01 
+ 3.628000000000e-10  5.555161552443e-01 
+ 3.728000000000e-10  2.093659332353e-01 
+ 3.828000000000e-10 -1.439645708780e-01 
+ 3.928000000000e-10 -4.012864243472e-01 
+ 4.028000000000e-10 -5.490981432908e-01 
+ 4.128000000000e-10 -6.367310776976e-01 
+ 4.228000000000e-10 -7.238327358891e-01 
+ 4.328000000000e-10 -8.030945225544e-01 
+ 4.428000000000e-10 -8.345032641498e-01 
+ 4.528000000000e-10 -7.705076814073e-01 
+ 4.628000000000e-10 -5.555368200040e-01 
+ 4.728000000000e-10 -2.093450233604e-01 
+ 4.828000000000e-10  1.439466188317e-01 
+ 4.928000000000e-10  4.013057839415e-01 
+ 5.028000000000e-10  5.490801810840e-01 
+ 5.128000000000e-10  6.367502973173e-01 
+ 5.228000000000e-10  7.238134370273e-01 
+ 5.328000000000e-10  8.031142213064e-01 
+ 5.428000000000e-10  8.344836920712e-01 
+ 5.528000000000e-10  7.705267055682e-01 
+ 5.628000000000e-10  5.555176728822e-01 
+ 5.728000000000e-10  2.093634169255e-01 
+ 5.828000000000e-10 -1.439633135713e-01 
+ 5.928000000000e-10 -4.012903718012e-01 
+ 6.028000000000e-10 -5.490957661747e-01 
+ 6.128000000000e-10 -6.367354259501e-01 
+ 6.228000000000e-10 -7.238289911799e-01 
+ 6.328000000000e-10 -8.030991093312e-01 
+ 6.428000000000e-10 -8.344987261970e-01 
+ 6.528000000000e-10 -7.705113506628e-01 
+ 6.628000000000e-10 -5.555339922038e-01 
+ 6.728000000000e-10 -2.093472747699e-01 
+ 6.828000000000e-10  1.439488143392e-01 
+ 6.928000000000e-10  4.013051006454e-01 
+ 7.028000000000e-10  5.490813620131e-01 
+ 7.128000000000e-10  6.367501696447e-01 
+ 7.228000000000e-10  7.238138408460e-01 
+ 7.328000000000e-10  8.031138234310e-01 
+ 7.428000000000e-10  8.344840024625e-01 
+ 7.528000000000e-10  7.705257750612e-01 
+ 7.628000000000e-10  5.555193682491e-01 
+ 7.728000000000e-10  2.093616154732e-01 
+ 7.828000000000e-10 -1.439618235384e-01 
+ 7.928000000000e-10 -4.012927107128e-01 
+ 8.028000000000e-10 -5.490937463184e-01 
+ 8.128000000000e-10 -6.367380404539e-01 
+ 8.228000000000e-10 -7.238264478501e-01 
+ 8.328000000000e-10 -8.031018435980e-01 
+ 8.428000000000e-10 -8.344959687989e-01 
+ 8.528000000000e-10 -7.705137100306e-01 
+ 8.628000000000e-10 -5.555321098787e-01 
+ 8.728000000000e-10 -2.093489927492e-01 
+ 8.828000000000e-10  1.439504269532e-01 
+ 8.928000000000e-10  4.013041525432e-01 
+ 9.028000000000e-10  5.490824887692e-01 
+ 9.128000000000e-10  6.367494882502e-01 
+ 9.228000000000e-10  7.238146944607e-01 
+ 9.328000000000e-10  8.031131051507e-01 
+ 9.428000000000e-10  8.344847147049e-01 
+ 9.528000000000e-10  7.705248067970e-01 
+ 9.628000000000e-10  5.555207970002e-01 
+ 9.728000000000e-10  2.093601819839e-01 
+ 9.828000000000e-10 -1.439605753448e-01 
+ 9.928000000000e-10 -4.012943342775e-01 
+ 1.000000000000e-09 -5.158218772706e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/conditions.yaml
new file mode 100644
index 00000000..b870c1dc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 23
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_23
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb.sch
new file mode 100644
index 00000000..155b63de
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb_24.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb_24.data
new file mode 100644
index 00000000..a8519464
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_core_tb_24.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.405028365217e-01 
+ 1.728000000000e-10  2.142897527484e-01 
+ 1.828000000000e-10 -1.231353412434e-01 
+ 1.928000000000e-10 -3.782847553257e-01 
+ 2.028000000000e-10 -5.290944707244e-01 
+ 2.128000000000e-10 -6.207435846591e-01 
+ 2.228000000000e-10 -7.069850917784e-01 
+ 2.328000000000e-10 -7.774395392863e-01 
+ 2.428000000000e-10 -7.982183108700e-01 
+ 2.528000000000e-10 -7.327456021571e-01 
+ 2.628000000000e-10 -5.310063164445e-01 
+ 2.728000000000e-10 -2.063297175293e-01 
+ 2.828000000000e-10  1.293176468137e-01 
+ 2.928000000000e-10  3.835270490977e-01 
+ 3.028000000000e-10  5.333180257023e-01 
+ 3.128000000000e-10  6.240938619865e-01 
+ 3.228000000000e-10  7.092802493907e-01 
+ 3.328000000000e-10  7.789607942300e-01 
+ 3.428000000000e-10  7.989234313230e-01 
+ 3.528000000000e-10  7.331763415294e-01 
+ 3.628000000000e-10  5.312045040772e-01 
+ 3.728000000000e-10  2.065847902134e-01 
+ 3.828000000000e-10 -1.291958906021e-01 
+ 3.928000000000e-10 -3.833411283085e-01 
+ 4.028000000000e-10 -5.332389173297e-01 
+ 4.128000000000e-10 -6.239588708494e-01 
+ 4.228000000000e-10 -7.092541595355e-01 
+ 4.328000000000e-10 -7.788766619073e-01 
+ 4.428000000000e-10 -7.989439817890e-01 
+ 4.528000000000e-10 -7.331237184970e-01 
+ 4.628000000000e-10 -5.312431858800e-01 
+ 4.728000000000e-10 -2.065354720445e-01 
+ 4.828000000000e-10  1.291604530900e-01 
+ 4.928000000000e-10  3.833851407049e-01 
+ 5.028000000000e-10  5.332033925163e-01 
+ 5.128000000000e-10  6.240009303805e-01 
+ 5.228000000000e-10  7.092156296740e-01 
+ 5.328000000000e-10  7.789178950697e-01 
+ 5.428000000000e-10  7.989050835748e-01 
+ 5.528000000000e-10  7.331635644704e-01 
+ 5.628000000000e-10  5.312038508238e-01 
+ 5.728000000000e-10  2.065745538625e-01 
+ 5.828000000000e-10 -1.291960705945e-01 
+ 5.928000000000e-10 -3.833509278886e-01 
+ 6.028000000000e-10 -5.332368573592e-01 
+ 6.128000000000e-10 -6.239679712691e-01 
+ 6.228000000000e-10 -7.092497084655e-01 
+ 6.328000000000e-10 -7.788845366535e-01 
+ 6.428000000000e-10 -7.989377629672e-01 
+ 6.528000000000e-10 -7.331298791234e-01 
+ 6.628000000000e-10 -5.312385744549e-01 
+ 6.728000000000e-10 -2.065399094583e-01 
+ 6.828000000000e-10  1.291646812354e-01 
+ 6.928000000000e-10  3.833822988637e-01 
+ 7.028000000000e-10  5.332062833028e-01 
+ 7.128000000000e-10  6.239988652624e-01 
+ 7.228000000000e-10  7.092181343784e-01 
+ 7.328000000000e-10  7.789155267181e-01 
+ 7.428000000000e-10  7.989074545455e-01 
+ 7.528000000000e-10  7.331605295450e-01 
+ 7.628000000000e-10  5.312080087648e-01 
+ 7.728000000000e-10  2.065705039315e-01 
+ 7.828000000000e-10 -1.291926212165e-01 
+ 7.928000000000e-10 -3.833551733065e-01 
+ 8.028000000000e-10 -5.332328436976e-01 
+ 8.128000000000e-10 -6.239725200032e-01 
+ 8.228000000000e-10 -7.092452956008e-01 
+ 8.328000000000e-10 -7.788891439389e-01 
+ 8.428000000000e-10 -7.989331916474e-01 
+ 8.528000000000e-10 -7.331340451631e-01 
+ 8.628000000000e-10 -5.312350772815e-01 
+ 8.728000000000e-10 -2.065433053799e-01 
+ 8.828000000000e-10  1.291679984852e-01 
+ 8.928000000000e-10  3.833797175156e-01 
+ 9.028000000000e-10  5.332088978421e-01 
+ 9.128000000000e-10  6.239966795455e-01 
+ 9.228000000000e-10  7.092206518532e-01 
+ 9.328000000000e-10  7.789132522577e-01 
+ 9.428000000000e-10  7.989096829455e-01 
+ 9.528000000000e-10  7.331579091452e-01 
+ 9.628000000000e-10  5.312112407565e-01 
+ 9.728000000000e-10  2.065672983353e-01 
+ 9.828000000000e-10 -1.291898675297e-01 
+ 9.928000000000e-10 -3.833583124064e-01 
+ 1.000000000000e-09 -4.991705375338e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/conditions.yaml
new file mode 100644
index 00000000..d924e2a1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 24
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_24
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb.sch
new file mode 100644
index 00000000..84a6a627
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb_25.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb_25.data
new file mode 100644
index 00000000..39c04d30
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_core_tb_25.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.368449571564e-01 
+ 1.728000000000e-10  2.154696494615e-01 
+ 1.828000000000e-10 -1.180750667507e-01 
+ 1.928000000000e-10 -3.694801437498e-01 
+ 2.028000000000e-10 -5.157339685643e-01 
+ 2.128000000000e-10 -6.051803608378e-01 
+ 2.228000000000e-10 -6.923688047900e-01 
+ 2.328000000000e-10 -7.627278516708e-01 
+ 2.428000000000e-10 -7.836324050269e-01 
+ 2.528000000000e-10 -7.217390774868e-01 
+ 2.628000000000e-10 -5.258344598842e-01 
+ 2.728000000000e-10 -2.060622799160e-01 
+ 2.828000000000e-10  1.253068918672e-01 
+ 2.928000000000e-10  3.754763463876e-01 
+ 3.028000000000e-10  5.204513706872e-01 
+ 3.128000000000e-10  6.088547126517e-01 
+ 3.228000000000e-10  6.948747427610e-01 
+ 3.328000000000e-10  7.643967320598e-01 
+ 3.428000000000e-10  7.844541546789e-01 
+ 3.528000000000e-10  7.222905371020e-01 
+ 3.628000000000e-10  5.261436989659e-01 
+ 3.728000000000e-10  2.064244494061e-01 
+ 3.828000000000e-10 -1.251087630482e-01 
+ 3.928000000000e-10 -3.752230316774e-01 
+ 4.028000000000e-10 -5.203274407129e-01 
+ 4.128000000000e-10 -6.086807930540e-01 
+ 4.228000000000e-10 -6.948278459755e-01 
+ 4.328000000000e-10 -7.642927444658e-01 
+ 4.428000000000e-10 -7.844689558048e-01 
+ 4.528000000000e-10 -7.222270537973e-01 
+ 4.628000000000e-10 -5.261810188038e-01 
+ 4.728000000000e-10 -2.063649367923e-01 
+ 4.828000000000e-10  1.250740150254e-01 
+ 4.928000000000e-10  3.752740624702e-01 
+ 5.028000000000e-10  5.202917067072e-01 
+ 5.128000000000e-10  6.087280474834e-01 
+ 5.228000000000e-10  6.947875493975e-01 
+ 5.328000000000e-10  7.643381446772e-01 
+ 5.428000000000e-10  7.844278436925e-01 
+ 5.528000000000e-10  7.222707134126e-01 
+ 5.628000000000e-10  5.261386731045e-01 
+ 5.728000000000e-10  2.064078101390e-01 
+ 5.828000000000e-10 -1.251125509614e-01 
+ 5.928000000000e-10 -3.752362786491e-01 
+ 6.028000000000e-10 -5.203279553884e-01 
+ 6.128000000000e-10 -6.086920089480e-01 
+ 6.228000000000e-10 -6.948246280643e-01 
+ 6.328000000000e-10 -7.643013046090e-01 
+ 6.428000000000e-10 -7.844633201903e-01 
+ 6.528000000000e-10 -7.222336042293e-01 
+ 6.628000000000e-10 -5.261766512068e-01 
+ 6.728000000000e-10 -2.063691829929e-01 
+ 6.828000000000e-10  1.250784814444e-01 
+ 6.928000000000e-10  3.752708432251e-01 
+ 7.028000000000e-10  5.202949527958e-01 
+ 7.128000000000e-10  6.087256874770e-01 
+ 7.228000000000e-10  6.947904319095e-01 
+ 7.328000000000e-10  7.643352365607e-01 
+ 7.428000000000e-10  7.844306677783e-01 
+ 7.528000000000e-10  7.222672114429e-01 
+ 7.628000000000e-10  5.261433781551e-01 
+ 7.728000000000e-10  2.064029029490e-01 
+ 7.828000000000e-10 -1.251089390610e-01 
+ 7.928000000000e-10 -3.752408867518e-01 
+ 8.028000000000e-10 -5.203238706374e-01 
+ 8.128000000000e-10 -6.086968714396e-01 
+ 8.228000000000e-10 -6.948200705245e-01 
+ 8.328000000000e-10 -7.643060605343e-01 
+ 8.428000000000e-10 -7.844586734539e-01 
+ 8.528000000000e-10 -7.222379683755e-01 
+ 8.628000000000e-10 -5.261730442965e-01 
+ 8.728000000000e-10 -2.063725681788e-01 
+ 8.828000000000e-10  1.250820910423e-01 
+ 8.928000000000e-10  3.752680406761e-01 
+ 9.028000000000e-10  5.202978581562e-01 
+ 9.128000000000e-10  6.087233210610e-01 
+ 9.228000000000e-10  6.947932359489e-01 
+ 9.328000000000e-10  7.643326365950e-01 
+ 9.428000000000e-10  7.844331791786e-01 
+ 9.528000000000e-10  7.222642751837e-01 
+ 9.628000000000e-10  5.261469613157e-01 
+ 9.728000000000e-10  2.063991803079e-01 
+ 9.828000000000e-10 -1.251060220915e-01 
+ 9.928000000000e-10 -3.752443155305e-01 
+ 1.000000000000e-09 -4.875704709340e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/conditions.yaml
new file mode 100644
index 00000000..e7fd67d6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 25
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_25
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb.sch
new file mode 100644
index 00000000..89053b1d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb_26.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb_26.data
new file mode 100644
index 00000000..894f4c67
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_core_tb_26.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.436948212736e-01 
+ 1.728000000000e-10  2.205877879634e-01 
+ 1.828000000000e-10 -1.163348151974e-01 
+ 1.928000000000e-10 -3.771420921807e-01 
+ 2.028000000000e-10 -5.370108455130e-01 
+ 2.128000000000e-10 -6.331888427572e-01 
+ 2.228000000000e-10 -7.164762236683e-01 
+ 2.328000000000e-10 -7.851286946760e-01 
+ 2.428000000000e-10 -8.059531868761e-01 
+ 2.528000000000e-10 -7.384564800459e-01 
+ 2.628000000000e-10 -5.363144999221e-01 
+ 2.728000000000e-10 -2.144637665285e-01 
+ 2.828000000000e-10  1.212929793685e-01 
+ 2.928000000000e-10  3.815418180812e-01 
+ 3.028000000000e-10  5.406606883043e-01 
+ 3.128000000000e-10  6.361475176918e-01 
+ 3.228000000000e-10  7.185360719894e-01 
+ 3.328000000000e-10  7.865091736067e-01 
+ 3.428000000000e-10  8.065713749450e-01 
+ 3.528000000000e-10  7.387921596039e-01 
+ 3.628000000000e-10  5.364259512539e-01 
+ 3.728000000000e-10  2.146317863835e-01 
+ 3.828000000000e-10 -1.212295238309e-01 
+ 3.928000000000e-10 -3.814110096077e-01 
+ 4.028000000000e-10 -5.406166203788e-01 
+ 4.128000000000e-10 -6.360467438854e-01 
+ 4.228000000000e-10 -7.185257686739e-01 
+ 4.328000000000e-10 -7.864422304189e-01 
+ 4.428000000000e-10 -8.065937411296e-01 
+ 4.528000000000e-10 -7.387487319623e-01 
+ 4.628000000000e-10 -5.364619855530e-01 
+ 4.728000000000e-10 -2.145913861363e-01 
+ 4.828000000000e-10  1.211959412322e-01 
+ 4.928000000000e-10  3.814481551476e-01 
+ 5.028000000000e-10  5.405833390120e-01 
+ 5.128000000000e-10  6.360831449777e-01 
+ 5.228000000000e-10  7.184907253890e-01 
+ 5.328000000000e-10  7.864786648334e-01 
+ 5.428000000000e-10  8.065585198321e-01 
+ 5.528000000000e-10  7.387840006966e-01 
+ 5.628000000000e-10  5.364270346085e-01 
+ 5.728000000000e-10  2.146260338484e-01 
+ 5.828000000000e-10 -1.212277001077e-01 
+ 5.928000000000e-10 -3.814182410321e-01 
+ 6.028000000000e-10 -5.406130595607e-01 
+ 6.128000000000e-10 -6.360540210765e-01 
+ 6.228000000000e-10 -7.185209180994e-01 
+ 6.328000000000e-10 -7.864492678158e-01 
+ 6.428000000000e-10 -8.065874846616e-01 
+ 6.528000000000e-10 -7.387544794760e-01 
+ 6.628000000000e-10 -5.364572547805e-01 
+ 6.728000000000e-10 -2.145959871001e-01 
+ 6.828000000000e-10  1.211997934696e-01 
+ 6.928000000000e-10  3.814456726213e-01 
+ 7.028000000000e-10  5.405857946323e-01 
+ 7.128000000000e-10  6.360813265814e-01 
+ 7.228000000000e-10  7.184929266665e-01 
+ 7.328000000000e-10  7.864767243186e-01 
+ 7.428000000000e-10  8.065604357181e-01 
+ 7.528000000000e-10  7.387815158779e-01 
+ 7.628000000000e-10  5.364303644926e-01 
+ 7.728000000000e-10  2.146228844142e-01 
+ 7.828000000000e-10 -1.212245339809e-01 
+ 7.928000000000e-10 -3.814220075435e-01 
+ 8.028000000000e-10 -5.406092538148e-01 
+ 8.128000000000e-10 -6.360581238583e-01 
+ 8.228000000000e-10 -7.185168954112e-01 
+ 8.328000000000e-10 -7.864535273883e-01 
+ 8.428000000000e-10 -8.065831328643e-01 
+ 8.528000000000e-10 -7.387583532284e-01 
+ 8.628000000000e-10 -5.364538735708e-01 
+ 8.728000000000e-10 -2.145992968151e-01 
+ 8.828000000000e-10  1.212027591883e-01 
+ 8.928000000000e-10  3.814433789143e-01 
+ 9.028000000000e-10  5.405880431190e-01 
+ 9.128000000000e-10  6.360793794818e-01 
+ 9.228000000000e-10  7.184951630330e-01 
+ 9.328000000000e-10  7.864747526663e-01 
+ 9.428000000000e-10  8.065622905723e-01 
+ 9.528000000000e-10  7.387792872630e-01 
+ 9.628000000000e-10  5.364330391099e-01 
+ 9.728000000000e-10  2.146202349236e-01 
+ 9.828000000000e-10 -1.212220310216e-01 
+ 9.928000000000e-10 -3.814247853449e-01 
+ 1.000000000000e-09 -5.040490090913e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/conditions.yaml
new file mode 100644
index 00000000..8ef7dbf9
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 26
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/run_26
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/simulation_summary.csv
new file mode 100644
index 00000000..2f5f947b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/simulation_summary.csv
@@ -0,0 +1,28 @@
+run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing
+run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.952e-01, -6.044e-02, 0.182, …]",4.722e+09,0.709,1.418
+run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.648e-01, -3.672e-02, 0.198, …]",4.722e+09,0.693,1.386
+run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.227e-01, -8.540e-02, 0.161, …]",4.722e+09,0.722,1.444
+run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.752e-01, -5.371e-02, 0.179, …]",4.722e+09,0.692,1.383
+run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.482e-01, -3.259e-02, 0.193, …]",4.722e+09,0.672,1.345
+run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.027e-01, -8.046e-02, 0.156, …]",4.722e+09,0.706,1.412
+run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.659e-01, -5.659e-02, 0.167, …]",4.722e+09,0.669,1.338
+run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.411e-01, -3.745e-02, 0.179, …]",4.722e+09,0.648,1.295
+run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.916e-01, -8.207e-02, 0.144, …]",4.722e+09,0.685,1.371
+run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.397e-01, -2.046e-01, 0.131, …]",4.722e+09,0.807,1.614
+run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.293e-01, -2.034e-01, 0.125, …]",4.722e+09,0.789,1.577
+run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.474e-01, -2.088e-01, 0.131, …]",4.722e+09,0.819,1.638
+run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.050e-01, -1.958e-01, 0.120, …]",4.722e+09,0.771,1.543
+run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.935e-01, -1.929e-01, 0.116, …]",4.722e+09,0.753,1.505
+run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.133e-01, -2.032e-01, 0.114, …]",4.722e+09,0.783,1.566
+run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.765e-01, -1.934e-01, 0.103, …]",4.722e+09,0.743,1.486
+run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.643e-01, -1.890e-01, 0.101, …]",4.722e+09,0.725,1.450
+run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.853e-01, -2.024e-01, 9.500e-02, …]",4.722e+09,0.755,1.510
+run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.575, 0.203, -1.640e-01, …]",4.722e+09,0.851,1.702
+run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.571, 0.205, -1.568e-01, …]",4.722e+09,0.836,1.672
+run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.579, 0.208, -1.623e-01, …]",4.722e+09,0.860,1.720
+run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.557, 0.208, -1.460e-01, …]",4.722e+09,0.826,1.653
+run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.554, 0.209, -1.400e-01, …]",4.722e+09,0.812,1.624
+run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.561, 0.214, -1.407e-01, …]",4.722e+09,0.834,1.669
+run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.541, 0.214, -1.231e-01, …]",4.722e+09,0.799,1.598
+run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.537, 0.215, -1.181e-01, …]",4.722e+09,0.784,1.569
+run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.544, 0.221, -1.163e-01, …]",4.722e+09,0.807,1.613
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/simulation_summary.md
new file mode 100644
index 00000000..6401031e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/simulation_summary.md
@@ -0,0 +1,31 @@
+# Simulation Summary for CML divider frequency response
+
+| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing |
+| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: |
+| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.952e-01, -6.044e-02, 0.182, …] | 4.722e+09 | 0.709 | 1.418 |
+| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.648e-01, -3.672e-02, 0.198, …] | 4.722e+09 | 0.693 | 1.386 |
+| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.227e-01, -8.540e-02, 0.161, …] | 4.722e+09 | 0.722 | 1.444 |
+| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.752e-01, -5.371e-02, 0.179, …] | 4.722e+09 | 0.692 | 1.383 |
+| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.482e-01, -3.259e-02, 0.193, …] | 4.722e+09 | 0.672 | 1.345 |
+| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.027e-01, -8.046e-02, 0.156, …] | 4.722e+09 | 0.706 | 1.412 |
+| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.659e-01, -5.659e-02, 0.167, …] | 4.722e+09 | 0.669 | 1.338 |
+| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.411e-01, -3.745e-02, 0.179, …] | 4.722e+09 | 0.648 | 1.295 |
+| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.916e-01, -8.207e-02, 0.144, …] | 4.722e+09 | 0.685 | 1.371 |
+| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.397e-01, -2.046e-01, 0.131, …] | 4.722e+09 | 0.807 | 1.614 |
+| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.293e-01, -2.034e-01, 0.125, …] | 4.722e+09 | 0.789 | 1.577 |
+| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.474e-01, -2.088e-01, 0.131, …] | 4.722e+09 | 0.819 | 1.638 |
+| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.050e-01, -1.958e-01, 0.120, …] | 4.722e+09 | 0.771 | 1.543 |
+| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.935e-01, -1.929e-01, 0.116, …] | 4.722e+09 | 0.753 | 1.505 |
+| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.133e-01, -2.032e-01, 0.114, …] | 4.722e+09 | 0.783 | 1.566 |
+| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.765e-01, -1.934e-01, 0.103, …] | 4.722e+09 | 0.743 | 1.486 |
+| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.643e-01, -1.890e-01, 0.101, …] | 4.722e+09 | 0.725 | 1.450 |
+| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.853e-01, -2.024e-01, 9.500e-02, …] | 4.722e+09 | 0.755 | 1.510 |
+| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.575, 0.203, -1.640e-01, …] | 4.722e+09 | 0.851 | 1.702 |
+| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.571, 0.205, -1.568e-01, …] | 4.722e+09 | 0.836 | 1.672 |
+| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.579, 0.208, -1.623e-01, …] | 4.722e+09 | 0.860 | 1.720 |
+| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.557, 0.208, -1.460e-01, …] | 4.722e+09 | 0.826 | 1.653 |
+| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.554, 0.209, -1.400e-01, …] | 4.722e+09 | 0.812 | 1.624 |
+| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.561, 0.214, -1.407e-01, …] | 4.722e+09 | 0.834 | 1.669 |
+| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.541, 0.214, -1.231e-01, …] | 4.722e+09 | 0.799 | 1.598 |
+| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.537, 0.215, -1.181e-01, …] | 4.722e+09 | 0.784 | 1.569 |
+| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.544, 0.221, -1.163e-01, …] | 4.722e+09 | 0.807 | 1.613 |
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/vo_diff_vs_time.png
new file mode 100644
index 00000000..64d1b808
Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/parameters/ac_params/vo_diff_vs_time.png differ
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/summary.md
new file mode 100644
index 00000000..a11c2c65
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-34-33/summary.md
@@ -0,0 +1,11 @@
+
+# CACE Summary for CML_divider
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |  4.722 GHz |      5.0 GHz |  4.722 GHz |      5.2 GHz |  4.722 GHz |   Pass ✅    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |    0.648 V |        0.4 V |    0.771 V |        0.6 V |    0.860 V |   Fail ❌    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |    1.295 V |        0.8 V |    1.543 V |        1.2 V |    1.720 V |   Fail ❌    |
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/CML_core_tb.sch
new file mode 100644
index 00000000..48f6f0bb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb.sch
new file mode 100644
index 00000000..bdaed397
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb_0.data
new file mode 100644
index 00000000..6e5c755c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_core_tb_0.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.952325246460e-01 
+ 1.728000000000e-10 -6.043942197180e-02 
+ 1.828000000000e-10  1.817064006720e-01 
+ 1.928000000000e-10  3.985392356515e-01 
+ 2.028000000000e-10  5.562505249699e-01 
+ 2.128000000000e-10  6.572874178466e-01 
+ 2.228000000000e-10  7.087352858161e-01 
+ 2.328000000000e-10  7.029522511861e-01 
+ 2.428000000000e-10  6.344368312078e-01 
+ 2.528000000000e-10  5.013241237787e-01 
+ 2.628000000000e-10  3.030080742176e-01 
+ 2.728000000000e-10  6.578821975767e-02 
+ 2.828000000000e-10 -1.781586778972e-01 
+ 2.928000000000e-10 -3.964040373443e-01 
+ 3.028000000000e-10 -5.555461653242e-01 
+ 3.128000000000e-10 -6.571022283471e-01 
+ 3.228000000000e-10 -7.092808909864e-01 
+ 3.328000000000e-10 -7.040843150938e-01 
+ 3.428000000000e-10 -6.362469325195e-01 
+ 3.528000000000e-10 -5.032364212786e-01 
+ 3.628000000000e-10 -3.051350358226e-01 
+ 3.728000000000e-10 -6.762904380973e-02 
+ 3.828000000000e-10  1.763878132349e-01 
+ 3.928000000000e-10  3.951284969670e-01 
+ 4.028000000000e-10  5.545978983505e-01 
+ 4.128000000000e-10  6.566315830069e-01 
+ 4.228000000000e-10  7.089962487465e-01 
+ 4.328000000000e-10  7.042633111532e-01 
+ 4.428000000000e-10  6.365365170049e-01 
+ 4.528000000000e-10  5.037912579488e-01 
+ 4.628000000000e-10  3.056253251435e-01 
+ 4.728000000000e-10  6.823087043489e-02 
+ 4.828000000000e-10 -1.759620590786e-01 
+ 4.928000000000e-10 -3.946766675460e-01 
+ 5.028000000000e-10 -5.543918551335e-01 
+ 5.128000000000e-10 -6.564106038653e-01 
+ 5.228000000000e-10 -7.089804674794e-01 
+ 5.328000000000e-10 -7.042284637667e-01 
+ 5.428000000000e-10 -6.366831677063e-01 
+ 5.528000000000e-10 -5.038654128054e-01 
+ 5.628000000000e-10 -3.058301627321e-01 
+ 5.728000000000e-10 -6.832081314378e-02 
+ 5.828000000000e-10  1.757744687450e-01 
+ 5.928000000000e-10  3.946207346164e-01 
+ 6.028000000000e-10  5.542681653143e-01 
+ 6.128000000000e-10  6.564162326939e-01 
+ 6.228000000000e-10  7.089102158365e-01 
+ 6.328000000000e-10  7.042850183822e-01 
+ 6.428000000000e-10  6.366586213363e-01 
+ 6.528000000000e-10  5.039505543903e-01 
+ 6.628000000000e-10  3.058219717524e-01 
+ 6.728000000000e-10  6.840961740524e-02 
+ 6.828000000000e-10 -1.757862033444e-01 
+ 6.928000000000e-10 -3.945467987447e-01 
+ 7.028000000000e-10 -5.542929102277e-01 
+ 7.128000000000e-10 -6.563603422698e-01 
+ 7.228000000000e-10 -7.089481650220e-01 
+ 7.328000000000e-10 -7.042424683005e-01 
+ 7.428000000000e-10 -6.367078290897e-01 
+ 7.528000000000e-10 -5.039165471509e-01 
+ 7.628000000000e-10 -3.058753018579e-01 
+ 7.728000000000e-10 -6.837707225292e-02 
+ 7.828000000000e-10  1.757345833407e-01 
+ 7.928000000000e-10  3.945785215449e-01 
+ 8.028000000000e-10  5.542482652542e-01 
+ 8.128000000000e-10  6.563959408481e-01 
+ 8.228000000000e-10  7.089082113076e-01 
+ 8.328000000000e-10  7.042817797830e-01 
+ 8.428000000000e-10  6.366719399828e-01 
+ 8.528000000000e-10  5.039573608246e-01 
+ 8.628000000000e-10  3.058408732486e-01 
+ 8.728000000000e-10  6.841772818469e-02 
+ 8.828000000000e-10 -1.757686495942e-01 
+ 8.928000000000e-10 -3.945419964750e-01 
+ 9.028000000000e-10 -5.542809328797e-01 
+ 9.128000000000e-10 -6.563614885531e-01 
+ 9.228000000000e-10 -7.089411806967e-01 
+ 9.328000000000e-10 -7.042479976407e-01 
+ 9.428000000000e-10 -6.367051444468e-01 
+ 9.528000000000e-10 -5.039245834310e-01 
+ 9.628000000000e-10 -3.058742220339e-01 
+ 9.728000000000e-10 -6.838526492007e-02 
+ 9.828000000000e-10  1.757358039920e-01 
+ 9.928000000000e-10  3.945718167364e-01 
+ 1.000000000000e-09  5.155910006549e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/conditions.yaml
new file mode 100644
index 00000000..0b7f398a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 0
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_00
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb.sch
new file mode 100644
index 00000000..6d814da2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb_1.data
new file mode 100644
index 00000000..94a2849c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_core_tb_1.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.647956442563e-01 
+ 1.728000000000e-10 -3.672466403620e-02 
+ 1.828000000000e-10  1.978055322165e-01 
+ 1.928000000000e-10  4.056017943518e-01 
+ 2.028000000000e-10  5.547344088879e-01 
+ 2.128000000000e-10  6.487490848065e-01 
+ 2.228000000000e-10  6.923653634957e-01 
+ 2.328000000000e-10  6.780886353961e-01 
+ 2.428000000000e-10  6.039598047192e-01 
+ 2.528000000000e-10  4.698168410475e-01 
+ 2.628000000000e-10  2.751260896566e-01 
+ 2.728000000000e-10  4.430157580526e-02 
+ 2.828000000000e-10 -1.925038311834e-01 
+ 2.928000000000e-10 -4.023301580756e-01 
+ 3.028000000000e-10 -5.533152551340e-01 
+ 3.128000000000e-10 -6.481954476962e-01 
+ 3.228000000000e-10 -6.930655672739e-01 
+ 3.328000000000e-10 -6.800540209913e-01 
+ 3.428000000000e-10 -6.070129146880e-01 
+ 3.528000000000e-10 -4.732295235615e-01 
+ 3.628000000000e-10 -2.788311309623e-01 
+ 3.728000000000e-10 -4.769207273318e-02 
+ 3.828000000000e-10  1.893739393663e-01 
+ 3.928000000000e-10  3.999895682405e-01 
+ 4.028000000000e-10  5.516914161753e-01 
+ 4.128000000000e-10  6.473194453459e-01 
+ 4.228000000000e-10  6.926967113745e-01 
+ 4.328000000000e-10  6.804409619078e-01 
+ 4.428000000000e-10  6.077344291363e-01 
+ 4.528000000000e-10  4.743209278754e-01 
+ 4.628000000000e-10  2.799315218230e-01 
+ 4.728000000000e-10  4.887682675205e-02 
+ 4.828000000000e-10 -1.884058832182e-01 
+ 4.928000000000e-10 -3.991237321070e-01 
+ 5.028000000000e-10 -5.511979674959e-01 
+ 5.128000000000e-10 -6.469402879887e-01 
+ 5.228000000000e-10 -6.926225993557e-01 
+ 5.328000000000e-10 -6.804805060919e-01 
+ 5.428000000000e-10 -6.080204415279e-01 
+ 5.528000000000e-10 -4.745961817340e-01 
+ 5.628000000000e-10 -2.803459413605e-01 
+ 5.728000000000e-10 -4.918721233066e-02 
+ 5.828000000000e-10  1.880320213273e-01 
+ 5.928000000000e-10  3.989072784961e-01 
+ 6.028000000000e-10  5.509784832100e-01 
+ 6.128000000000e-10  6.468776696433e-01 
+ 6.228000000000e-10  6.925382949500e-01 
+ 6.328000000000e-10  6.805520167761e-01 
+ 6.428000000000e-10  6.080522625696e-01 
+ 6.528000000000e-10  4.747422384222e-01 
+ 6.628000000000e-10  2.804194075907e-01 
+ 6.728000000000e-10  4.934414267879e-02 
+ 6.828000000000e-10 -1.879699706397e-01 
+ 6.928000000000e-10 -3.987854446736e-01 
+ 7.028000000000e-10 -5.509613139230e-01 
+ 7.128000000000e-10 -6.468062697707e-01 
+ 7.228000000000e-10 -6.925630874809e-01 
+ 7.328000000000e-10 -6.805223964692e-01 
+ 7.428000000000e-10 -6.081132322697e-01 
+ 7.528000000000e-10 -4.747366406660e-01 
+ 7.628000000000e-10 -2.804933490724e-01 
+ 7.728000000000e-10 -4.934235519722e-02 
+ 7.828000000000e-10  1.879006367827e-01 
+ 7.928000000000e-10  3.987938070562e-01 
+ 8.028000000000e-10  5.509093463144e-01 
+ 8.128000000000e-10  6.468293959909e-01 
+ 8.228000000000e-10  6.925252291894e-01 
+ 8.328000000000e-10  6.805590879185e-01 
+ 8.428000000000e-10  6.080875904937e-01 
+ 8.528000000000e-10  4.747803907956e-01 
+ 8.628000000000e-10  2.804721530083e-01 
+ 8.728000000000e-10  4.938687520288e-02 
+ 8.828000000000e-10 -1.879222775604e-01 
+ 8.928000000000e-10 -3.987554695640e-01 
+ 9.028000000000e-10 -5.509333914335e-01 
+ 9.128000000000e-10 -6.467969990881e-01 
+ 9.228000000000e-10 -6.925530415231e-01 
+ 9.328000000000e-10 -6.805304150604e-01 
+ 9.428000000000e-10 -6.081187600045e-01 
+ 9.528000000000e-10 -4.747542418837e-01 
+ 9.628000000000e-10 -2.805045225794e-01 
+ 9.728000000000e-10 -4.936125388638e-02 
+ 9.828000000000e-10  1.878908530872e-01 
+ 9.928000000000e-10  3.987795364060e-01 
+ 1.000000000000e-09  5.142017254263e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/conditions.yaml
new file mode 100644
index 00000000..a6501d32
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 1
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_01
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb.sch
new file mode 100644
index 00000000..41a5530c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb_2.data
new file mode 100644
index 00000000..cdbb156b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_core_tb_2.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.226907107526e-01 
+ 1.728000000000e-10 -8.539968284410e-02 
+ 1.828000000000e-10  1.614480909662e-01 
+ 1.928000000000e-10  3.869191924745e-01 
+ 2.028000000000e-10  5.540483396157e-01 
+ 2.128000000000e-10  6.620167995175e-01 
+ 2.228000000000e-10  7.202634748901e-01 
+ 2.328000000000e-10  7.212523007105e-01 
+ 2.428000000000e-10  6.566979396260e-01 
+ 2.528000000000e-10  5.250303609426e-01 
+ 2.628000000000e-10  3.265092852166e-01 
+ 2.728000000000e-10  8.707604756770e-02 
+ 2.828000000000e-10 -1.611600424348e-01 
+ 2.928000000000e-10 -3.873238626333e-01 
+ 3.028000000000e-10 -5.550746884823e-01 
+ 3.128000000000e-10 -6.629366269634e-01 
+ 3.228000000000e-10 -7.212894794449e-01 
+ 3.328000000000e-10 -7.220878341254e-01 
+ 3.428000000000e-10 -6.576651735802e-01 
+ 3.528000000000e-10 -5.257535323793e-01 
+ 3.628000000000e-10 -3.273054874384e-01 
+ 3.728000000000e-10 -8.759901468451e-02 
+ 3.828000000000e-10  1.605580394287e-01 
+ 3.928000000000e-10  3.869863823107e-01 
+ 4.028000000000e-10  5.547303069787e-01 
+ 4.128000000000e-10  6.628461833305e-01 
+ 4.228000000000e-10  7.211466820779e-01 
+ 4.328000000000e-10  7.221995653822e-01 
+ 4.428000000000e-10  6.577128147927e-01 
+ 4.528000000000e-10  5.259884868760e-01 
+ 4.628000000000e-10  3.274163471898e-01 
+ 4.728000000000e-10  8.784541550780e-02 
+ 4.828000000000e-10 -1.604682108624e-01 
+ 4.928000000000e-10 -3.867888973241e-01 
+ 5.028000000000e-10 -5.547066546217e-01 
+ 5.128000000000e-10 -6.627253094524e-01 
+ 5.228000000000e-10 -7.211826888209e-01 
+ 5.328000000000e-10 -7.221369141817e-01 
+ 5.428000000000e-10 -6.577994031943e-01 
+ 5.528000000000e-10 -5.259620192587e-01 
+ 5.628000000000e-10 -3.275201865204e-01 
+ 5.728000000000e-10 -8.782404636233e-02 
+ 5.828000000000e-10  1.603689538405e-01 
+ 5.928000000000e-10  3.868153343854e-01 
+ 6.028000000000e-10  5.546284247412e-01 
+ 6.128000000000e-10  6.627691182366e-01 
+ 6.228000000000e-10  7.211205707397e-01 
+ 6.328000000000e-10  7.221945096033e-01 
+ 6.428000000000e-10  6.577508134366e-01 
+ 6.528000000000e-10  5.260261908485e-01 
+ 6.628000000000e-10  3.274760111912e-01 
+ 6.728000000000e-10  8.788851273295e-02 
+ 6.828000000000e-10 -1.604138329037e-01 
+ 6.928000000000e-10 -3.867579820075e-01 
+ 7.028000000000e-10 -5.546733587088e-01 
+ 7.128000000000e-10 -6.627166397254e-01 
+ 7.228000000000e-10 -7.211676696649e-01 
+ 7.328000000000e-10 -7.221448613305e-01 
+ 7.428000000000e-10 -6.577993970261e-01 
+ 7.528000000000e-10 -5.259796511606e-01 
+ 7.628000000000e-10 -3.275252420812e-01 
+ 7.728000000000e-10 -8.784270745333e-02 
+ 7.828000000000e-10  1.603648729372e-01 
+ 7.928000000000e-10  3.868003178892e-01 
+ 8.028000000000e-10  5.546284703905e-01 
+ 8.128000000000e-10  6.627594909397e-01 
+ 8.228000000000e-10  7.211247368625e-01 
+ 8.328000000000e-10  7.221884517678e-01 
+ 8.428000000000e-10  6.577581123739e-01 
+ 8.528000000000e-10  5.260226393584e-01 
+ 8.628000000000e-10  3.274844581735e-01 
+ 8.728000000000e-10  8.788515759553e-02 
+ 8.828000000000e-10 -1.604054537172e-01 
+ 8.928000000000e-10 -3.867616376768e-01 
+ 9.028000000000e-10 -5.546662826942e-01 
+ 9.128000000000e-10 -6.627215467888e-01 
+ 9.228000000000e-10 -7.211618152183e-01 
+ 9.328000000000e-10 -7.221504122635e-01 
+ 9.428000000000e-10 -6.577943183983e-01 
+ 9.528000000000e-10 -5.259856282734e-01 
+ 9.628000000000e-10 -3.275204867996e-01 
+ 9.728000000000e-10 -8.784851998896e-02 
+ 9.828000000000e-10  1.603694682536e-01 
+ 9.928000000000e-10  3.867951846118e-01 
+ 1.000000000000e-09  5.139507493642e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/conditions.yaml
new file mode 100644
index 00000000..443b9fe6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 2
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_02
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb.sch
new file mode 100644
index 00000000..769600e2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb_3.data
new file mode 100644
index 00000000..a5b707e1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_core_tb_3.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.752371518652e-01 
+ 1.728000000000e-10 -5.371376319542e-02 
+ 1.828000000000e-10  1.789877413053e-01 
+ 1.928000000000e-10  3.904548691103e-01 
+ 2.028000000000e-10  5.481842948229e-01 
+ 2.128000000000e-10  6.473880529986e-01 
+ 2.228000000000e-10  6.910106576952e-01 
+ 2.328000000000e-10  6.747515328639e-01 
+ 2.428000000000e-10  5.993982850131e-01 
+ 2.528000000000e-10  4.678235295331e-01 
+ 2.628000000000e-10  2.811940191144e-01 
+ 2.728000000000e-10  5.749892092429e-02 
+ 2.828000000000e-10 -1.768703468756e-01 
+ 2.928000000000e-10 -3.894327299011e-01 
+ 3.028000000000e-10 -5.481462871223e-01 
+ 3.128000000000e-10 -6.476233959034e-01 
+ 3.228000000000e-10 -6.918267741740e-01 
+ 3.328000000000e-10 -6.759891610513e-01 
+ 3.428000000000e-10 -6.011477081233e-01 
+ 3.528000000000e-10 -4.695436066175e-01 
+ 3.628000000000e-10 -2.830251877311e-01 
+ 3.728000000000e-10 -5.907673776650e-02 
+ 3.828000000000e-10  1.753349861707e-01 
+ 3.928000000000e-10  3.883274219019e-01 
+ 4.028000000000e-10  5.473035177189e-01 
+ 4.128000000000e-10  6.472356324664e-01 
+ 4.228000000000e-10  6.916308158427e-01 
+ 4.328000000000e-10  6.762268077787e-01 
+ 4.428000000000e-10  6.014684070962e-01 
+ 4.528000000000e-10  4.700895666681e-01 
+ 4.628000000000e-10  2.834862741746e-01 
+ 4.728000000000e-10  5.964855757083e-02 
+ 4.828000000000e-10 -1.749274761915e-01 
+ 4.928000000000e-10 -3.878897710558e-01 
+ 5.028000000000e-10 -5.470986037433e-01 
+ 5.128000000000e-10 -6.470272164409e-01 
+ 5.228000000000e-10 -6.916322065746e-01 
+ 5.328000000000e-10 -6.762158687864e-01 
+ 5.428000000000e-10 -6.016311330158e-01 
+ 5.528000000000e-10 -4.701782346337e-01 
+ 5.628000000000e-10 -2.836941639082e-01 
+ 5.728000000000e-10 -5.974768838544e-02 
+ 5.828000000000e-10  1.747352099095e-01 
+ 5.928000000000e-10  3.878245260251e-01 
+ 6.028000000000e-10  5.469715931678e-01 
+ 6.128000000000e-10  6.470284806517e-01 
+ 6.228000000000e-10  6.915679621080e-01 
+ 6.328000000000e-10  6.762768333485e-01 
+ 6.428000000000e-10  6.016163496453e-01 
+ 6.528000000000e-10  4.702674812943e-01 
+ 6.628000000000e-10  2.836938506434e-01 
+ 6.728000000000e-10  5.983990401354e-02 
+ 6.828000000000e-10 -1.747391664584e-01 
+ 6.928000000000e-10 -3.877472828580e-01 
+ 7.028000000000e-10 -5.469903889528e-01 
+ 7.128000000000e-10 -6.469730360721e-01 
+ 7.228000000000e-10 -6.916047287716e-01 
+ 7.328000000000e-10 -6.762386026180e-01 
+ 7.428000000000e-10 -6.016669907082e-01 
+ 7.528000000000e-10 -4.702390118128e-01 
+ 7.628000000000e-10 -2.837481181728e-01 
+ 7.728000000000e-10 -5.981248689037e-02 
+ 7.828000000000e-10  1.746867337354e-01 
+ 7.928000000000e-10  3.877749638679e-01 
+ 8.028000000000e-10  5.469462314077e-01 
+ 8.128000000000e-10  6.470055622974e-01 
+ 8.228000000000e-10  6.915665740520e-01 
+ 8.328000000000e-10  6.762766371031e-01 
+ 8.428000000000e-10  6.016337946720e-01 
+ 8.528000000000e-10  4.702787360349e-01 
+ 8.628000000000e-10  2.837166478210e-01 
+ 8.728000000000e-10  5.985233152723e-02 
+ 8.828000000000e-10 -1.747180248353e-01 
+ 8.928000000000e-10 -3.877389392165e-01 
+ 9.028000000000e-10 -5.469764940938e-01 
+ 9.128000000000e-10 -6.469724949526e-01 
+ 9.228000000000e-10 -6.915980610397e-01 
+ 9.328000000000e-10 -6.762447762615e-01 
+ 9.428000000000e-10 -6.016660865709e-01 
+ 9.528000000000e-10 -4.702484057793e-01 
+ 9.628000000000e-10 -2.837489236123e-01 
+ 9.728000000000e-10 -5.982216431619e-02 
+ 9.828000000000e-10  1.746862818107e-01 
+ 9.928000000000e-10  3.877670239311e-01 
+ 1.000000000000e-09  5.084292112944e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/conditions.yaml
new file mode 100644
index 00000000..b8a61493
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 3
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_03
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb.sch
new file mode 100644
index 00000000..1da7bc04
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb_4.data
new file mode 100644
index 00000000..8dbaf881
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_core_tb_4.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.482257947455e-01 
+ 1.728000000000e-10 -3.259266550035e-02 
+ 1.828000000000e-10  1.930322087844e-01 
+ 1.928000000000e-10  3.960886599474e-01 
+ 2.028000000000e-10  5.450058997505e-01 
+ 2.128000000000e-10  6.360387116800e-01 
+ 2.228000000000e-10  6.712975422190e-01 
+ 2.328000000000e-10  6.474938983982e-01 
+ 2.428000000000e-10  5.679706274704e-01 
+ 2.528000000000e-10  4.364781736218e-01 
+ 2.628000000000e-10  2.536409133725e-01 
+ 2.728000000000e-10  3.555786929817e-02 
+ 2.828000000000e-10 -1.919150168478e-01 
+ 2.928000000000e-10 -3.960490843585e-01 
+ 3.028000000000e-10 -5.456465197220e-01 
+ 3.128000000000e-10 -6.367232933250e-01 
+ 3.228000000000e-10 -6.725166925877e-01 
+ 3.328000000000e-10 -6.491812984547e-01 
+ 3.428000000000e-10 -5.701612342484e-01 
+ 3.528000000000e-10 -4.386195239579e-01 
+ 3.628000000000e-10 -2.558666299298e-01 
+ 3.728000000000e-10 -3.750940439386e-02 
+ 3.828000000000e-10  1.900731677010e-01 
+ 3.928000000000e-10  3.947279065049e-01 
+ 4.028000000000e-10  5.446879536498e-01 
+ 4.128000000000e-10  6.362937598492e-01 
+ 4.228000000000e-10  6.723764816130e-01 
+ 4.328000000000e-10  6.495551727740e-01 
+ 4.428000000000e-10  5.706690754638e-01 
+ 4.528000000000e-10  4.393690386281e-01 
+ 4.628000000000e-10  2.565445890136e-01 
+ 4.728000000000e-10  3.828939038748e-02 
+ 4.828000000000e-10 -1.894747026650e-01 
+ 4.928000000000e-10 -3.941469427019e-01 
+ 5.028000000000e-10 -5.443881652157e-01 
+ 5.128000000000e-10 -6.360424686566e-01 
+ 5.228000000000e-10 -6.723795425302e-01 
+ 5.328000000000e-10 -6.495951074105e-01 
+ 5.428000000000e-10 -5.709049111673e-01 
+ 5.528000000000e-10 -4.395480856777e-01 
+ 5.628000000000e-10 -2.568451405700e-01 
+ 5.728000000000e-10 -3.848386295174e-02 
+ 5.828000000000e-10  1.891998017504e-01 
+ 5.928000000000e-10  3.940128253458e-01 
+ 6.028000000000e-10  5.442195759360e-01 
+ 6.128000000000e-10  6.360190076123e-01 
+ 6.228000000000e-10  6.723154692419e-01 
+ 6.328000000000e-10  6.496722035130e-01 
+ 6.428000000000e-10  5.709215560836e-01 
+ 6.528000000000e-10  4.396716365902e-01 
+ 6.628000000000e-10  2.568848555761e-01 
+ 6.728000000000e-10  3.861258812938e-02 
+ 6.828000000000e-10 -1.891673406027e-01 
+ 6.928000000000e-10 -3.939096487469e-01 
+ 7.028000000000e-10 -5.442185154541e-01 
+ 7.128000000000e-10 -6.359555029215e-01 
+ 7.228000000000e-10 -6.723494769467e-01 
+ 7.328000000000e-10 -6.496420384079e-01 
+ 7.428000000000e-10 -5.709822816025e-01 
+ 7.528000000000e-10 -4.396582995671e-01 
+ 7.628000000000e-10 -2.569529185106e-01 
+ 7.728000000000e-10 -3.860128053097e-02 
+ 7.828000000000e-10  1.891028165048e-01 
+ 7.928000000000e-10  3.939252197739e-01 
+ 8.028000000000e-10  5.441685861906e-01 
+ 8.128000000000e-10  6.359828023137e-01 
+ 8.228000000000e-10  6.723118712615e-01 
+ 8.328000000000e-10  6.496812709937e-01 
+ 8.428000000000e-10  5.709544657577e-01 
+ 8.528000000000e-10  4.397022527784e-01 
+ 8.628000000000e-10  2.569280980597e-01 
+ 8.728000000000e-10  3.864565597286e-02 
+ 8.828000000000e-10 -1.891278298806e-01 
+ 8.928000000000e-10 -3.938862165142e-01 
+ 9.028000000000e-10 -5.441949734698e-01 
+ 9.128000000000e-10 -6.359493781265e-01 
+ 9.228000000000e-10 -6.723420888760e-01 
+ 9.328000000000e-10 -6.496512561522e-01 
+ 9.428000000000e-10 -5.709874488604e-01 
+ 9.528000000000e-10 -4.396746422576e-01 
+ 9.628000000000e-10 -2.569616958772e-01 
+ 9.728000000000e-10 -3.861839939192e-02 
+ 9.828000000000e-10  1.890951489097e-01 
+ 9.928000000000e-10  3.939119089870e-01 
+ 1.000000000000e-09  5.081084039478e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/conditions.yaml
new file mode 100644
index 00000000..0fc6562b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 4
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_04
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb.sch
new file mode 100644
index 00000000..2c044836
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb_5.data
new file mode 100644
index 00000000..72d71163
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_core_tb_5.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.026592886865e-01 
+ 1.728000000000e-10 -8.046058591213e-02 
+ 1.828000000000e-10  1.560684489845e-01 
+ 1.928000000000e-10  3.758215815324e-01 
+ 2.028000000000e-10  5.441825187720e-01 
+ 2.128000000000e-10  6.527787402061e-01 
+ 2.228000000000e-10  7.054162779080e-01 
+ 2.328000000000e-10  6.966940307878e-01 
+ 2.428000000000e-10  6.251719997267e-01 
+ 2.528000000000e-10  4.948986245243e-01 
+ 2.628000000000e-10  3.088338841037e-01 
+ 2.728000000000e-10  8.463582249819e-02 
+ 2.828000000000e-10 -1.534379373390e-01 
+ 2.928000000000e-10 -3.742382678981e-01 
+ 3.028000000000e-10 -5.437587344983e-01 
+ 3.128000000000e-10 -6.527795869025e-01 
+ 3.228000000000e-10 -7.060578401775e-01 
+ 3.328000000000e-10 -6.977288800308e-01 
+ 3.428000000000e-10 -6.267241220561e-01 
+ 3.528000000000e-10 -4.964034573067e-01 
+ 3.628000000000e-10 -3.104523257846e-01 
+ 3.728000000000e-10 -8.599843693100e-02 
+ 3.828000000000e-10  1.520614001089e-01 
+ 3.928000000000e-10  3.732327292359e-01 
+ 4.028000000000e-10  5.429530946109e-01 
+ 4.128000000000e-10  6.523997728799e-01 
+ 4.228000000000e-10  7.058202145507e-01 
+ 4.328000000000e-10  6.979022558405e-01 
+ 4.428000000000e-10  6.269588593419e-01 
+ 4.528000000000e-10  4.968624227466e-01 
+ 4.628000000000e-10  3.108132149603e-01 
+ 4.728000000000e-10  8.648038785746e-02 
+ 4.828000000000e-10 -1.517384677919e-01 
+ 4.928000000000e-10 -3.728474794484e-01 
+ 5.028000000000e-10 -5.427866011842e-01 
+ 5.128000000000e-10 -6.522022614009e-01 
+ 5.228000000000e-10 -7.058208822479e-01 
+ 5.328000000000e-10 -6.978651082200e-01 
+ 5.428000000000e-10 -6.270935668997e-01 
+ 5.528000000000e-10 -4.969096569281e-01 
+ 5.628000000000e-10 -3.109835748750e-01 
+ 5.728000000000e-10 -8.653572716924e-02 
+ 5.828000000000e-10  1.515778681972e-01 
+ 5.928000000000e-10  3.728127447205e-01 
+ 6.028000000000e-10  5.426739415091e-01 
+ 6.128000000000e-10  6.522162007318e-01 
+ 6.228000000000e-10  7.057544179932e-01 
+ 6.328000000000e-10  6.979224304337e-01 
+ 6.428000000000e-10  6.270641898671e-01 
+ 6.528000000000e-10  4.969874144680e-01 
+ 6.628000000000e-10  3.109648292365e-01 
+ 6.728000000000e-10  8.661535651254e-02 
+ 6.828000000000e-10 -1.515990397030e-01 
+ 6.928000000000e-10 -3.727433125293e-01 
+ 7.028000000000e-10 -5.427028559119e-01 
+ 7.128000000000e-10 -6.521615488134e-01 
+ 7.228000000000e-10 -7.057946841560e-01 
+ 7.328000000000e-10 -6.978790263426e-01 
+ 7.428000000000e-10 -6.271133848792e-01 
+ 7.528000000000e-10 -4.969513861012e-01 
+ 7.628000000000e-10 -3.110159233563e-01 
+ 7.728000000000e-10 -8.658006676818e-02 
+ 7.828000000000e-10  1.515487071721e-01 
+ 7.928000000000e-10  3.727772980737e-01 
+ 8.028000000000e-10  5.426589701450e-01 
+ 8.128000000000e-10  6.521979789832e-01 
+ 8.228000000000e-10  7.057547305503e-01 
+ 8.328000000000e-10  6.979187185021e-01 
+ 8.428000000000e-10  6.270767072939e-01 
+ 8.528000000000e-10  4.969913946096e-01 
+ 8.628000000000e-10  3.109805885282e-01 
+ 8.728000000000e-10  8.662004567696e-02 
+ 8.828000000000e-10 -1.515841004471e-01 
+ 8.928000000000e-10 -3.727405314049e-01 
+ 9.028000000000e-10 -5.426922302859e-01 
+ 9.128000000000e-10 -6.521632231968e-01 
+ 9.228000000000e-10 -7.057882763540e-01 
+ 9.328000000000e-10 -6.978845659833e-01 
+ 9.428000000000e-10 -6.271103709374e-01 
+ 9.528000000000e-10 -4.969587868574e-01 
+ 9.628000000000e-10 -3.110138943909e-01 
+ 9.728000000000e-10 -8.658760475646e-02 
+ 9.828000000000e-10  1.515508999036e-01 
+ 9.928000000000e-10  3.727707590510e-01 
+ 1.000000000000e-09  5.012730784879e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/conditions.yaml
new file mode 100644
index 00000000..0ad1edf7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 5
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_05
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb.sch
new file mode 100644
index 00000000..6264c557
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb_6.data
new file mode 100644
index 00000000..2ac25b32
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_core_tb_6.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.658991355482e-01 
+ 1.728000000000e-10 -5.658971746101e-02 
+ 1.828000000000e-10  1.665652322471e-01 
+ 1.928000000000e-10  3.726189743475e-01 
+ 2.028000000000e-10  5.303705116758e-01 
+ 2.128000000000e-10  6.287796796090e-01 
+ 2.228000000000e-10  6.685380236864e-01 
+ 2.328000000000e-10  6.490234756137e-01 
+ 2.428000000000e-10  5.737092070140e-01 
+ 2.528000000000e-10  4.474825535463e-01 
+ 2.628000000000e-10  2.725242795062e-01 
+ 2.728000000000e-10  6.117177433707e-02 
+ 2.828000000000e-10 -1.637031734923e-01 
+ 2.928000000000e-10 -3.708935568747e-01 
+ 3.028000000000e-10 -5.297756369707e-01 
+ 3.128000000000e-10 -6.287017384995e-01 
+ 3.228000000000e-10 -6.693265533929e-01 
+ 3.328000000000e-10 -6.504570398323e-01 
+ 3.428000000000e-10 -5.758168078022e-01 
+ 3.528000000000e-10 -4.496242973413e-01 
+ 3.628000000000e-10 -2.747981275605e-01 
+ 3.728000000000e-10 -6.319393908833e-02 
+ 3.828000000000e-10  1.617439470913e-01 
+ 3.928000000000e-10  3.694169588634e-01 
+ 4.028000000000e-10  5.286499307585e-01 
+ 4.128000000000e-10  6.281722098808e-01 
+ 4.228000000000e-10  6.691184385543e-01 
+ 4.328000000000e-10  6.507901751637e-01 
+ 4.428000000000e-10  5.762974118946e-01 
+ 4.528000000000e-10  4.503608294114e-01 
+ 4.628000000000e-10  2.754522690623e-01 
+ 4.728000000000e-10  6.396306731359e-02 
+ 4.828000000000e-10 -1.611542650007e-01 
+ 4.928000000000e-10 -3.688169747432e-01 
+ 5.028000000000e-10 -5.283292872594e-01 
+ 5.128000000000e-10 -6.279003852563e-01 
+ 5.228000000000e-10 -6.691136918962e-01 
+ 5.328000000000e-10 -6.508124831570e-01 
+ 5.428000000000e-10 -5.765249280825e-01 
+ 5.528000000000e-10 -4.505225248069e-01 
+ 5.628000000000e-10 -2.757393848954e-01 
+ 5.728000000000e-10 -6.413835118523e-02 
+ 5.828000000000e-10  1.608879015274e-01 
+ 5.928000000000e-10  3.686909867212e-01 
+ 6.028000000000e-10  5.281558224884e-01 
+ 6.128000000000e-10  6.278785795680e-01 
+ 6.228000000000e-10  6.690442760911e-01 
+ 6.328000000000e-10  6.508870303825e-01 
+ 6.428000000000e-10  5.765321271449e-01 
+ 6.528000000000e-10  4.506407637839e-01 
+ 6.628000000000e-10  2.757670228304e-01 
+ 6.728000000000e-10  6.426080532693e-02 
+ 6.828000000000e-10 -1.608659404084e-01 
+ 6.928000000000e-10 -3.685888330346e-01 
+ 7.028000000000e-10 -5.281591419234e-01 
+ 7.128000000000e-10 -6.278127091451e-01 
+ 7.228000000000e-10 -6.690805910819e-01 
+ 7.328000000000e-10 -6.508520944992e-01 
+ 7.428000000000e-10 -5.765925476372e-01 
+ 7.528000000000e-10 -4.506215704207e-01 
+ 7.628000000000e-10 -2.758332595929e-01 
+ 7.728000000000e-10 -6.424327491403e-02 
+ 7.828000000000e-10  1.608024320318e-01 
+ 7.928000000000e-10  3.686091606456e-01 
+ 8.028000000000e-10  5.281080947303e-01 
+ 8.128000000000e-10  6.278426474070e-01 
+ 8.228000000000e-10  6.690409470235e-01 
+ 8.328000000000e-10  6.508923982303e-01 
+ 8.428000000000e-10  5.765614162070e-01 
+ 8.528000000000e-10  4.506656063053e-01 
+ 8.628000000000e-10  2.758047260180e-01 
+ 8.728000000000e-10  6.428762429922e-02 
+ 8.828000000000e-10 -1.608310872580e-01 
+ 8.928000000000e-10 -3.685690211775e-01 
+ 9.028000000000e-10 -5.281370864240e-01 
+ 9.128000000000e-10 -6.278075066251e-01 
+ 9.228000000000e-10 -6.690730291835e-01 
+ 9.328000000000e-10 -6.508603444096e-01 
+ 9.428000000000e-10 -5.765956636587e-01 
+ 9.528000000000e-10 -4.506359555730e-01 
+ 9.628000000000e-10 -2.758391852585e-01 
+ 9.728000000000e-10 -6.425829353036e-02 
+ 9.828000000000e-10  1.607973448132e-01 
+ 9.928000000000e-10  3.685968285070e-01 
+ 1.000000000000e-09  4.894958047088e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/conditions.yaml
new file mode 100644
index 00000000..36f5013b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 6
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_06
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb.sch
new file mode 100644
index 00000000..a5abe997
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb_7.data
new file mode 100644
index 00000000..8cc8eec2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_core_tb_7.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.411371086013e-01 
+ 1.728000000000e-10 -3.745255924116e-02 
+ 1.828000000000e-10  1.789428987452e-01 
+ 1.928000000000e-10  3.769558934840e-01 
+ 2.028000000000e-10  5.255858783541e-01 
+ 2.128000000000e-10  6.150086513683e-01 
+ 2.228000000000e-10  6.463506095909e-01 
+ 2.328000000000e-10  6.202014565113e-01 
+ 2.428000000000e-10  5.417075102450e-01 
+ 2.528000000000e-10  4.161519970610e-01 
+ 2.628000000000e-10  2.448960905686e-01 
+ 2.728000000000e-10  3.892968213965e-02 
+ 2.828000000000e-10 -1.791505445505e-01 
+ 2.928000000000e-10 -3.778686664383e-01 
+ 3.028000000000e-10 -5.268093330033e-01 
+ 3.128000000000e-10 -6.159877416348e-01 
+ 3.228000000000e-10 -6.476195951568e-01 
+ 3.328000000000e-10 -6.216667221790e-01 
+ 3.428000000000e-10 -5.435382878554e-01 
+ 3.528000000000e-10 -4.178448923887e-01 
+ 3.628000000000e-10 -2.466531390426e-01 
+ 3.728000000000e-10 -4.041876256606e-02 
+ 3.828000000000e-10  1.777092594525e-01 
+ 3.928000000000e-10  3.768542192180e-01 
+ 4.028000000000e-10  5.260351926041e-01 
+ 4.128000000000e-10  6.156923491854e-01 
+ 4.228000000000e-10  6.475364165656e-01 
+ 4.328000000000e-10  6.220253224816e-01 
+ 4.428000000000e-10  5.439681165412e-01 
+ 4.528000000000e-10  4.184919515643e-01 
+ 4.628000000000e-10  2.472032785778e-01 
+ 4.728000000000e-10  4.108392377197e-02 
+ 4.828000000000e-10 -1.772209974541e-01 
+ 4.928000000000e-10 -3.763464849454e-01 
+ 5.028000000000e-10 -5.257893585276e-01 
+ 5.128000000000e-10 -6.154751208437e-01 
+ 5.228000000000e-10 -6.475677164184e-01 
+ 5.328000000000e-10 -6.220637777790e-01 
+ 5.428000000000e-10 -5.441970040997e-01 
+ 5.528000000000e-10 -4.186454653208e-01 
+ 5.628000000000e-10 -2.474812841152e-01 
+ 5.728000000000e-10 -4.124875776275e-02 
+ 5.828000000000e-10  1.769646369358e-01 
+ 5.928000000000e-10  3.762321495571e-01 
+ 6.028000000000e-10  5.256270530622e-01 
+ 6.128000000000e-10  6.154644314175e-01 
+ 6.228000000000e-10  6.475079392204e-01 
+ 6.328000000000e-10  6.221477255403e-01 
+ 6.428000000000e-10  5.442104878297e-01 
+ 6.528000000000e-10  4.187701859554e-01 
+ 6.628000000000e-10  2.475138621783e-01 
+ 6.728000000000e-10  4.137738638918e-02 
+ 6.828000000000e-10 -1.769383615791e-01 
+ 6.928000000000e-10 -3.761265802968e-01 
+ 7.028000000000e-10 -5.256298366366e-01 
+ 7.128000000000e-10 -6.153992750277e-01 
+ 7.228000000000e-10 -6.475476374408e-01 
+ 7.328000000000e-10 -6.221164421539e-01 
+ 7.428000000000e-10 -5.442762390873e-01 
+ 7.528000000000e-10 -4.187551150856e-01 
+ 7.628000000000e-10 -2.475858208222e-01 
+ 7.728000000000e-10 -4.136415856981e-02 
+ 7.828000000000e-10  1.768699557901e-01 
+ 7.928000000000e-10  3.761440347995e-01 
+ 8.028000000000e-10  5.255765528630e-01 
+ 8.128000000000e-10  6.154291154928e-01 
+ 8.228000000000e-10  6.475082015932e-01 
+ 8.328000000000e-10  6.221591874056e-01 
+ 8.428000000000e-10  5.442468649409e-01 
+ 8.528000000000e-10  4.188025713318e-01 
+ 8.628000000000e-10  2.475593730203e-01 
+ 8.728000000000e-10  4.141194467582e-02 
+ 8.828000000000e-10 -1.768965906206e-01 
+ 8.928000000000e-10 -3.761014263264e-01 
+ 9.028000000000e-10 -5.256047249426e-01 
+ 9.128000000000e-10 -6.153930400649e-01 
+ 9.228000000000e-10 -6.475410523019e-01 
+ 9.328000000000e-10 -6.221273229309e-01 
+ 9.428000000000e-10 -5.442828742825e-01 
+ 9.528000000000e-10 -4.187734552047e-01 
+ 9.628000000000e-10 -2.475958588134e-01 
+ 9.728000000000e-10 -4.138326223977e-02 
+ 9.828000000000e-10  1.768611473522e-01 
+ 9.928000000000e-10  3.761288017358e-01 
+ 1.000000000000e-09  4.898465656484e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/conditions.yaml
new file mode 100644
index 00000000..69575399
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 7
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_07
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb.sch
new file mode 100644
index 00000000..85c2bca7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb_8.data
new file mode 100644
index 00000000..2ec9911e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_core_tb_8.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.915574653990e-01 
+ 1.728000000000e-10 -8.207206468644e-02 
+ 1.828000000000e-10  1.443140454917e-01 
+ 1.928000000000e-10  3.578501059917e-01 
+ 2.028000000000e-10  5.264102614641e-01 
+ 2.128000000000e-10  6.356033847750e-01 
+ 2.228000000000e-10  6.852124516173e-01 
+ 2.328000000000e-10  6.731697751231e-01 
+ 2.428000000000e-10  6.014680860110e-01 
+ 2.528000000000e-10  4.762934940598e-01 
+ 2.628000000000e-10  3.019743151843e-01 
+ 2.728000000000e-10  9.052768843264e-02 
+ 2.828000000000e-10 -1.376882496508e-01 
+ 2.928000000000e-10 -3.528073773591e-01 
+ 3.028000000000e-10 -5.234244166185e-01 
+ 3.128000000000e-10 -6.340851318675e-01 
+ 3.228000000000e-10 -6.854084589569e-01 
+ 3.328000000000e-10 -6.747695956588e-01 
+ 3.428000000000e-10 -6.042844418494e-01 
+ 3.528000000000e-10 -4.793995649692e-01 
+ 3.628000000000e-10 -3.052822644166e-01 
+ 3.728000000000e-10 -9.358407685982e-02 
+ 3.828000000000e-10  1.347194202511e-01 
+ 3.928000000000e-10  3.504174847188e-01 
+ 4.028000000000e-10  5.215924623562e-01 
+ 4.128000000000e-10  6.330900225454e-01 
+ 4.228000000000e-10  6.849701135730e-01 
+ 4.328000000000e-10  6.751037342439e-01 
+ 4.428000000000e-10  6.049384750133e-01 
+ 4.528000000000e-10  4.803914109079e-01 
+ 4.628000000000e-10  3.062148923158e-01 
+ 4.728000000000e-10  9.463220881739e-02 
+ 4.828000000000e-10 -1.338572933423e-01 
+ 4.928000000000e-10 -3.495689260045e-01 
+ 5.028000000000e-10 -5.210792449240e-01 
+ 5.128000000000e-10 -6.326887195405e-01 
+ 5.228000000000e-10 -6.848983576670e-01 
+ 5.328000000000e-10 -6.751198274713e-01 
+ 5.428000000000e-10 -6.052060952211e-01 
+ 5.528000000000e-10 -4.806148207689e-01 
+ 5.628000000000e-10 -3.065686575138e-01 
+ 5.728000000000e-10 -9.487468231530e-02 
+ 5.828000000000e-10  1.335246601606e-01 
+ 5.928000000000e-10  3.493821792388e-01 
+ 6.028000000000e-10  5.208575371198e-01 
+ 6.128000000000e-10  6.326338805716e-01 
+ 6.228000000000e-10  6.848108600046e-01 
+ 6.328000000000e-10  6.751907109187e-01 
+ 6.428000000000e-10  6.052214841565e-01 
+ 6.528000000000e-10  4.807458450129e-01 
+ 6.628000000000e-10  3.066111422989e-01 
+ 6.728000000000e-10  9.501122064621e-02 
+ 6.828000000000e-10 -1.334882175614e-01 
+ 6.928000000000e-10 -3.492660352924e-01 
+ 7.028000000000e-10 -5.208495294585e-01 
+ 7.128000000000e-10 -6.325598499367e-01 
+ 7.228000000000e-10 -6.848421004985e-01 
+ 7.328000000000e-10 -6.751543080912e-01 
+ 7.428000000000e-10 -6.052828258645e-01 
+ 7.528000000000e-10 -4.807293659120e-01 
+ 7.628000000000e-10 -3.066794924108e-01 
+ 7.728000000000e-10 -9.499664108150e-02 
+ 7.828000000000e-10  1.334220275121e-01 
+ 7.928000000000e-10  3.492835018463e-01 
+ 8.028000000000e-10  5.207961769649e-01 
+ 8.128000000000e-10  6.325876998525e-01 
+ 8.228000000000e-10  6.848014468222e-01 
+ 8.328000000000e-10  6.751935994962e-01 
+ 8.428000000000e-10  6.052518981308e-01 
+ 8.528000000000e-10  4.807729857688e-01 
+ 8.628000000000e-10  3.066516205185e-01 
+ 8.728000000000e-10  9.504068447267e-02 
+ 8.828000000000e-10 -1.334502935734e-01 
+ 8.928000000000e-10 -3.492430994753e-01 
+ 9.028000000000e-10 -5.208246106410e-01 
+ 9.128000000000e-10 -6.325523513325e-01 
+ 9.228000000000e-10 -6.848328984481e-01 
+ 9.328000000000e-10 -6.751615848536e-01 
+ 9.428000000000e-10 -6.052856721640e-01 
+ 9.528000000000e-10 -4.807436971446e-01 
+ 9.628000000000e-10 -3.066854569150e-01 
+ 9.728000000000e-10 -9.501170247959e-02 
+ 9.828000000000e-10  1.334168358063e-01 
+ 9.928000000000e-10  3.492707284922e-01 
+ 1.000000000000e-09  4.787459694615e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/conditions.yaml
new file mode 100644
index 00000000..a0f14717
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 8
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_08
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb.sch
new file mode 100644
index 00000000..6cbfd323
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb_9.data
new file mode 100644
index 00000000..1eb23e09
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_core_tb_9.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.397443385003e-01 
+ 1.728000000000e-10 -2.045536352810e-01 
+ 1.828000000000e-10  1.313863393294e-01 
+ 1.928000000000e-10  3.838209275603e-01 
+ 2.028000000000e-10  5.347375940933e-01 
+ 2.128000000000e-10  6.276591932156e-01 
+ 2.228000000000e-10  7.115621702194e-01 
+ 2.328000000000e-10  7.798611559065e-01 
+ 2.428000000000e-10  8.066497785728e-01 
+ 2.528000000000e-10  7.447444131165e-01 
+ 2.628000000000e-10  5.331798214247e-01 
+ 2.728000000000e-10  1.991243487461e-01 
+ 2.828000000000e-10 -1.352153251063e-01 
+ 2.928000000000e-10 -3.864762984078e-01 
+ 3.028000000000e-10 -5.369168929595e-01 
+ 3.128000000000e-10 -6.290603792866e-01 
+ 3.228000000000e-10 -7.126196515736e-01 
+ 3.328000000000e-10 -7.804415576126e-01 
+ 3.428000000000e-10 -8.071911048716e-01 
+ 3.528000000000e-10 -7.450481751688e-01 
+ 3.628000000000e-10 -5.336055963763e-01 
+ 3.728000000000e-10 -1.993198332358e-01 
+ 3.828000000000e-10  1.349559401886e-01 
+ 3.928000000000e-10  3.864112742700e-01 
+ 4.028000000000e-10  5.367351878370e-01 
+ 4.128000000000e-10  6.290489992071e-01 
+ 4.228000000000e-10  7.124864782962e-01 
+ 4.328000000000e-10  7.804750739895e-01 
+ 4.428000000000e-10  8.070933947437e-01 
+ 4.528000000000e-10  7.451033689318e-01 
+ 4.628000000000e-10  5.335168975820e-01 
+ 4.728000000000e-10  1.993807368925e-01 
+ 4.828000000000e-10 -1.350304895400e-01 
+ 4.928000000000e-10 -3.863532554681e-01 
+ 5.028000000000e-10 -5.368040585560e-01 
+ 5.128000000000e-10 -6.289909078772e-01 
+ 5.228000000000e-10 -7.125533448218e-01 
+ 5.328000000000e-10 -7.804160897110e-01 
+ 5.428000000000e-10 -8.071554863663e-01 
+ 5.528000000000e-10 -7.450422465689e-01 
+ 5.628000000000e-10 -5.335838460974e-01 
+ 5.728000000000e-10 -1.993167730115e-01 
+ 5.828000000000e-10  1.349726890253e-01 
+ 5.928000000000e-10  3.864109858256e-01 
+ 6.028000000000e-10  5.367479691018e-01 
+ 6.128000000000e-10  6.290476980128e-01 
+ 6.228000000000e-10  7.124950121919e-01 
+ 6.328000000000e-10  7.804717191606e-01 
+ 6.428000000000e-10  8.070994779138e-01 
+ 6.528000000000e-10  7.450975613250e-01 
+ 6.628000000000e-10  5.335259065522e-01 
+ 6.728000000000e-10  1.993734548210e-01 
+ 6.828000000000e-10 -1.350242777574e-01 
+ 6.928000000000e-10 -3.863605033303e-01 
+ 7.028000000000e-10 -5.367975294074e-01 
+ 7.128000000000e-10 -6.289982763959e-01 
+ 7.228000000000e-10 -7.125455111440e-01 
+ 7.328000000000e-10 -7.804238043085e-01 
+ 7.428000000000e-10 -8.071473680780e-01 
+ 7.528000000000e-10 -7.450494772754e-01 
+ 7.628000000000e-10 -5.335773499054e-01 
+ 7.728000000000e-10 -1.993230348361e-01 
+ 7.828000000000e-10  1.349793746975e-01 
+ 7.928000000000e-10  3.864055722387e-01 
+ 8.028000000000e-10  5.367539279153e-01 
+ 8.128000000000e-10  6.290427569852e-01 
+ 8.228000000000e-10  7.125002063044e-01 
+ 8.328000000000e-10  7.804668926767e-01 
+ 8.428000000000e-10  8.071042297758e-01 
+ 8.528000000000e-10  7.450922570276e-01 
+ 8.628000000000e-10  5.335323457615e-01 
+ 8.728000000000e-10  1.993673584870e-01 
+ 8.828000000000e-10 -1.350193573750e-01 
+ 8.928000000000e-10 -3.863660901230e-01 
+ 9.028000000000e-10 -5.367925035482e-01 
+ 9.128000000000e-10 -6.290039875175e-01 
+ 9.228000000000e-10 -7.125398122704e-01 
+ 9.328000000000e-10 -7.804294363608e-01 
+ 9.428000000000e-10 -8.071416857778e-01 
+ 9.528000000000e-10 -7.450548065452e-01 
+ 9.628000000000e-10 -5.335722743766e-01 
+ 9.728000000000e-10 -1.993280329539e-01 
+ 9.828000000000e-10  1.349843549639e-01 
+ 9.928000000000e-10  3.864011317450e-01 
+ 1.000000000000e-09  5.028020863733e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/conditions.yaml
new file mode 100644
index 00000000..25163809
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 9
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_09
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb.sch
new file mode 100644
index 00000000..c13e9c20
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb_10.data
new file mode 100644
index 00000000..973ede5e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_core_tb_10.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.293189432094e-01 
+ 1.728000000000e-10 -2.034299929592e-01 
+ 1.828000000000e-10  1.254532736892e-01 
+ 1.928000000000e-10  3.744603520131e-01 
+ 2.028000000000e-10  5.220595086358e-01 
+ 2.128000000000e-10  6.139346231694e-01 
+ 2.228000000000e-10  6.977077768020e-01 
+ 2.328000000000e-10  7.638951530454e-01 
+ 2.428000000000e-10  7.881008470503e-01 
+ 2.528000000000e-10  7.271434956617e-01 
+ 2.628000000000e-10  5.227259392947e-01 
+ 2.728000000000e-10  1.977807095317e-01 
+ 2.828000000000e-10 -1.296557480667e-01 
+ 2.928000000000e-10 -3.774966254092e-01 
+ 3.028000000000e-10 -5.245506032311e-01 
+ 3.128000000000e-10 -6.155925798862e-01 
+ 3.228000000000e-10 -6.989490114600e-01 
+ 3.328000000000e-10 -7.646204924296e-01 
+ 3.428000000000e-10 -7.887093478172e-01 
+ 3.528000000000e-10 -7.274783648153e-01 
+ 3.628000000000e-10 -5.231513423786e-01 
+ 3.728000000000e-10 -1.979863018154e-01 
+ 3.828000000000e-10  1.294013660930e-01 
+ 3.928000000000e-10  3.774276121382e-01 
+ 4.028000000000e-10  5.243833105689e-01 
+ 4.128000000000e-10  6.155813660155e-01 
+ 4.228000000000e-10  6.988272077165e-01 
+ 4.328000000000e-10  7.646509984988e-01 
+ 4.428000000000e-10  7.886185007607e-01 
+ 4.528000000000e-10  7.275266613790e-01 
+ 4.628000000000e-10  5.230676681296e-01 
+ 4.728000000000e-10  1.980405747385e-01 
+ 4.828000000000e-10 -1.294713662253e-01 
+ 4.928000000000e-10 -3.773761496757e-01 
+ 5.028000000000e-10 -5.244469821379e-01 
+ 5.128000000000e-10 -6.155294307936e-01 
+ 5.228000000000e-10 -6.988887956355e-01 
+ 5.328000000000e-10 -7.645972449904e-01 
+ 5.428000000000e-10 -7.886754254295e-01 
+ 5.528000000000e-10 -7.274706677122e-01 
+ 5.628000000000e-10 -5.231295350854e-01 
+ 5.728000000000e-10 -1.979806299381e-01 
+ 5.828000000000e-10  1.294187696545e-01 
+ 5.928000000000e-10  3.774292707563e-01 
+ 6.028000000000e-10  5.243961595933e-01 
+ 6.128000000000e-10  6.155814701559e-01 
+ 6.228000000000e-10  6.988355515168e-01 
+ 6.328000000000e-10  7.646484599731e-01 
+ 6.428000000000e-10  7.886243100181e-01 
+ 6.528000000000e-10  7.275215569265e-01 
+ 6.628000000000e-10  5.230764840752e-01 
+ 6.728000000000e-10  1.980332799823e-01 
+ 6.828000000000e-10 -1.294660192513e-01 
+ 6.928000000000e-10 -3.773827405650e-01 
+ 7.028000000000e-10 -5.244413520748e-01 
+ 7.128000000000e-10 -6.155361997798e-01 
+ 7.228000000000e-10 -6.988817029216e-01 
+ 7.328000000000e-10 -7.646043204444e-01 
+ 7.428000000000e-10 -7.886680576572e-01 
+ 7.528000000000e-10 -7.274772120684e-01 
+ 7.628000000000e-10 -5.231238849653e-01 
+ 7.728000000000e-10 -1.979860775160e-01 
+ 7.828000000000e-10  1.294249237809e-01 
+ 7.928000000000e-10  3.774244918330e-01 
+ 8.028000000000e-10  5.244015690321e-01 
+ 8.128000000000e-10  6.155771739165e-01 
+ 8.228000000000e-10  6.988402156207e-01 
+ 8.328000000000e-10  7.646441380646e-01 
+ 8.428000000000e-10  7.886285892332e-01 
+ 8.528000000000e-10  7.275167248781e-01 
+ 8.628000000000e-10  5.230825202638e-01 
+ 8.728000000000e-10  1.980273627479e-01 
+ 8.828000000000e-10 -1.294617038455e-01 
+ 8.928000000000e-10 -3.773878907236e-01 
+ 9.028000000000e-10 -5.244369215985e-01 
+ 9.128000000000e-10 -6.155414802599e-01 
+ 9.228000000000e-10 -6.988765421320e-01 
+ 9.328000000000e-10 -7.646094975483e-01 
+ 9.428000000000e-10 -7.886629049186e-01 
+ 9.528000000000e-10 -7.274820443091e-01 
+ 9.628000000000e-10 -5.231193961018e-01 
+ 9.728000000000e-10 -1.979905037884e-01 
+ 9.828000000000e-10  1.294294922144e-01 
+ 9.928000000000e-10  3.774205018001e-01 
+ 1.000000000000e-09  4.912603506308e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/conditions.yaml
new file mode 100644
index 00000000..3d2bd3a6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 10
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_10
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb.sch
new file mode 100644
index 00000000..d1583716
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb_11.data
new file mode 100644
index 00000000..799f8459
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_core_tb_11.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.473675478550e-01 
+ 1.728000000000e-10 -2.087893101739e-01 
+ 1.828000000000e-10  1.310494751476e-01 
+ 1.928000000000e-10  3.871555645678e-01 
+ 2.028000000000e-10  5.437689230363e-01 
+ 2.128000000000e-10  6.391330299748e-01 
+ 2.228000000000e-10  7.213082317981e-01 
+ 2.328000000000e-10  7.903248370025e-01 
+ 2.428000000000e-10  8.187618792919e-01 
+ 2.528000000000e-10  7.555729663838e-01 
+ 2.628000000000e-10  5.409345054541e-01 
+ 2.728000000000e-10  2.036912835862e-01 
+ 2.828000000000e-10 -1.345140506878e-01 
+ 2.928000000000e-10 -3.895370892644e-01 
+ 3.028000000000e-10 -5.457400052530e-01 
+ 3.128000000000e-10 -6.403498057265e-01 
+ 3.228000000000e-10 -7.222286336937e-01 
+ 3.328000000000e-10 -7.907911780827e-01 
+ 3.428000000000e-10 -8.192361080664e-01 
+ 3.528000000000e-10 -7.558198978931e-01 
+ 3.628000000000e-10 -5.413206307136e-01 
+ 3.728000000000e-10 -2.038438399825e-01 
+ 3.828000000000e-10  1.342763346632e-01 
+ 3.928000000000e-10  3.894921044587e-01 
+ 4.028000000000e-10  5.455616788274e-01 
+ 4.128000000000e-10  6.403489734683e-01 
+ 4.228000000000e-10  7.220944352324e-01 
+ 4.328000000000e-10  7.908322596821e-01 
+ 4.428000000000e-10  8.191363162855e-01 
+ 4.528000000000e-10  7.558824803046e-01 
+ 4.628000000000e-10  5.412307821184e-01 
+ 4.728000000000e-10  2.039121351986e-01 
+ 4.828000000000e-10 -1.343528713892e-01 
+ 4.928000000000e-10 -3.894290190191e-01 
+ 5.028000000000e-10 -5.456335562174e-01 
+ 5.128000000000e-10 -6.402860869065e-01 
+ 5.228000000000e-10 -7.221652152444e-01 
+ 5.328000000000e-10 -7.907686614943e-01 
+ 5.428000000000e-10 -8.192023796026e-01 
+ 5.528000000000e-10 -7.558173441778e-01 
+ 5.628000000000e-10 -5.413004970284e-01 
+ 5.728000000000e-10 -2.038447386050e-01 
+ 5.828000000000e-10  1.342913524064e-01 
+ 5.928000000000e-10  3.894897157728e-01 
+ 6.028000000000e-10  5.455737058766e-01 
+ 6.128000000000e-10  6.403462778603e-01 
+ 6.228000000000e-10  7.221032530671e-01 
+ 6.328000000000e-10  7.908278354740e-01 
+ 6.428000000000e-10  8.191430293573e-01 
+ 6.528000000000e-10  7.558759446864e-01 
+ 6.628000000000e-10  5.412396296665e-01 
+ 6.728000000000e-10  2.039046702204e-01 
+ 6.828000000000e-10 -1.343459163903e-01 
+ 6.928000000000e-10 -3.894366779769e-01 
+ 7.028000000000e-10 -5.456262483653e-01 
+ 7.128000000000e-10 -6.402940065215e-01 
+ 7.228000000000e-10 -7.221570137640e-01 
+ 7.328000000000e-10 -7.907769448806e-01 
+ 7.428000000000e-10 -8.191938542033e-01 
+ 7.528000000000e-10 -7.558251320231e-01 
+ 7.628000000000e-10 -5.412933191298e-01 
+ 7.728000000000e-10 -2.038518419443e-01 
+ 7.828000000000e-10  1.342982918430e-01 
+ 7.928000000000e-10  3.894837914532e-01 
+ 8.028000000000e-10  5.455799247329e-01 
+ 8.128000000000e-10  6.403408689327e-01 
+ 8.228000000000e-10  7.221089932485e-01 
+ 8.328000000000e-10  7.908225333386e-01 
+ 8.428000000000e-10  8.191482615363e-01 
+ 8.528000000000e-10  7.558702665648e-01 
+ 8.628000000000e-10  5.412462517638e-01 
+ 8.728000000000e-10  2.038984202104e-01 
+ 8.828000000000e-10 -1.343404705774e-01 
+ 8.928000000000e-10 -3.894425333092e-01 
+ 9.028000000000e-10 -5.456206778041e-01 
+ 9.128000000000e-10 -6.403000729433e-01 
+ 9.228000000000e-10 -7.221509667404e-01 
+ 9.328000000000e-10 -7.907829740936e-01 
+ 9.428000000000e-10 -8.191877974471e-01 
+ 9.528000000000e-10 -7.558308764830e-01 
+ 9.628000000000e-10 -5.412878201925e-01 
+ 9.728000000000e-10 -2.038573569097e-01 
+ 9.828000000000e-10  1.343035264203e-01 
+ 9.928000000000e-10  3.894790170617e-01 
+ 1.000000000000e-09  5.100069898815e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/conditions.yaml
new file mode 100644
index 00000000..9911aad3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 11
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_11
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb.sch
new file mode 100644
index 00000000..39a0b30e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb_12.data
new file mode 100644
index 00000000..db4e4cce
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_core_tb_12.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.049557277618e-01 
+ 1.728000000000e-10 -1.958466480437e-01 
+ 1.828000000000e-10  1.196319367700e-01 
+ 1.928000000000e-10  3.700244189406e-01 
+ 2.028000000000e-10  5.308067637731e-01 
+ 2.128000000000e-10  6.311299202315e-01 
+ 2.228000000000e-10  7.086540860403e-01 
+ 2.328000000000e-10  7.625529356493e-01 
+ 2.428000000000e-10  7.708473475114e-01 
+ 2.528000000000e-10  6.980446990655e-01 
+ 2.628000000000e-10  4.981026307256e-01 
+ 2.728000000000e-10  1.904449044265e-01 
+ 2.828000000000e-10 -1.236510258628e-01 
+ 2.928000000000e-10 -3.730975798774e-01 
+ 3.028000000000e-10 -5.333436235403e-01 
+ 3.128000000000e-10 -6.328422885796e-01 
+ 3.228000000000e-10 -7.099622515515e-01 
+ 3.328000000000e-10 -7.633093670089e-01 
+ 3.428000000000e-10 -7.714462858000e-01 
+ 3.528000000000e-10 -6.983543456334e-01 
+ 3.628000000000e-10 -4.984830350414e-01 
+ 3.728000000000e-10 -1.906133898346e-01 
+ 3.828000000000e-10  1.234140438752e-01 
+ 3.928000000000e-10  3.730258572177e-01 
+ 4.028000000000e-10  5.331667972487e-01 
+ 4.128000000000e-10  6.328214645319e-01 
+ 4.228000000000e-10  7.098336990067e-01 
+ 4.328000000000e-10  7.633335528675e-01 
+ 4.428000000000e-10  7.713603033543e-01 
+ 4.528000000000e-10  6.984040906368e-01 
+ 4.628000000000e-10  4.984087981115e-01 
+ 4.728000000000e-10  1.906698925098e-01 
+ 4.828000000000e-10 -1.234792426423e-01 
+ 4.928000000000e-10 -3.729733539485e-01 
+ 5.028000000000e-10 -5.332277682129e-01 
+ 5.128000000000e-10 -6.327690017914e-01 
+ 5.228000000000e-10 -7.098933602520e-01 
+ 5.328000000000e-10 -7.632805035294e-01 
+ 5.428000000000e-10 -7.714147767047e-01 
+ 5.528000000000e-10 -6.983493927960e-01 
+ 5.628000000000e-10 -4.984657326360e-01 
+ 5.728000000000e-10 -1.906133403657e-01 
+ 5.828000000000e-10  1.234275058651e-01 
+ 5.928000000000e-10  3.730246636548e-01 
+ 6.028000000000e-10  5.331775888699e-01 
+ 6.128000000000e-10  6.328197652536e-01 
+ 6.228000000000e-10  7.098419058182e-01 
+ 6.328000000000e-10  7.633301342197e-01 
+ 6.428000000000e-10  7.713661487972e-01 
+ 6.528000000000e-10  6.983986251010e-01 
+ 6.628000000000e-10  4.984160910452e-01 
+ 6.728000000000e-10  1.906635868460e-01 
+ 6.828000000000e-10 -1.234734747225e-01 
+ 6.928000000000e-10 -3.729797013887e-01 
+ 7.028000000000e-10 -5.332215969565e-01 
+ 7.128000000000e-10 -6.327757131741e-01 
+ 7.228000000000e-10 -7.098865351622e-01 
+ 7.328000000000e-10 -7.632871392149e-01 
+ 7.428000000000e-10 -7.714081948986e-01 
+ 7.528000000000e-10 -6.983555969606e-01 
+ 7.628000000000e-10 -4.984601688237e-01 
+ 7.728000000000e-10 -1.906192454806e-01 
+ 7.828000000000e-10  1.234332321656e-01 
+ 7.928000000000e-10  3.730195983111e-01 
+ 8.028000000000e-10  5.331826746949e-01 
+ 8.128000000000e-10  6.328151783475e-01 
+ 8.228000000000e-10  7.098466992587e-01 
+ 8.328000000000e-10  7.633256332241e-01 
+ 8.428000000000e-10  7.713705417094e-01 
+ 8.528000000000e-10  6.983937777920e-01 
+ 8.628000000000e-10  4.984215072239e-01 
+ 8.728000000000e-10  1.906583322627e-01 
+ 8.828000000000e-10 -1.234689419945e-01 
+ 8.928000000000e-10 -3.729845695752e-01 
+ 9.028000000000e-10 -5.332169477613e-01 
+ 9.128000000000e-10 -6.327807857544e-01 
+ 9.228000000000e-10 -7.098815617208e-01 
+ 9.328000000000e-10 -7.632920474235e-01 
+ 9.428000000000e-10 -7.714033753149e-01 
+ 9.528000000000e-10 -6.983602366678e-01 
+ 9.628000000000e-10 -4.984557776243e-01 
+ 9.728000000000e-10 -1.906237729891e-01 
+ 9.828000000000e-10  1.234375916302e-01 
+ 9.928000000000e-10  3.730155682884e-01 
+ 1.000000000000e-09  4.959193237551e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/conditions.yaml
new file mode 100644
index 00000000..cddd2127
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 12
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_12
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb.sch
new file mode 100644
index 00000000..268d2560
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb_13.data
new file mode 100644
index 00000000..abbd3617
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_core_tb_13.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.935497259980e-01 
+ 1.728000000000e-10 -1.928633983658e-01 
+ 1.828000000000e-10  1.160949240371e-01 
+ 1.928000000000e-10  3.619360857197e-01 
+ 2.028000000000e-10  5.185143131218e-01 
+ 2.128000000000e-10  6.170086772416e-01 
+ 2.228000000000e-10  6.939063598865e-01 
+ 2.328000000000e-10  7.457993341265e-01 
+ 2.428000000000e-10  7.520509596304e-01 
+ 2.528000000000e-10  6.804739824857e-01 
+ 2.628000000000e-10  4.870426149481e-01 
+ 2.728000000000e-10  1.875308246798e-01 
+ 2.828000000000e-10 -1.202389208092e-01 
+ 2.928000000000e-10 -3.651754434827e-01 
+ 3.028000000000e-10 -5.211918880427e-01 
+ 3.128000000000e-10 -6.188469707889e-01 
+ 3.228000000000e-10 -6.953072467312e-01 
+ 3.328000000000e-10 -7.466129151979e-01 
+ 3.428000000000e-10 -7.526565311823e-01 
+ 3.528000000000e-10 -6.807675409917e-01 
+ 3.628000000000e-10 -4.873945801883e-01 
+ 3.728000000000e-10 -1.876809763872e-01 
+ 3.828000000000e-10  1.200199744899e-01 
+ 3.928000000000e-10  3.651151173578e-01 
+ 4.028000000000e-10  5.210322421793e-01 
+ 4.128000000000e-10  6.188330192958e-01 
+ 4.228000000000e-10  6.951893716680e-01 
+ 4.328000000000e-10  7.466394998986e-01 
+ 4.428000000000e-10  7.525773069027e-01 
+ 4.528000000000e-10  6.808165070916e-01 
+ 4.628000000000e-10  4.873248087716e-01 
+ 4.728000000000e-10  1.877358679741e-01 
+ 4.828000000000e-10 -1.200819840902e-01 
+ 4.928000000000e-10 -3.650646413699e-01 
+ 5.028000000000e-10 -5.210903047408e-01 
+ 5.128000000000e-10 -6.187830156405e-01 
+ 5.228000000000e-10 -6.952462050643e-01 
+ 5.328000000000e-10 -7.465883056072e-01 
+ 5.428000000000e-10 -7.526293067125e-01 
+ 5.528000000000e-10 -6.807638103361e-01 
+ 5.628000000000e-10 -4.873795115625e-01 
+ 5.728000000000e-10 -1.876807689254e-01 
+ 5.828000000000e-10  1.200326256254e-01 
+ 5.928000000000e-10  3.651139754788e-01 
+ 6.028000000000e-10  5.210426454606e-01 
+ 6.128000000000e-10  6.188315227579e-01 
+ 6.228000000000e-10  6.951972695911e-01 
+ 6.328000000000e-10  7.466359762403e-01 
+ 6.428000000000e-10  7.525829976005e-01 
+ 6.528000000000e-10  6.808110143898e-01 
+ 6.628000000000e-10  4.873318873720e-01 
+ 6.728000000000e-10  1.877292356433e-01 
+ 6.828000000000e-10 -1.200767202072e-01 
+ 6.928000000000e-10 -3.650706499628e-01 
+ 7.028000000000e-10 -5.210847183857e-01 
+ 7.128000000000e-10 -6.187893543189e-01 
+ 7.228000000000e-10 -6.952399017798e-01 
+ 7.328000000000e-10 -7.465944604664e-01 
+ 7.428000000000e-10 -7.526232942576e-01 
+ 7.528000000000e-10 -6.807695137827e-01 
+ 7.628000000000e-10 -4.873744121182e-01 
+ 7.728000000000e-10 -1.876860880622e-01 
+ 7.828000000000e-10  1.200380835632e-01 
+ 7.928000000000e-10  3.651091778387e-01 
+ 8.028000000000e-10  5.210475167171e-01 
+ 8.128000000000e-10  6.188272213187e-01 
+ 8.228000000000e-10  6.952018279574e-01 
+ 8.328000000000e-10  7.466316140292e-01 
+ 8.428000000000e-10  7.525872528114e-01 
+ 8.528000000000e-10  6.808063071094e-01 
+ 8.628000000000e-10  4.873371355126e-01 
+ 8.728000000000e-10  1.877239857571e-01 
+ 8.828000000000e-10 -1.200724809112e-01 
+ 8.928000000000e-10 -3.650752679165e-01 
+ 9.028000000000e-10 -5.210804068397e-01 
+ 9.128000000000e-10 -6.187941569931e-01 
+ 9.228000000000e-10 -6.952352466105e-01 
+ 9.328000000000e-10 -7.465990720366e-01 
+ 9.428000000000e-10 -7.526188226163e-01 
+ 9.528000000000e-10 -6.807738360998e-01 
+ 9.628000000000e-10 -4.873703126609e-01 
+ 9.728000000000e-10 -1.876902725775e-01 
+ 9.828000000000e-10  1.200422409457e-01 
+ 9.928000000000e-10  3.651053453859e-01 
+ 1.000000000000e-09  4.847952698035e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/conditions.yaml
new file mode 100644
index 00000000..46ff607c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 13
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_13
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb.sch
new file mode 100644
index 00000000..439b1ad4
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb_14.data
new file mode 100644
index 00000000..3796cea3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_core_tb_14.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.133282675634e-01 
+ 1.728000000000e-10 -2.031582081928e-01 
+ 1.828000000000e-10  1.144804838339e-01 
+ 1.928000000000e-10  3.698591588516e-01 
+ 2.028000000000e-10  5.380258146680e-01 
+ 2.128000000000e-10  6.422542980920e-01 
+ 2.228000000000e-10  7.191574927620e-01 
+ 2.328000000000e-10  7.734390216007e-01 
+ 2.428000000000e-10  7.823512104827e-01 
+ 2.528000000000e-10  7.081342613122e-01 
+ 2.628000000000e-10  5.065809773945e-01 
+ 2.728000000000e-10  1.980707374060e-01 
+ 2.828000000000e-10 -1.181831896095e-01 
+ 2.928000000000e-10 -3.727163876319e-01 
+ 3.028000000000e-10 -5.404428949084e-01 
+ 3.128000000000e-10 -6.438704305572e-01 
+ 3.228000000000e-10 -7.204145434420e-01 
+ 3.328000000000e-10 -7.741471374370e-01 
+ 3.428000000000e-10 -7.829309638154e-01 
+ 3.528000000000e-10 -7.084110972821e-01 
+ 3.628000000000e-10 -5.069426471107e-01 
+ 3.728000000000e-10 -1.982066720174e-01 
+ 3.828000000000e-10  1.179564926067e-01 
+ 3.928000000000e-10  3.726621714283e-01 
+ 4.028000000000e-10  5.402630628674e-01 
+ 4.128000000000e-10  6.438601752956e-01 
+ 4.228000000000e-10  7.202791375194e-01 
+ 4.328000000000e-10  7.741793827377e-01 
+ 4.428000000000e-10  7.828380754967e-01 
+ 4.528000000000e-10  7.084693803333e-01 
+ 4.628000000000e-10  5.068627667504e-01 
+ 4.728000000000e-10  1.982719515445e-01 
+ 4.828000000000e-10 -1.180275895897e-01 
+ 4.928000000000e-10 -3.726028735362e-01 
+ 5.028000000000e-10 -5.403301024789e-01 
+ 5.128000000000e-10 -6.438008084190e-01 
+ 5.228000000000e-10 -7.203455420725e-01 
+ 5.328000000000e-10 -7.741198297783e-01 
+ 5.428000000000e-10 -7.828987326701e-01 
+ 5.528000000000e-10 -7.084084859242e-01 
+ 5.628000000000e-10 -5.069251044876e-01 
+ 5.728000000000e-10 -1.982094732584e-01 
+ 5.828000000000e-10  1.179697981212e-01 
+ 5.928000000000e-10  3.726595322461e-01 
+ 6.028000000000e-10  5.402739437431e-01 
+ 6.128000000000e-10  6.438573026479e-01 
+ 6.228000000000e-10  7.202880216174e-01 
+ 6.328000000000e-10  7.741750830136e-01 
+ 6.428000000000e-10  7.828445699494e-01 
+ 6.528000000000e-10  7.084631989914e-01 
+ 6.628000000000e-10  5.068703543607e-01 
+ 6.728000000000e-10  1.982651160797e-01 
+ 6.828000000000e-10 -1.180209524418e-01 
+ 6.928000000000e-10 -3.726100259571e-01 
+ 7.028000000000e-10 -5.403229404029e-01 
+ 7.128000000000e-10 -6.438083895554e-01 
+ 7.228000000000e-10 -7.203378638829e-01 
+ 7.328000000000e-10 -7.741273273776e-01 
+ 7.428000000000e-10 -7.828912312659e-01 
+ 7.528000000000e-10 -7.084155733246e-01 
+ 7.628000000000e-10 -5.069185371484e-01 
+ 7.728000000000e-10 -1.982163796445e-01 
+ 7.828000000000e-10  1.179761824049e-01 
+ 7.928000000000e-10  3.726538824343e-01 
+ 8.028000000000e-10  5.402795684719e-01 
+ 8.128000000000e-10  6.438520994328e-01 
+ 8.228000000000e-10  7.202935093188e-01 
+ 8.328000000000e-10  7.741699689895e-01 
+ 8.428000000000e-10  7.828494756723e-01 
+ 8.528000000000e-10  7.084578188073e-01 
+ 8.628000000000e-10  5.068761410729e-01 
+ 8.728000000000e-10  1.982594122387e-01 
+ 8.828000000000e-10 -1.180157633845e-01 
+ 8.928000000000e-10 -3.726154653834e-01 
+ 9.028000000000e-10 -5.403175771302e-01 
+ 9.128000000000e-10 -6.438140825829e-01 
+ 9.228000000000e-10 -7.203322576361e-01 
+ 9.328000000000e-10 -7.741328388949e-01 
+ 9.428000000000e-10 -7.828857350121e-01 
+ 9.528000000000e-10 -7.084208512479e-01 
+ 9.628000000000e-10 -5.069134738545e-01 
+ 9.728000000000e-10 -1.982215797151e-01 
+ 9.828000000000e-10  1.179810466336e-01 
+ 9.928000000000e-10  3.726493985613e-01 
+ 1.000000000000e-09  5.010433738758e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/conditions.yaml
new file mode 100644
index 00000000..8cbc3b80
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 14
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_14
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb.sch
new file mode 100644
index 00000000..9cd78fdc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb_15.data
new file mode 100644
index 00000000..a18684b0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_core_tb_15.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.764925698370e-01 
+ 1.728000000000e-10 -1.934019301872e-01 
+ 1.828000000000e-10  1.027850457497e-01 
+ 1.928000000000e-10  3.499528968595e-01 
+ 2.028000000000e-10  5.186059326128e-01 
+ 2.128000000000e-10  6.254912177700e-01 
+ 2.228000000000e-10  6.994356057335e-01 
+ 2.328000000000e-10  7.419604616039e-01 
+ 2.428000000000e-10  7.366001230119e-01 
+ 2.528000000000e-10  6.575586826882e-01 
+ 2.628000000000e-10  4.703480039804e-01 
+ 2.728000000000e-10  1.887311437228e-01 
+ 2.828000000000e-10 -1.064955609068e-01 
+ 2.928000000000e-10 -3.530674432656e-01 
+ 3.028000000000e-10 -5.214103928852e-01 
+ 3.128000000000e-10 -6.276329249236e-01 
+ 3.228000000000e-10 -7.010919569868e-01 
+ 3.328000000000e-10 -7.428528846984e-01 
+ 3.428000000000e-10 -7.371070425945e-01 
+ 3.528000000000e-10 -6.576931102984e-01 
+ 3.628000000000e-10 -4.705213908487e-01 
+ 3.728000000000e-10 -1.887451417089e-01 
+ 3.828000000000e-10  1.063771169054e-01 
+ 3.928000000000e-10  3.530644558224e-01 
+ 4.028000000000e-10  5.212882945537e-01 
+ 4.128000000000e-10  6.276273956697e-01 
+ 4.228000000000e-10  7.009872983885e-01 
+ 4.328000000000e-10  7.428850006835e-01 
+ 4.428000000000e-10  7.370483197885e-01 
+ 4.528000000000e-10  6.577532995019e-01 
+ 4.628000000000e-10  4.704734311564e-01 
+ 4.728000000000e-10  1.888066765622e-01 
+ 4.828000000000e-10 -1.064251900033e-01 
+ 4.928000000000e-10 -3.530110058012e-01 
+ 5.028000000000e-10 -5.213363794122e-01 
+ 5.128000000000e-10 -6.275779961821e-01 
+ 5.228000000000e-10 -7.010367362436e-01 
+ 5.328000000000e-10 -7.428359180794e-01 
+ 5.428000000000e-10 -7.370946234404e-01 
+ 5.528000000000e-10 -6.577041924295e-01 
+ 5.628000000000e-10 -4.705211118057e-01 
+ 5.728000000000e-10 -1.887571402743e-01 
+ 5.828000000000e-10  1.063798390696e-01 
+ 5.928000000000e-10  3.530562876751e-01 
+ 6.028000000000e-10  5.212929538773e-01 
+ 6.128000000000e-10  6.276223718978e-01 
+ 6.228000000000e-10  7.009927681762e-01 
+ 6.328000000000e-10  7.428797293753e-01 
+ 6.428000000000e-10  7.370526578677e-01 
+ 6.528000000000e-10  6.577470674825e-01 
+ 6.628000000000e-10  4.704784998901e-01 
+ 6.728000000000e-10  1.888003575241e-01 
+ 6.828000000000e-10 -1.064204487643e-01 
+ 6.928000000000e-10 -3.530168946500e-01 
+ 7.028000000000e-10 -5.213312567329e-01 
+ 7.128000000000e-10 -6.275838929681e-01 
+ 7.228000000000e-10 -7.010312441909e-01 
+ 7.328000000000e-10 -7.428415937954e-01 
+ 7.428000000000e-10 -7.370893810626e-01 
+ 7.528000000000e-10 -6.577094889087e-01 
+ 7.628000000000e-10 -4.705162397262e-01 
+ 7.728000000000e-10 -1.887623115300e-01 
+ 7.828000000000e-10  1.063847513579e-01 
+ 7.928000000000e-10  3.530516705381e-01 
+ 8.028000000000e-10  5.212973590939e-01 
+ 8.128000000000e-10  6.276181223045e-01 
+ 8.228000000000e-10  7.009970786285e-01 
+ 8.328000000000e-10  7.428754735512e-01 
+ 8.428000000000e-10  7.370567570344e-01 
+ 8.528000000000e-10  6.577427030952e-01 
+ 8.628000000000e-10  4.704830497474e-01 
+ 8.728000000000e-10  1.887958404937e-01 
+ 8.828000000000e-10 -1.064163174914e-01 
+ 8.928000000000e-10 -3.530210908451e-01 
+ 9.028000000000e-10 -5.213271590930e-01 
+ 9.128000000000e-10 -6.275881896870e-01 
+ 9.228000000000e-10 -7.010270518598e-01 
+ 9.328000000000e-10 -7.428457852801e-01 
+ 9.428000000000e-10 -7.370853633469e-01 
+ 9.528000000000e-10 -6.577134719194e-01 
+ 9.628000000000e-10 -4.705123783357e-01 
+ 9.728000000000e-10 -1.887662540331e-01 
+ 9.828000000000e-10  1.063885555413e-01 
+ 9.928000000000e-10  3.530480784075e-01 
+ 1.000000000000e-09  4.814572085440e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/conditions.yaml
new file mode 100644
index 00000000..5baebc44
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 15
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_15
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb.sch
new file mode 100644
index 00000000..c9d91e93
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb_16.data
new file mode 100644
index 00000000..5b9b7365
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_core_tb_16.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.643042367579e-01 
+ 1.728000000000e-10 -1.889536448800e-01 
+ 1.828000000000e-10  1.011027156160e-01 
+ 1.928000000000e-10  3.431119917378e-01 
+ 2.028000000000e-10  5.070519088353e-01 
+ 2.128000000000e-10  6.112991757094e-01 
+ 2.228000000000e-10  6.838020209744e-01 
+ 2.328000000000e-10  7.242864479517e-01 
+ 2.428000000000e-10  7.174167448313e-01 
+ 2.528000000000e-10  6.398083866093e-01 
+ 2.628000000000e-10  4.585166519927e-01 
+ 2.728000000000e-10  1.844271573483e-01 
+ 2.828000000000e-10 -1.048019054065e-01 
+ 2.928000000000e-10 -3.462317584687e-01 
+ 3.028000000000e-10 -5.098344721858e-01 
+ 3.128000000000e-10 -6.133899227371e-01 
+ 3.228000000000e-10 -6.853968517792e-01 
+ 3.328000000000e-10 -7.251059393871e-01 
+ 3.428000000000e-10 -7.178642533065e-01 
+ 3.528000000000e-10 -6.398898931720e-01 
+ 3.628000000000e-10 -4.586473976402e-01 
+ 3.728000000000e-10 -1.843989570585e-01 
+ 3.828000000000e-10  1.047140758745e-01 
+ 3.928000000000e-10  3.462576483703e-01 
+ 4.028000000000e-10  5.097333770465e-01 
+ 4.128000000000e-10  6.134023110554e-01 
+ 4.228000000000e-10  6.853047053340e-01 
+ 4.328000000000e-10  7.251501511308e-01 
+ 4.428000000000e-10  7.178117501486e-01 
+ 4.528000000000e-10  6.399568281317e-01 
+ 4.628000000000e-10  4.586017943502e-01 
+ 4.728000000000e-10  1.844658494373e-01 
+ 4.828000000000e-10 -1.047609876408e-01 
+ 4.928000000000e-10 -3.462003104379e-01 
+ 5.028000000000e-10 -5.097813732572e-01 
+ 5.128000000000e-10 -6.133504189098e-01 
+ 5.228000000000e-10 -6.853547602223e-01 
+ 5.328000000000e-10 -7.250985458364e-01 
+ 5.428000000000e-10 -7.178593251267e-01 
+ 5.528000000000e-10 -6.399055102013e-01 
+ 5.628000000000e-10 -4.586511534755e-01 
+ 5.728000000000e-10 -1.844138975484e-01 
+ 5.828000000000e-10  1.047143295024e-01 
+ 5.928000000000e-10  3.462472486482e-01 
+ 6.028000000000e-10  5.097369504642e-01 
+ 6.128000000000e-10  6.133959963639e-01 
+ 6.228000000000e-10  6.853096740322e-01 
+ 6.328000000000e-10  7.251438129543e-01 
+ 6.428000000000e-10  7.178160816468e-01 
+ 6.528000000000e-10  6.399498616471e-01 
+ 6.628000000000e-10  4.586069220749e-01 
+ 6.728000000000e-10  1.844588245643e-01 
+ 6.828000000000e-10 -1.047563687876e-01 
+ 6.928000000000e-10 -3.462063328010e-01 
+ 7.028000000000e-10 -5.097765086741e-01 
+ 7.128000000000e-10 -6.133562893232e-01 
+ 7.228000000000e-10 -6.853494321266e-01 
+ 7.328000000000e-10 -7.251041291885e-01 
+ 7.428000000000e-10 -7.178542203751e-01 
+ 7.528000000000e-10 -6.399107355976e-01 
+ 7.628000000000e-10 -4.586462738291e-01 
+ 7.728000000000e-10 -1.844190131957e-01 
+ 7.828000000000e-10  1.047193339603e-01 
+ 7.928000000000e-10  3.462424630766e-01 
+ 8.028000000000e-10  5.097415276109e-01 
+ 8.128000000000e-10  6.133915881396e-01 
+ 8.228000000000e-10  6.853141467162e-01 
+ 8.328000000000e-10  7.251393167662e-01 
+ 8.428000000000e-10  7.178204152808e-01 
+ 8.528000000000e-10  6.399452651751e-01 
+ 8.628000000000e-10  4.586116651576e-01 
+ 8.728000000000e-10  1.844540563551e-01 
+ 8.828000000000e-10 -1.047521530128e-01 
+ 8.928000000000e-10 -3.462105768541e-01 
+ 9.028000000000e-10 -5.097724238353e-01 
+ 9.128000000000e-10 -6.133605792288e-01 
+ 9.228000000000e-10 -6.853452315529e-01 
+ 9.328000000000e-10 -7.251083207568e-01 
+ 9.428000000000e-10 -7.178502144615e-01 
+ 9.528000000000e-10 -6.399147306347e-01 
+ 9.628000000000e-10 -4.586423495280e-01 
+ 9.728000000000e-10 -1.844229988419e-01 
+ 9.828000000000e-10  1.047232268776e-01 
+ 9.928000000000e-10  3.462387497741e-01 
+ 1.000000000000e-09  4.710752262880e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/conditions.yaml
new file mode 100644
index 00000000..252bbf24
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 16
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_16
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb.sch
new file mode 100644
index 00000000..0be98424
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb_17.data
new file mode 100644
index 00000000..15600382
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_core_tb_17.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.852886719505e-01 
+ 1.728000000000e-10 -2.023606658915e-01 
+ 1.828000000000e-10  9.500407548716e-02 
+ 1.928000000000e-10  3.473018630854e-01 
+ 2.028000000000e-10  5.238539974445e-01 
+ 2.128000000000e-10  6.356942626004e-01 
+ 2.228000000000e-10  7.106560719901e-01 
+ 2.328000000000e-10  7.539243132234e-01 
+ 2.428000000000e-10  7.486736309564e-01 
+ 2.528000000000e-10  6.681985082542e-01 
+ 2.628000000000e-10  4.800908099257e-01 
+ 2.728000000000e-10  1.985903293754e-01 
+ 2.828000000000e-10 -9.801965724844e-02 
+ 2.928000000000e-10 -3.499456539083e-01 
+ 3.028000000000e-10 -5.264166063204e-01 
+ 3.128000000000e-10 -6.377599985577e-01 
+ 3.228000000000e-10 -7.123258227204e-01 
+ 3.328000000000e-10 -7.548386637736e-01 
+ 3.428000000000e-10 -7.491646196322e-01 
+ 3.528000000000e-10 -6.682802381819e-01 
+ 3.628000000000e-10 -4.802044877583e-01 
+ 3.728000000000e-10 -1.985554586747e-01 
+ 3.828000000000e-10  9.793570714348e-02 
+ 3.928000000000e-10  3.499705083814e-01 
+ 4.028000000000e-10  5.263126851869e-01 
+ 4.128000000000e-10  6.377668221774e-01 
+ 4.228000000000e-10  7.122256281615e-01 
+ 4.328000000000e-10  7.548735616237e-01 
+ 4.428000000000e-10  7.491068615558e-01 
+ 4.528000000000e-10  6.683430307676e-01 
+ 4.628000000000e-10  4.801581700099e-01 
+ 4.728000000000e-10  1.986186025664e-01 
+ 4.828000000000e-10 -9.798359332438e-02 
+ 4.928000000000e-10 -3.499159407959e-01 
+ 5.028000000000e-10 -5.263605524234e-01 
+ 5.128000000000e-10 -6.377159898188e-01 
+ 5.228000000000e-10 -7.122753084256e-01 
+ 5.328000000000e-10 -7.548237332543e-01 
+ 5.428000000000e-10 -7.491535548765e-01 
+ 5.528000000000e-10 -6.682936663178e-01 
+ 5.628000000000e-10 -4.802057994081e-01 
+ 5.728000000000e-10 -1.985692377738e-01 
+ 5.828000000000e-10  9.793754425938e-02 
+ 5.928000000000e-10  3.499612594703e-01 
+ 6.028000000000e-10  5.263165540334e-01 
+ 6.128000000000e-10  6.377608692391e-01 
+ 6.228000000000e-10  7.122309292959e-01 
+ 6.328000000000e-10  7.548679483739e-01 
+ 6.428000000000e-10  7.491113260135e-01 
+ 6.528000000000e-10  6.683367510584e-01 
+ 6.628000000000e-10  4.801631540398e-01 
+ 6.728000000000e-10  1.986123746205e-01 
+ 6.828000000000e-10 -9.797860547701e-02 
+ 6.928000000000e-10 -3.499219086015e-01 
+ 7.028000000000e-10 -5.263552271330e-01 
+ 7.128000000000e-10 -6.377219921840e-01 
+ 7.228000000000e-10 -7.122696952774e-01 
+ 7.328000000000e-10 -7.548295298651e-01 
+ 7.428000000000e-10 -7.491481908175e-01 
+ 7.528000000000e-10 -6.682991221138e-01 
+ 7.628000000000e-10 -4.802006967346e-01 
+ 7.728000000000e-10 -1.985745887274e-01 
+ 7.828000000000e-10  9.794256695295e-02 
+ 7.928000000000e-10  3.499565849765e-01 
+ 8.028000000000e-10  5.263210489698e-01 
+ 8.128000000000e-10  6.377564579322e-01 
+ 8.228000000000e-10  7.122353719246e-01 
+ 8.328000000000e-10  7.548635649925e-01 
+ 8.428000000000e-10  7.491155123701e-01 
+ 8.528000000000e-10  6.683323549155e-01 
+ 8.628000000000e-10  4.801676539865e-01 
+ 8.728000000000e-10  1.986078923136e-01 
+ 8.828000000000e-10 -9.797434132868e-02 
+ 8.928000000000e-10 -3.499261582655e-01 
+ 9.028000000000e-10 -5.263510069851e-01 
+ 9.128000000000e-10 -6.377263524572e-01 
+ 9.228000000000e-10 -7.122654282965e-01 
+ 9.328000000000e-10 -7.548337908470e-01 
+ 9.428000000000e-10 -7.491440991364e-01 
+ 9.528000000000e-10 -6.683032069827e-01 
+ 9.628000000000e-10 -4.801967157057e-01 
+ 9.728000000000e-10 -1.985786291727e-01 
+ 9.828000000000e-10  9.794644208878e-02 
+ 9.928000000000e-10  3.499529545785e-01 
+ 1.000000000000e-09  4.843355885316e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/conditions.yaml
new file mode 100644
index 00000000..0c4952bc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 17
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_17
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb.sch
new file mode 100644
index 00000000..328a4361
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb_18.data
new file mode 100644
index 00000000..6bdb4a2e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_core_tb_18.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.747244840755e-01 
+ 1.728000000000e-10  2.031348680811e-01 
+ 1.828000000000e-10 -1.640358346053e-01 
+ 1.928000000000e-10 -4.121983890365e-01 
+ 2.028000000000e-10 -5.403960481430e-01 
+ 2.128000000000e-10 -6.175267008304e-01 
+ 2.228000000000e-10 -7.185181164841e-01 
+ 2.328000000000e-10 -8.111835866476e-01 
+ 2.428000000000e-10 -8.505757111821e-01 
+ 2.528000000000e-10 -7.941523888433e-01 
+ 2.628000000000e-10 -5.697557803605e-01 
+ 2.728000000000e-10 -1.993901761575e-01 
+ 2.828000000000e-10  1.667454340744e-01 
+ 2.928000000000e-10  4.143424459307e-01 
+ 3.028000000000e-10  5.421310172268e-01 
+ 3.128000000000e-10  6.189024162340e-01 
+ 3.228000000000e-10  7.194369498053e-01 
+ 3.328000000000e-10  8.117600127730e-01 
+ 3.428000000000e-10  8.508336653308e-01 
+ 3.528000000000e-10  7.942656656211e-01 
+ 3.628000000000e-10  5.697751550033e-01 
+ 3.728000000000e-10  1.994135726672e-01 
+ 3.828000000000e-10 -1.667386419247e-01 
+ 3.928000000000e-10 -4.143148464313e-01 
+ 4.028000000000e-10 -5.421262038320e-01 
+ 4.128000000000e-10 -6.188832903749e-01 
+ 4.228000000000e-10 -7.194346712496e-01 
+ 4.328000000000e-10 -8.117442314974e-01 
+ 4.428000000000e-10 -8.508381039982e-01 
+ 4.528000000000e-10 -7.942559196005e-01 
+ 4.628000000000e-10 -5.697859373045e-01 
+ 4.728000000000e-10 -1.993975895742e-01 
+ 4.828000000000e-10  1.667322235508e-01 
+ 4.928000000000e-10  4.143280512458e-01 
+ 5.028000000000e-10  5.421195877560e-01 
+ 5.128000000000e-10  6.188968586913e-01 
+ 5.228000000000e-10  7.194236426239e-01 
+ 5.328000000000e-10  8.117540342679e-01 
+ 5.428000000000e-10  8.508266757829e-01 
+ 5.528000000000e-10  7.942652287581e-01 
+ 5.628000000000e-10  5.697754142960e-01 
+ 5.728000000000e-10  1.994033695962e-01 
+ 5.828000000000e-10 -1.667424669503e-01 
+ 5.928000000000e-10 -4.143216611718e-01 
+ 6.028000000000e-10 -5.421291067647e-01 
+ 6.128000000000e-10 -6.188909595847e-01 
+ 6.228000000000e-10 -7.194310352535e-01 
+ 6.328000000000e-10 -8.117467342350e-01 
+ 6.428000000000e-10 -8.508333273630e-01 
+ 6.528000000000e-10 -7.942577903765e-01 
+ 6.628000000000e-10 -5.697836419865e-01 
+ 6.728000000000e-10 -1.993929431350e-01 
+ 6.828000000000e-10  1.667361734044e-01 
+ 6.928000000000e-10  4.143307053824e-01 
+ 7.028000000000e-10  5.421226813799e-01 
+ 7.128000000000e-10  6.189001833416e-01 
+ 7.228000000000e-10  7.194227358993e-01 
+ 7.328000000000e-10  8.117542266055e-01 
+ 7.428000000000e-10  8.508251070290e-01 
+ 7.528000000000e-10  7.942649966766e-01 
+ 7.628000000000e-10  5.697756363247e-01 
+ 7.728000000000e-10  1.993989977467e-01 
+ 7.828000000000e-10 -1.667434615441e-01 
+ 7.928000000000e-10 -4.143248161746e-01 
+ 8.028000000000e-10 -5.421295610790e-01 
+ 8.128000000000e-10 -6.188945163710e-01 
+ 8.228000000000e-10 -7.194289229798e-01 
+ 8.328000000000e-10 -8.117483413843e-01 
+ 8.428000000000e-10 -8.508308647988e-01 
+ 8.528000000000e-10 -7.942590780393e-01 
+ 8.628000000000e-10 -5.697822347435e-01 
+ 8.728000000000e-10 -1.993917000580e-01 
+ 8.828000000000e-10  1.667380255271e-01 
+ 8.928000000000e-10  4.143314131245e-01 
+ 9.028000000000e-10  5.421241182927e-01 
+ 9.128000000000e-10  6.189011822630e-01 
+ 9.228000000000e-10  7.194226089303e-01 
+ 9.328000000000e-10  8.117540798381e-01 
+ 9.428000000000e-10  8.508247577722e-01 
+ 9.528000000000e-10  7.942646412254e-01 
+ 9.628000000000e-10  5.697760282588e-01 
+ 9.728000000000e-10  1.993969946892e-01 
+ 9.828000000000e-10 -1.667434796269e-01 
+ 9.928000000000e-10 -4.143264352220e-01 
+ 1.000000000000e-09 -5.150731751424e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/conditions.yaml
new file mode 100644
index 00000000..8c98dac6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 18
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_18
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb.sch
new file mode 100644
index 00000000..c09a1129
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb_19.data
new file mode 100644
index 00000000..cfa0d051
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_core_tb_19.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.707988120441e-01 
+ 1.728000000000e-10  2.050562196689e-01 
+ 1.828000000000e-10 -1.568083182045e-01 
+ 1.928000000000e-10 -4.020696229917e-01 
+ 2.028000000000e-10 -5.270997867267e-01 
+ 2.128000000000e-10 -6.030122328411e-01 
+ 2.228000000000e-10 -7.060404303518e-01 
+ 2.328000000000e-10 -7.977729548420e-01 
+ 2.428000000000e-10 -8.357087979117e-01 
+ 2.528000000000e-10 -7.823438332914e-01 
+ 2.628000000000e-10 -5.641015035384e-01 
+ 2.728000000000e-10 -1.996979729386e-01 
+ 2.828000000000e-10  1.605395493177e-01 
+ 2.928000000000e-10  4.049019788065e-01 
+ 3.028000000000e-10  5.293349858313e-01 
+ 3.128000000000e-10  6.047755538782e-01 
+ 3.228000000000e-10  7.072083327509e-01 
+ 3.328000000000e-10  7.985177439850e-01 
+ 3.428000000000e-10  8.360745897587e-01 
+ 3.528000000000e-10  7.825643018760e-01 
+ 3.628000000000e-10  5.642043953033e-01 
+ 3.728000000000e-10  1.998026918934e-01 
+ 3.828000000000e-10 -1.604858693758e-01 
+ 3.928000000000e-10 -4.048299316522e-01 
+ 4.028000000000e-10 -5.293048172022e-01 
+ 4.128000000000e-10 -6.047267733392e-01 
+ 4.228000000000e-10 -7.071932602489e-01 
+ 4.328000000000e-10 -7.984844304353e-01 
+ 4.428000000000e-10 -8.360789616419e-01 
+ 4.528000000000e-10 -7.825446968704e-01 
+ 4.628000000000e-10 -5.642205462461e-01 
+ 4.728000000000e-10 -1.997755595675e-01 
+ 4.828000000000e-10  1.604765943145e-01 
+ 4.928000000000e-10  4.048512691297e-01 
+ 5.028000000000e-10  5.292953655278e-01 
+ 5.128000000000e-10  6.047472585148e-01 
+ 5.228000000000e-10  7.071773753770e-01 
+ 5.328000000000e-10  7.985008103891e-01 
+ 5.428000000000e-10  8.360621173440e-01 
+ 5.528000000000e-10  7.825604957102e-01 
+ 5.628000000000e-10  5.642042607216e-01 
+ 5.728000000000e-10  1.997857962408e-01 
+ 5.828000000000e-10 -1.604926267251e-01 
+ 5.928000000000e-10 -4.048407079574e-01 
+ 6.028000000000e-10 -5.293103597207e-01 
+ 6.128000000000e-10 -6.047374718328e-01 
+ 6.228000000000e-10 -7.071895246392e-01 
+ 6.328000000000e-10 -7.984887922220e-01 
+ 6.428000000000e-10 -8.360735876941e-01 
+ 6.528000000000e-10 -7.825482507809e-01 
+ 6.628000000000e-10 -5.642183473935e-01 
+ 6.728000000000e-10 -1.997692084041e-01 
+ 6.828000000000e-10  1.604823178167e-01 
+ 6.928000000000e-10  4.048548923992e-01 
+ 7.028000000000e-10  5.293001528657e-01 
+ 7.128000000000e-10  6.047514904939e-01 
+ 7.228000000000e-10  7.071767775245e-01 
+ 7.328000000000e-10  7.985010886851e-01 
+ 7.428000000000e-10  8.360609061049e-01 
+ 7.528000000000e-10  7.825602391468e-01 
+ 7.628000000000e-10  5.642057995328e-01 
+ 7.728000000000e-10  1.997793833692e-01 
+ 7.828000000000e-10 -1.604939026989e-01 
+ 7.928000000000e-10 -4.048452814924e-01 
+ 8.028000000000e-10 -5.293110935611e-01 
+ 8.128000000000e-10 -6.047422910037e-01 
+ 8.228000000000e-10 -7.071868576548e-01 
+ 8.328000000000e-10 -7.984914661054e-01 
+ 8.428000000000e-10 -8.360704549701e-01 
+ 8.528000000000e-10 -7.825505283213e-01 
+ 8.628000000000e-10 -5.642168951425e-01 
+ 8.728000000000e-10 -1.997675829904e-01 
+ 8.828000000000e-10  1.604850893678e-01 
+ 8.928000000000e-10  4.048557791622e-01 
+ 9.028000000000e-10  5.293024006551e-01 
+ 9.128000000000e-10  6.047526676189e-01 
+ 9.228000000000e-10  7.071769813422e-01 
+ 9.328000000000e-10  7.985009240492e-01 
+ 9.428000000000e-10  8.360608174754e-01 
+ 9.528000000000e-10  7.825597625659e-01 
+ 9.628000000000e-10  5.642070937767e-01 
+ 9.728000000000e-10  1.997763618165e-01 
+ 9.828000000000e-10 -1.604938267743e-01 
+ 9.928000000000e-10 -4.048476936234e-01 
+ 1.000000000000e-09 -5.033604123532e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/conditions.yaml
new file mode 100644
index 00000000..8604dc5c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 19
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_19
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb.sch
new file mode 100644
index 00000000..40ea2fb0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb_20.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb_20.data
new file mode 100644
index 00000000..696f2b8b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_core_tb_20.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.787258342535e-01 
+ 1.728000000000e-10  2.078017915173e-01 
+ 1.828000000000e-10 -1.622649468476e-01 
+ 1.928000000000e-10 -4.154784848215e-01 
+ 2.028000000000e-10 -5.503628241592e-01 
+ 2.128000000000e-10 -6.299323770996e-01 
+ 2.228000000000e-10 -7.254942323191e-01 
+ 2.328000000000e-10 -8.176578932007e-01 
+ 2.428000000000e-10 -8.600222409410e-01 
+ 2.528000000000e-10 -8.019093712422e-01 
+ 2.628000000000e-10 -5.756893793886e-01 
+ 2.728000000000e-10 -2.057606209176e-01 
+ 2.828000000000e-10  1.639197157563e-01 
+ 2.928000000000e-10  4.168841038800e-01 
+ 3.028000000000e-10  5.515424627408e-01 
+ 3.128000000000e-10  6.308336221978e-01 
+ 3.228000000000e-10  7.261208861559e-01 
+ 3.328000000000e-10  8.180354096547e-01 
+ 3.428000000000e-10  8.601969327831e-01 
+ 3.528000000000e-10  8.019450515145e-01 
+ 3.628000000000e-10  5.756806762770e-01 
+ 3.728000000000e-10  2.057351595047e-01 
+ 3.828000000000e-10 -1.639234125928e-01 
+ 3.928000000000e-10 -4.168916689126e-01 
+ 4.028000000000e-10 -5.515399403849e-01 
+ 4.128000000000e-10 -6.308421950132e-01 
+ 4.228000000000e-10 -7.261151591955e-01 
+ 4.328000000000e-10 -8.180409257235e-01 
+ 4.428000000000e-10 -8.601903753395e-01 
+ 4.528000000000e-10 -8.019506024478e-01 
+ 4.628000000000e-10 -5.756757498169e-01 
+ 4.728000000000e-10 -2.057370812605e-01 
+ 4.828000000000e-10  1.639284669376e-01 
+ 4.928000000000e-10  4.168895758092e-01 
+ 5.028000000000e-10  5.515444733402e-01 
+ 5.128000000000e-10  6.308408648378e-01 
+ 5.228000000000e-10  7.261175778597e-01 
+ 5.328000000000e-10  8.180376908128e-01 
+ 5.428000000000e-10  8.601923700088e-01 
+ 5.528000000000e-10  8.019470527506e-01 
+ 5.628000000000e-10  5.756789455974e-01 
+ 5.728000000000e-10  2.057316537746e-01 
+ 5.828000000000e-10 -1.639258645561e-01 
+ 5.928000000000e-10 -4.168940343704e-01 
+ 6.028000000000e-10 -5.515416140289e-01 
+ 6.128000000000e-10 -6.308456056710e-01 
+ 6.228000000000e-10 -7.261132930683e-01 
+ 6.328000000000e-10 -8.180415890619e-01 
+ 6.428000000000e-10 -8.601877913845e-01 
+ 6.528000000000e-10 -8.019507055326e-01 
+ 6.628000000000e-10 -5.756748223597e-01 
+ 6.728000000000e-10 -2.057339330851e-01 
+ 6.828000000000e-10  1.639294327626e-01 
+ 6.928000000000e-10  4.168918933453e-01 
+ 7.028000000000e-10  5.515448110547e-01 
+ 7.128000000000e-10  6.308438013344e-01 
+ 7.228000000000e-10  7.261156471026e-01 
+ 7.328000000000e-10  8.180389426729e-01 
+ 7.428000000000e-10  8.601899882644e-01 
+ 7.528000000000e-10  8.019478991926e-01 
+ 7.628000000000e-10  5.756775488816e-01 
+ 7.728000000000e-10  2.057303912125e-01 
+ 7.828000000000e-10 -1.639270777727e-01 
+ 7.928000000000e-10 -4.168949361223e-01 
+ 8.028000000000e-10 -5.515423789761e-01 
+ 8.128000000000e-10 -6.308469511551e-01 
+ 8.228000000000e-10 -7.261125857103e-01 
+ 8.328000000000e-10 -8.180418172660e-01 
+ 8.428000000000e-10 -8.601868536640e-01 
+ 8.528000000000e-10 -8.019506539776e-01 
+ 8.628000000000e-10 -5.756745040863e-01 
+ 8.728000000000e-10 -2.057325997968e-01 
+ 8.828000000000e-10  1.639296206310e-01 
+ 8.928000000000e-10  4.168929982528e-01 
+ 9.028000000000e-10  5.515447184418e-01 
+ 9.128000000000e-10  6.308451859194e-01 
+ 9.228000000000e-10  7.261146020976e-01 
+ 9.328000000000e-10  8.180396416883e-01 
+ 9.428000000000e-10  8.601888436252e-01 
+ 9.528000000000e-10  8.019484098509e-01 
+ 9.628000000000e-10  5.756767177581e-01 
+ 9.728000000000e-10  2.057300830001e-01 
+ 9.828000000000e-10 -1.639276725752e-01 
+ 9.928000000000e-10 -4.168951851932e-01 
+ 1.000000000000e-09 -5.223291820834e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/conditions.yaml
new file mode 100644
index 00000000..1514a4fc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 20
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_20
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb.sch
new file mode 100644
index 00000000..31235299
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb_21.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb_21.data
new file mode 100644
index 00000000..b199692b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_core_tb_21.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.573501255338e-01 
+ 1.728000000000e-10  2.075317226020e-01 
+ 1.828000000000e-10 -1.459750710281e-01 
+ 1.928000000000e-10 -3.981214724862e-01 
+ 2.028000000000e-10 -5.378144391949e-01 
+ 2.128000000000e-10 -6.222071778117e-01 
+ 2.228000000000e-10 -7.144656924256e-01 
+ 2.328000000000e-10 -7.957588475985e-01 
+ 2.428000000000e-10 -8.259944634024e-01 
+ 2.528000000000e-10 -7.639419051023e-01 
+ 2.628000000000e-10 -5.499582313836e-01 
+ 2.728000000000e-10 -2.015822705639e-01 
+ 2.828000000000e-10  1.503547149045e-01 
+ 2.928000000000e-10  4.016725871885e-01 
+ 3.028000000000e-10  5.406529598204e-01 
+ 3.128000000000e-10  6.244429748136e-01 
+ 3.228000000000e-10  7.159703736038e-01 
+ 3.328000000000e-10  7.967442303644e-01 
+ 3.428000000000e-10  8.264465978318e-01 
+ 3.528000000000e-10  7.642028659706e-01 
+ 3.628000000000e-10  5.500598536778e-01 
+ 3.728000000000e-10  2.017167809837e-01 
+ 3.828000000000e-10 -1.502994036069e-01 
+ 3.928000000000e-10 -4.015772846450e-01 
+ 4.028000000000e-10 -5.406194194587e-01 
+ 4.128000000000e-10 -6.243734224937e-01 
+ 4.228000000000e-10 -7.159615996115e-01 
+ 4.328000000000e-10 -7.966982014285e-01 
+ 4.428000000000e-10 -8.264613960108e-01 
+ 4.528000000000e-10 -7.641725666632e-01 
+ 4.628000000000e-10 -5.500862997678e-01 
+ 4.728000000000e-10 -2.016863380222e-01 
+ 4.828000000000e-10  1.502773228882e-01 
+ 4.928000000000e-10  4.016041852700e-01 
+ 5.028000000000e-10  5.405973091915e-01 
+ 5.128000000000e-10  6.243995261147e-01 
+ 5.228000000000e-10  7.159367954986e-01 
+ 5.328000000000e-10  7.967237369409e-01 
+ 5.428000000000e-10  8.264362767952e-01 
+ 5.528000000000e-10  7.641972989051e-01 
+ 5.628000000000e-10  5.500612169320e-01 
+ 5.728000000000e-10  2.017098008556e-01 
+ 5.828000000000e-10 -1.502994747055e-01 
+ 5.928000000000e-10 -4.015836624598e-01 
+ 6.028000000000e-10 -5.406181129288e-01 
+ 6.128000000000e-10 -6.243799299897e-01 
+ 6.228000000000e-10 -7.159574419629e-01 
+ 6.328000000000e-10 -7.967036557443e-01 
+ 6.428000000000e-10 -8.264562124237e-01 
+ 6.528000000000e-10 -7.641768324224e-01 
+ 6.628000000000e-10 -5.500832409355e-01 
+ 6.728000000000e-10 -2.016878835950e-01 
+ 6.828000000000e-10  1.502805147690e-01 
+ 6.928000000000e-10  4.016033959904e-01 
+ 7.028000000000e-10  5.405993862387e-01 
+ 7.128000000000e-10  6.243994053085e-01 
+ 7.228000000000e-10  7.159375001908e-01 
+ 7.328000000000e-10  7.967227911979e-01 
+ 7.428000000000e-10  8.264369695557e-01 
+ 7.528000000000e-10  7.641957504677e-01 
+ 7.628000000000e-10  5.500638388088e-01 
+ 7.728000000000e-10  2.017065810231e-01 
+ 7.828000000000e-10 -1.502977706940e-01 
+ 7.928000000000e-10 -4.015868518817e-01 
+ 8.028000000000e-10 -5.406159021220e-01 
+ 8.128000000000e-10 -6.243834226598e-01 
+ 8.228000000000e-10 -7.159542700032e-01 
+ 8.328000000000e-10 -7.967069113699e-01 
+ 8.428000000000e-10 -8.264528986398e-01 
+ 8.528000000000e-10 -7.641796598358e-01 
+ 8.628000000000e-10 -5.500810114131e-01 
+ 8.728000000000e-10 -2.016895461018e-01 
+ 8.828000000000e-10  1.502827695530e-01 
+ 8.928000000000e-10  4.016022282365e-01 
+ 9.028000000000e-10  5.406011687872e-01 
+ 9.128000000000e-10  6.243986267121e-01 
+ 9.228000000000e-10  7.159387803359e-01 
+ 9.328000000000e-10  7.967217157361e-01 
+ 9.428000000000e-10  8.264380732409e-01 
+ 9.528000000000e-10  7.641943142595e-01 
+ 9.628000000000e-10  5.500658668163e-01 
+ 9.728000000000e-10  2.017043552905e-01 
+ 9.828000000000e-10 -1.502962363926e-01 
+ 9.928000000000e-10 -4.015890294030e-01 
+ 1.000000000000e-09 -5.098048460363e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/conditions.yaml
new file mode 100644
index 00000000..8184d1c1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 21
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_21
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb.sch
new file mode 100644
index 00000000..e729411a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb_22.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb_22.data
new file mode 100644
index 00000000..60989baa
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_core_tb_22.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.539342660958e-01 
+ 1.728000000000e-10  2.092356958505e-01 
+ 1.828000000000e-10 -1.399589402437e-01 
+ 1.928000000000e-10 -3.887664135754e-01 
+ 2.028000000000e-10 -5.242925922458e-01 
+ 2.128000000000e-10 -6.069418933180e-01 
+ 2.228000000000e-10 -7.009344183633e-01 
+ 2.328000000000e-10 -7.819154973681e-01 
+ 2.428000000000e-10 -8.115011787752e-01 
+ 2.528000000000e-10 -7.528782125237e-01 
+ 2.628000000000e-10 -5.449881732974e-01 
+ 2.728000000000e-10 -2.018085669996e-01 
+ 2.828000000000e-10  1.453371294429e-01 
+ 2.928000000000e-10  3.930046196046e-01 
+ 3.028000000000e-10  5.275952350978e-01 
+ 3.128000000000e-10  6.094983923496e-01 
+ 3.228000000000e-10  7.026430994561e-01 
+ 3.328000000000e-10  7.830459101342e-01 
+ 3.428000000000e-10  8.120643124066e-01 
+ 3.528000000000e-10  7.532542388222e-01 
+ 3.628000000000e-10  5.451889146656e-01 
+ 3.728000000000e-10  2.020380161925e-01 
+ 3.828000000000e-10 -1.452202245966e-01 
+ 3.928000000000e-10 -3.928550396378e-01 
+ 4.028000000000e-10 -5.275272038156e-01 
+ 4.128000000000e-10 -6.093963788491e-01 
+ 4.228000000000e-10 -7.026185076638e-01 
+ 4.328000000000e-10 -7.829822343256e-01 
+ 4.428000000000e-10 -8.120760322925e-01 
+ 4.528000000000e-10 -7.532137307257e-01 
+ 4.628000000000e-10 -5.452168897181e-01 
+ 4.728000000000e-10 -2.019975663161e-01 
+ 4.828000000000e-10  1.451970774770e-01 
+ 4.928000000000e-10  3.928886426712e-01 
+ 5.028000000000e-10  5.275035947470e-01 
+ 5.128000000000e-10  6.094279224341e-01 
+ 5.228000000000e-10  7.025906785817e-01 
+ 5.328000000000e-10  7.830125874729e-01 
+ 5.428000000000e-10  8.120474298427e-01 
+ 5.528000000000e-10  7.532431353399e-01 
+ 5.628000000000e-10  5.451877569897e-01 
+ 5.728000000000e-10  2.020249691554e-01 
+ 5.828000000000e-10 -1.452230860448e-01 
+ 5.928000000000e-10 -3.928644448798e-01 
+ 6.028000000000e-10 -5.275279936983e-01 
+ 6.128000000000e-10 -6.094050782075e-01 
+ 6.228000000000e-10 -7.026148963104e-01 
+ 6.328000000000e-10 -7.829886841749e-01 
+ 6.428000000000e-10 -8.120708569069e-01 
+ 6.528000000000e-10 -7.532187757848e-01 
+ 6.628000000000e-10 -5.452139572157e-01 
+ 6.728000000000e-10 -2.019983459359e-01 
+ 6.828000000000e-10  1.452010057661e-01 
+ 6.928000000000e-10  3.928879698340e-01 
+ 7.028000000000e-10  5.275064479083e-01 
+ 7.128000000000e-10  6.094280990005e-01 
+ 7.228000000000e-10  7.025917879356e-01 
+ 7.328000000000e-10  7.830113821989e-01 
+ 7.428000000000e-10  8.120485256383e-01 
+ 7.528000000000e-10  7.532412367972e-01 
+ 7.628000000000e-10  5.451912171970e-01 
+ 7.728000000000e-10  2.020204953427e-01 
+ 7.828000000000e-10 -1.452213117732e-01 
+ 7.928000000000e-10 -3.928683087954e-01 
+ 8.028000000000e-10 -5.275257546899e-01 
+ 8.128000000000e-10 -6.094092443434e-01 
+ 8.228000000000e-10 -7.026114152643e-01 
+ 8.328000000000e-10 -7.829924127838e-01 
+ 8.428000000000e-10 -8.120671951794e-01 
+ 8.528000000000e-10 -7.532220607865e-01 
+ 8.628000000000e-10 -5.452116115033e-01 
+ 8.728000000000e-10 -2.019999026099e-01 
+ 8.828000000000e-10  1.452037268076e-01 
+ 8.928000000000e-10  3.928866787286e-01 
+ 9.028000000000e-10  5.275085793908e-01 
+ 9.128000000000e-10  6.094272189130e-01 
+ 9.228000000000e-10  7.025932924679e-01 
+ 9.328000000000e-10  7.830100596429e-01 
+ 9.428000000000e-10  8.120498613680e-01 
+ 9.528000000000e-10  7.532395420815e-01 
+ 9.628000000000e-10  5.451937902395e-01 
+ 9.728000000000e-10  2.020175827840e-01 
+ 9.828000000000e-10 -1.452196157349e-01 
+ 9.928000000000e-10 -3.928709378362e-01 
+ 1.000000000000e-09 -4.979849828547e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/conditions.yaml
new file mode 100644
index 00000000..9ee9fc95
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 22
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_22
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb.sch
new file mode 100644
index 00000000..15caf797
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb_23.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb_23.data
new file mode 100644
index 00000000..208aa09a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_core_tb_23.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.609932954578e-01 
+ 1.728000000000e-10  2.135803595156e-01 
+ 1.828000000000e-10 -1.406795105233e-01 
+ 1.928000000000e-10 -3.985242549940e-01 
+ 2.028000000000e-10 -5.467902250198e-01 
+ 2.128000000000e-10 -6.349197102047e-01 
+ 2.228000000000e-10 -7.225601155251e-01 
+ 2.328000000000e-10 -8.022847270862e-01 
+ 2.428000000000e-10 -8.341174139963e-01 
+ 2.528000000000e-10 -7.703472968512e-01 
+ 2.628000000000e-10 -5.554753546701e-01 
+ 2.728000000000e-10 -2.092959847468e-01 
+ 2.828000000000e-10  1.439827087572e-01 
+ 2.928000000000e-10  4.013409764958e-01 
+ 3.028000000000e-10  5.491103575815e-01 
+ 3.128000000000e-10  6.367736171292e-01 
+ 3.228000000000e-10  7.238327114492e-01 
+ 3.328000000000e-10  8.031250424519e-01 
+ 3.428000000000e-10  8.344898451807e-01 
+ 3.528000000000e-10  7.705288945959e-01 
+ 3.628000000000e-10  5.555161552443e-01 
+ 3.728000000000e-10  2.093659332353e-01 
+ 3.828000000000e-10 -1.439645708780e-01 
+ 3.928000000000e-10 -4.012864243472e-01 
+ 4.028000000000e-10 -5.490981432908e-01 
+ 4.128000000000e-10 -6.367310776976e-01 
+ 4.228000000000e-10 -7.238327358891e-01 
+ 4.328000000000e-10 -8.030945225544e-01 
+ 4.428000000000e-10 -8.345032641498e-01 
+ 4.528000000000e-10 -7.705076814073e-01 
+ 4.628000000000e-10 -5.555368200040e-01 
+ 4.728000000000e-10 -2.093450233604e-01 
+ 4.828000000000e-10  1.439466188317e-01 
+ 4.928000000000e-10  4.013057839415e-01 
+ 5.028000000000e-10  5.490801810840e-01 
+ 5.128000000000e-10  6.367502973173e-01 
+ 5.228000000000e-10  7.238134370273e-01 
+ 5.328000000000e-10  8.031142213064e-01 
+ 5.428000000000e-10  8.344836920712e-01 
+ 5.528000000000e-10  7.705267055682e-01 
+ 5.628000000000e-10  5.555176728822e-01 
+ 5.728000000000e-10  2.093634169255e-01 
+ 5.828000000000e-10 -1.439633135713e-01 
+ 5.928000000000e-10 -4.012903718012e-01 
+ 6.028000000000e-10 -5.490957661747e-01 
+ 6.128000000000e-10 -6.367354259501e-01 
+ 6.228000000000e-10 -7.238289911799e-01 
+ 6.328000000000e-10 -8.030991093312e-01 
+ 6.428000000000e-10 -8.344987261970e-01 
+ 6.528000000000e-10 -7.705113506628e-01 
+ 6.628000000000e-10 -5.555339922038e-01 
+ 6.728000000000e-10 -2.093472747699e-01 
+ 6.828000000000e-10  1.439488143392e-01 
+ 6.928000000000e-10  4.013051006454e-01 
+ 7.028000000000e-10  5.490813620131e-01 
+ 7.128000000000e-10  6.367501696447e-01 
+ 7.228000000000e-10  7.238138408460e-01 
+ 7.328000000000e-10  8.031138234310e-01 
+ 7.428000000000e-10  8.344840024625e-01 
+ 7.528000000000e-10  7.705257750612e-01 
+ 7.628000000000e-10  5.555193682491e-01 
+ 7.728000000000e-10  2.093616154732e-01 
+ 7.828000000000e-10 -1.439618235384e-01 
+ 7.928000000000e-10 -4.012927107128e-01 
+ 8.028000000000e-10 -5.490937463184e-01 
+ 8.128000000000e-10 -6.367380404539e-01 
+ 8.228000000000e-10 -7.238264478501e-01 
+ 8.328000000000e-10 -8.031018435980e-01 
+ 8.428000000000e-10 -8.344959687989e-01 
+ 8.528000000000e-10 -7.705137100306e-01 
+ 8.628000000000e-10 -5.555321098787e-01 
+ 8.728000000000e-10 -2.093489927492e-01 
+ 8.828000000000e-10  1.439504269532e-01 
+ 8.928000000000e-10  4.013041525432e-01 
+ 9.028000000000e-10  5.490824887692e-01 
+ 9.128000000000e-10  6.367494882502e-01 
+ 9.228000000000e-10  7.238146944607e-01 
+ 9.328000000000e-10  8.031131051507e-01 
+ 9.428000000000e-10  8.344847147049e-01 
+ 9.528000000000e-10  7.705248067970e-01 
+ 9.628000000000e-10  5.555207970002e-01 
+ 9.728000000000e-10  2.093601819839e-01 
+ 9.828000000000e-10 -1.439605753448e-01 
+ 9.928000000000e-10 -4.012943342775e-01 
+ 1.000000000000e-09 -5.158218772706e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/conditions.yaml
new file mode 100644
index 00000000..76389497
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 23
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_23
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb.sch
new file mode 100644
index 00000000..5d1666cf
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb_24.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb_24.data
new file mode 100644
index 00000000..a8519464
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_core_tb_24.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.405028365217e-01 
+ 1.728000000000e-10  2.142897527484e-01 
+ 1.828000000000e-10 -1.231353412434e-01 
+ 1.928000000000e-10 -3.782847553257e-01 
+ 2.028000000000e-10 -5.290944707244e-01 
+ 2.128000000000e-10 -6.207435846591e-01 
+ 2.228000000000e-10 -7.069850917784e-01 
+ 2.328000000000e-10 -7.774395392863e-01 
+ 2.428000000000e-10 -7.982183108700e-01 
+ 2.528000000000e-10 -7.327456021571e-01 
+ 2.628000000000e-10 -5.310063164445e-01 
+ 2.728000000000e-10 -2.063297175293e-01 
+ 2.828000000000e-10  1.293176468137e-01 
+ 2.928000000000e-10  3.835270490977e-01 
+ 3.028000000000e-10  5.333180257023e-01 
+ 3.128000000000e-10  6.240938619865e-01 
+ 3.228000000000e-10  7.092802493907e-01 
+ 3.328000000000e-10  7.789607942300e-01 
+ 3.428000000000e-10  7.989234313230e-01 
+ 3.528000000000e-10  7.331763415294e-01 
+ 3.628000000000e-10  5.312045040772e-01 
+ 3.728000000000e-10  2.065847902134e-01 
+ 3.828000000000e-10 -1.291958906021e-01 
+ 3.928000000000e-10 -3.833411283085e-01 
+ 4.028000000000e-10 -5.332389173297e-01 
+ 4.128000000000e-10 -6.239588708494e-01 
+ 4.228000000000e-10 -7.092541595355e-01 
+ 4.328000000000e-10 -7.788766619073e-01 
+ 4.428000000000e-10 -7.989439817890e-01 
+ 4.528000000000e-10 -7.331237184970e-01 
+ 4.628000000000e-10 -5.312431858800e-01 
+ 4.728000000000e-10 -2.065354720445e-01 
+ 4.828000000000e-10  1.291604530900e-01 
+ 4.928000000000e-10  3.833851407049e-01 
+ 5.028000000000e-10  5.332033925163e-01 
+ 5.128000000000e-10  6.240009303805e-01 
+ 5.228000000000e-10  7.092156296740e-01 
+ 5.328000000000e-10  7.789178950697e-01 
+ 5.428000000000e-10  7.989050835748e-01 
+ 5.528000000000e-10  7.331635644704e-01 
+ 5.628000000000e-10  5.312038508238e-01 
+ 5.728000000000e-10  2.065745538625e-01 
+ 5.828000000000e-10 -1.291960705945e-01 
+ 5.928000000000e-10 -3.833509278886e-01 
+ 6.028000000000e-10 -5.332368573592e-01 
+ 6.128000000000e-10 -6.239679712691e-01 
+ 6.228000000000e-10 -7.092497084655e-01 
+ 6.328000000000e-10 -7.788845366535e-01 
+ 6.428000000000e-10 -7.989377629672e-01 
+ 6.528000000000e-10 -7.331298791234e-01 
+ 6.628000000000e-10 -5.312385744549e-01 
+ 6.728000000000e-10 -2.065399094583e-01 
+ 6.828000000000e-10  1.291646812354e-01 
+ 6.928000000000e-10  3.833822988637e-01 
+ 7.028000000000e-10  5.332062833028e-01 
+ 7.128000000000e-10  6.239988652624e-01 
+ 7.228000000000e-10  7.092181343784e-01 
+ 7.328000000000e-10  7.789155267181e-01 
+ 7.428000000000e-10  7.989074545455e-01 
+ 7.528000000000e-10  7.331605295450e-01 
+ 7.628000000000e-10  5.312080087648e-01 
+ 7.728000000000e-10  2.065705039315e-01 
+ 7.828000000000e-10 -1.291926212165e-01 
+ 7.928000000000e-10 -3.833551733065e-01 
+ 8.028000000000e-10 -5.332328436976e-01 
+ 8.128000000000e-10 -6.239725200032e-01 
+ 8.228000000000e-10 -7.092452956008e-01 
+ 8.328000000000e-10 -7.788891439389e-01 
+ 8.428000000000e-10 -7.989331916474e-01 
+ 8.528000000000e-10 -7.331340451631e-01 
+ 8.628000000000e-10 -5.312350772815e-01 
+ 8.728000000000e-10 -2.065433053799e-01 
+ 8.828000000000e-10  1.291679984852e-01 
+ 8.928000000000e-10  3.833797175156e-01 
+ 9.028000000000e-10  5.332088978421e-01 
+ 9.128000000000e-10  6.239966795455e-01 
+ 9.228000000000e-10  7.092206518532e-01 
+ 9.328000000000e-10  7.789132522577e-01 
+ 9.428000000000e-10  7.989096829455e-01 
+ 9.528000000000e-10  7.331579091452e-01 
+ 9.628000000000e-10  5.312112407565e-01 
+ 9.728000000000e-10  2.065672983353e-01 
+ 9.828000000000e-10 -1.291898675297e-01 
+ 9.928000000000e-10 -3.833583124064e-01 
+ 1.000000000000e-09 -4.991705375338e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/conditions.yaml
new file mode 100644
index 00000000..9d15c663
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 24
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_24
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb.sch
new file mode 100644
index 00000000..25cfc5da
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb_25.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb_25.data
new file mode 100644
index 00000000..39c04d30
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_core_tb_25.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.368449571564e-01 
+ 1.728000000000e-10  2.154696494615e-01 
+ 1.828000000000e-10 -1.180750667507e-01 
+ 1.928000000000e-10 -3.694801437498e-01 
+ 2.028000000000e-10 -5.157339685643e-01 
+ 2.128000000000e-10 -6.051803608378e-01 
+ 2.228000000000e-10 -6.923688047900e-01 
+ 2.328000000000e-10 -7.627278516708e-01 
+ 2.428000000000e-10 -7.836324050269e-01 
+ 2.528000000000e-10 -7.217390774868e-01 
+ 2.628000000000e-10 -5.258344598842e-01 
+ 2.728000000000e-10 -2.060622799160e-01 
+ 2.828000000000e-10  1.253068918672e-01 
+ 2.928000000000e-10  3.754763463876e-01 
+ 3.028000000000e-10  5.204513706872e-01 
+ 3.128000000000e-10  6.088547126517e-01 
+ 3.228000000000e-10  6.948747427610e-01 
+ 3.328000000000e-10  7.643967320598e-01 
+ 3.428000000000e-10  7.844541546789e-01 
+ 3.528000000000e-10  7.222905371020e-01 
+ 3.628000000000e-10  5.261436989659e-01 
+ 3.728000000000e-10  2.064244494061e-01 
+ 3.828000000000e-10 -1.251087630482e-01 
+ 3.928000000000e-10 -3.752230316774e-01 
+ 4.028000000000e-10 -5.203274407129e-01 
+ 4.128000000000e-10 -6.086807930540e-01 
+ 4.228000000000e-10 -6.948278459755e-01 
+ 4.328000000000e-10 -7.642927444658e-01 
+ 4.428000000000e-10 -7.844689558048e-01 
+ 4.528000000000e-10 -7.222270537973e-01 
+ 4.628000000000e-10 -5.261810188038e-01 
+ 4.728000000000e-10 -2.063649367923e-01 
+ 4.828000000000e-10  1.250740150254e-01 
+ 4.928000000000e-10  3.752740624702e-01 
+ 5.028000000000e-10  5.202917067072e-01 
+ 5.128000000000e-10  6.087280474834e-01 
+ 5.228000000000e-10  6.947875493975e-01 
+ 5.328000000000e-10  7.643381446772e-01 
+ 5.428000000000e-10  7.844278436925e-01 
+ 5.528000000000e-10  7.222707134126e-01 
+ 5.628000000000e-10  5.261386731045e-01 
+ 5.728000000000e-10  2.064078101390e-01 
+ 5.828000000000e-10 -1.251125509614e-01 
+ 5.928000000000e-10 -3.752362786491e-01 
+ 6.028000000000e-10 -5.203279553884e-01 
+ 6.128000000000e-10 -6.086920089480e-01 
+ 6.228000000000e-10 -6.948246280643e-01 
+ 6.328000000000e-10 -7.643013046090e-01 
+ 6.428000000000e-10 -7.844633201903e-01 
+ 6.528000000000e-10 -7.222336042293e-01 
+ 6.628000000000e-10 -5.261766512068e-01 
+ 6.728000000000e-10 -2.063691829929e-01 
+ 6.828000000000e-10  1.250784814444e-01 
+ 6.928000000000e-10  3.752708432251e-01 
+ 7.028000000000e-10  5.202949527958e-01 
+ 7.128000000000e-10  6.087256874770e-01 
+ 7.228000000000e-10  6.947904319095e-01 
+ 7.328000000000e-10  7.643352365607e-01 
+ 7.428000000000e-10  7.844306677783e-01 
+ 7.528000000000e-10  7.222672114429e-01 
+ 7.628000000000e-10  5.261433781551e-01 
+ 7.728000000000e-10  2.064029029490e-01 
+ 7.828000000000e-10 -1.251089390610e-01 
+ 7.928000000000e-10 -3.752408867518e-01 
+ 8.028000000000e-10 -5.203238706374e-01 
+ 8.128000000000e-10 -6.086968714396e-01 
+ 8.228000000000e-10 -6.948200705245e-01 
+ 8.328000000000e-10 -7.643060605343e-01 
+ 8.428000000000e-10 -7.844586734539e-01 
+ 8.528000000000e-10 -7.222379683755e-01 
+ 8.628000000000e-10 -5.261730442965e-01 
+ 8.728000000000e-10 -2.063725681788e-01 
+ 8.828000000000e-10  1.250820910423e-01 
+ 8.928000000000e-10  3.752680406761e-01 
+ 9.028000000000e-10  5.202978581562e-01 
+ 9.128000000000e-10  6.087233210610e-01 
+ 9.228000000000e-10  6.947932359489e-01 
+ 9.328000000000e-10  7.643326365950e-01 
+ 9.428000000000e-10  7.844331791786e-01 
+ 9.528000000000e-10  7.222642751837e-01 
+ 9.628000000000e-10  5.261469613157e-01 
+ 9.728000000000e-10  2.063991803079e-01 
+ 9.828000000000e-10 -1.251060220915e-01 
+ 9.928000000000e-10 -3.752443155305e-01 
+ 1.000000000000e-09 -4.875704709340e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/conditions.yaml
new file mode 100644
index 00000000..ed90bd87
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 25
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_25
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb.sch
new file mode 100644
index 00000000..1ca4391f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb_26.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb_26.data
new file mode 100644
index 00000000..894f4c67
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_core_tb_26.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.436948212736e-01 
+ 1.728000000000e-10  2.205877879634e-01 
+ 1.828000000000e-10 -1.163348151974e-01 
+ 1.928000000000e-10 -3.771420921807e-01 
+ 2.028000000000e-10 -5.370108455130e-01 
+ 2.128000000000e-10 -6.331888427572e-01 
+ 2.228000000000e-10 -7.164762236683e-01 
+ 2.328000000000e-10 -7.851286946760e-01 
+ 2.428000000000e-10 -8.059531868761e-01 
+ 2.528000000000e-10 -7.384564800459e-01 
+ 2.628000000000e-10 -5.363144999221e-01 
+ 2.728000000000e-10 -2.144637665285e-01 
+ 2.828000000000e-10  1.212929793685e-01 
+ 2.928000000000e-10  3.815418180812e-01 
+ 3.028000000000e-10  5.406606883043e-01 
+ 3.128000000000e-10  6.361475176918e-01 
+ 3.228000000000e-10  7.185360719894e-01 
+ 3.328000000000e-10  7.865091736067e-01 
+ 3.428000000000e-10  8.065713749450e-01 
+ 3.528000000000e-10  7.387921596039e-01 
+ 3.628000000000e-10  5.364259512539e-01 
+ 3.728000000000e-10  2.146317863835e-01 
+ 3.828000000000e-10 -1.212295238309e-01 
+ 3.928000000000e-10 -3.814110096077e-01 
+ 4.028000000000e-10 -5.406166203788e-01 
+ 4.128000000000e-10 -6.360467438854e-01 
+ 4.228000000000e-10 -7.185257686739e-01 
+ 4.328000000000e-10 -7.864422304189e-01 
+ 4.428000000000e-10 -8.065937411296e-01 
+ 4.528000000000e-10 -7.387487319623e-01 
+ 4.628000000000e-10 -5.364619855530e-01 
+ 4.728000000000e-10 -2.145913861363e-01 
+ 4.828000000000e-10  1.211959412322e-01 
+ 4.928000000000e-10  3.814481551476e-01 
+ 5.028000000000e-10  5.405833390120e-01 
+ 5.128000000000e-10  6.360831449777e-01 
+ 5.228000000000e-10  7.184907253890e-01 
+ 5.328000000000e-10  7.864786648334e-01 
+ 5.428000000000e-10  8.065585198321e-01 
+ 5.528000000000e-10  7.387840006966e-01 
+ 5.628000000000e-10  5.364270346085e-01 
+ 5.728000000000e-10  2.146260338484e-01 
+ 5.828000000000e-10 -1.212277001077e-01 
+ 5.928000000000e-10 -3.814182410321e-01 
+ 6.028000000000e-10 -5.406130595607e-01 
+ 6.128000000000e-10 -6.360540210765e-01 
+ 6.228000000000e-10 -7.185209180994e-01 
+ 6.328000000000e-10 -7.864492678158e-01 
+ 6.428000000000e-10 -8.065874846616e-01 
+ 6.528000000000e-10 -7.387544794760e-01 
+ 6.628000000000e-10 -5.364572547805e-01 
+ 6.728000000000e-10 -2.145959871001e-01 
+ 6.828000000000e-10  1.211997934696e-01 
+ 6.928000000000e-10  3.814456726213e-01 
+ 7.028000000000e-10  5.405857946323e-01 
+ 7.128000000000e-10  6.360813265814e-01 
+ 7.228000000000e-10  7.184929266665e-01 
+ 7.328000000000e-10  7.864767243186e-01 
+ 7.428000000000e-10  8.065604357181e-01 
+ 7.528000000000e-10  7.387815158779e-01 
+ 7.628000000000e-10  5.364303644926e-01 
+ 7.728000000000e-10  2.146228844142e-01 
+ 7.828000000000e-10 -1.212245339809e-01 
+ 7.928000000000e-10 -3.814220075435e-01 
+ 8.028000000000e-10 -5.406092538148e-01 
+ 8.128000000000e-10 -6.360581238583e-01 
+ 8.228000000000e-10 -7.185168954112e-01 
+ 8.328000000000e-10 -7.864535273883e-01 
+ 8.428000000000e-10 -8.065831328643e-01 
+ 8.528000000000e-10 -7.387583532284e-01 
+ 8.628000000000e-10 -5.364538735708e-01 
+ 8.728000000000e-10 -2.145992968151e-01 
+ 8.828000000000e-10  1.212027591883e-01 
+ 8.928000000000e-10  3.814433789143e-01 
+ 9.028000000000e-10  5.405880431190e-01 
+ 9.128000000000e-10  6.360793794818e-01 
+ 9.228000000000e-10  7.184951630330e-01 
+ 9.328000000000e-10  7.864747526663e-01 
+ 9.428000000000e-10  8.065622905723e-01 
+ 9.528000000000e-10  7.387792872630e-01 
+ 9.628000000000e-10  5.364330391099e-01 
+ 9.728000000000e-10  2.146202349236e-01 
+ 9.828000000000e-10 -1.212220310216e-01 
+ 9.928000000000e-10 -3.814247853449e-01 
+ 1.000000000000e-09 -5.040490090913e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/conditions.yaml
new file mode 100644
index 00000000..9486e63a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 26
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/run_26
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/simulation_summary.csv
new file mode 100644
index 00000000..2f5f947b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/simulation_summary.csv
@@ -0,0 +1,28 @@
+run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing
+run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.952e-01, -6.044e-02, 0.182, …]",4.722e+09,0.709,1.418
+run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.648e-01, -3.672e-02, 0.198, …]",4.722e+09,0.693,1.386
+run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.227e-01, -8.540e-02, 0.161, …]",4.722e+09,0.722,1.444
+run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.752e-01, -5.371e-02, 0.179, …]",4.722e+09,0.692,1.383
+run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.482e-01, -3.259e-02, 0.193, …]",4.722e+09,0.672,1.345
+run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.027e-01, -8.046e-02, 0.156, …]",4.722e+09,0.706,1.412
+run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.659e-01, -5.659e-02, 0.167, …]",4.722e+09,0.669,1.338
+run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.411e-01, -3.745e-02, 0.179, …]",4.722e+09,0.648,1.295
+run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.916e-01, -8.207e-02, 0.144, …]",4.722e+09,0.685,1.371
+run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.397e-01, -2.046e-01, 0.131, …]",4.722e+09,0.807,1.614
+run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.293e-01, -2.034e-01, 0.125, …]",4.722e+09,0.789,1.577
+run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.474e-01, -2.088e-01, 0.131, …]",4.722e+09,0.819,1.638
+run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.050e-01, -1.958e-01, 0.120, …]",4.722e+09,0.771,1.543
+run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.935e-01, -1.929e-01, 0.116, …]",4.722e+09,0.753,1.505
+run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.133e-01, -2.032e-01, 0.114, …]",4.722e+09,0.783,1.566
+run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.765e-01, -1.934e-01, 0.103, …]",4.722e+09,0.743,1.486
+run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.643e-01, -1.890e-01, 0.101, …]",4.722e+09,0.725,1.450
+run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.853e-01, -2.024e-01, 9.500e-02, …]",4.722e+09,0.755,1.510
+run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.575, 0.203, -1.640e-01, …]",4.722e+09,0.851,1.702
+run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.571, 0.205, -1.568e-01, …]",4.722e+09,0.836,1.672
+run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.579, 0.208, -1.623e-01, …]",4.722e+09,0.860,1.720
+run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.557, 0.208, -1.460e-01, …]",4.722e+09,0.826,1.653
+run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.554, 0.209, -1.400e-01, …]",4.722e+09,0.812,1.624
+run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.561, 0.214, -1.407e-01, …]",4.722e+09,0.834,1.669
+run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.541, 0.214, -1.231e-01, …]",4.722e+09,0.799,1.598
+run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.537, 0.215, -1.181e-01, …]",4.722e+09,0.784,1.569
+run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.544, 0.221, -1.163e-01, …]",4.722e+09,0.807,1.613
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/simulation_summary.md
new file mode 100644
index 00000000..6401031e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/simulation_summary.md
@@ -0,0 +1,31 @@
+# Simulation Summary for CML divider frequency response
+
+| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing |
+| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: |
+| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.952e-01, -6.044e-02, 0.182, …] | 4.722e+09 | 0.709 | 1.418 |
+| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.648e-01, -3.672e-02, 0.198, …] | 4.722e+09 | 0.693 | 1.386 |
+| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.227e-01, -8.540e-02, 0.161, …] | 4.722e+09 | 0.722 | 1.444 |
+| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.752e-01, -5.371e-02, 0.179, …] | 4.722e+09 | 0.692 | 1.383 |
+| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.482e-01, -3.259e-02, 0.193, …] | 4.722e+09 | 0.672 | 1.345 |
+| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.027e-01, -8.046e-02, 0.156, …] | 4.722e+09 | 0.706 | 1.412 |
+| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.659e-01, -5.659e-02, 0.167, …] | 4.722e+09 | 0.669 | 1.338 |
+| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.411e-01, -3.745e-02, 0.179, …] | 4.722e+09 | 0.648 | 1.295 |
+| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.916e-01, -8.207e-02, 0.144, …] | 4.722e+09 | 0.685 | 1.371 |
+| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.397e-01, -2.046e-01, 0.131, …] | 4.722e+09 | 0.807 | 1.614 |
+| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.293e-01, -2.034e-01, 0.125, …] | 4.722e+09 | 0.789 | 1.577 |
+| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.474e-01, -2.088e-01, 0.131, …] | 4.722e+09 | 0.819 | 1.638 |
+| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.050e-01, -1.958e-01, 0.120, …] | 4.722e+09 | 0.771 | 1.543 |
+| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.935e-01, -1.929e-01, 0.116, …] | 4.722e+09 | 0.753 | 1.505 |
+| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.133e-01, -2.032e-01, 0.114, …] | 4.722e+09 | 0.783 | 1.566 |
+| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.765e-01, -1.934e-01, 0.103, …] | 4.722e+09 | 0.743 | 1.486 |
+| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.643e-01, -1.890e-01, 0.101, …] | 4.722e+09 | 0.725 | 1.450 |
+| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.853e-01, -2.024e-01, 9.500e-02, …] | 4.722e+09 | 0.755 | 1.510 |
+| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.575, 0.203, -1.640e-01, …] | 4.722e+09 | 0.851 | 1.702 |
+| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.571, 0.205, -1.568e-01, …] | 4.722e+09 | 0.836 | 1.672 |
+| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.579, 0.208, -1.623e-01, …] | 4.722e+09 | 0.860 | 1.720 |
+| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.557, 0.208, -1.460e-01, …] | 4.722e+09 | 0.826 | 1.653 |
+| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.554, 0.209, -1.400e-01, …] | 4.722e+09 | 0.812 | 1.624 |
+| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.561, 0.214, -1.407e-01, …] | 4.722e+09 | 0.834 | 1.669 |
+| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.541, 0.214, -1.231e-01, …] | 4.722e+09 | 0.799 | 1.598 |
+| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.537, 0.215, -1.181e-01, …] | 4.722e+09 | 0.784 | 1.569 |
+| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.544, 0.221, -1.163e-01, …] | 4.722e+09 | 0.807 | 1.613 |
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/vo_diff_vs_time.png
new file mode 100644
index 00000000..64d1b808
Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/parameters/ac_params/vo_diff_vs_time.png differ
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/summary.md
new file mode 100644
index 00000000..a11c2c65
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-38-33/summary.md
@@ -0,0 +1,11 @@
+
+# CACE Summary for CML_divider
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |  4.722 GHz |      5.0 GHz |  4.722 GHz |      5.2 GHz |  4.722 GHz |   Pass ✅    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |    0.648 V |        0.4 V |    0.771 V |        0.6 V |    0.860 V |   Fail ❌    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |    1.295 V |        0.8 V |    1.543 V |        1.2 V |    1.720 V |   Fail ❌    |
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/CML_core_tb.sch
new file mode 100644
index 00000000..48f6f0bb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb.sch
new file mode 100644
index 00000000..3c8ccdf1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb_0.data
new file mode 100644
index 00000000..6e5c755c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_core_tb_0.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.952325246460e-01 
+ 1.728000000000e-10 -6.043942197180e-02 
+ 1.828000000000e-10  1.817064006720e-01 
+ 1.928000000000e-10  3.985392356515e-01 
+ 2.028000000000e-10  5.562505249699e-01 
+ 2.128000000000e-10  6.572874178466e-01 
+ 2.228000000000e-10  7.087352858161e-01 
+ 2.328000000000e-10  7.029522511861e-01 
+ 2.428000000000e-10  6.344368312078e-01 
+ 2.528000000000e-10  5.013241237787e-01 
+ 2.628000000000e-10  3.030080742176e-01 
+ 2.728000000000e-10  6.578821975767e-02 
+ 2.828000000000e-10 -1.781586778972e-01 
+ 2.928000000000e-10 -3.964040373443e-01 
+ 3.028000000000e-10 -5.555461653242e-01 
+ 3.128000000000e-10 -6.571022283471e-01 
+ 3.228000000000e-10 -7.092808909864e-01 
+ 3.328000000000e-10 -7.040843150938e-01 
+ 3.428000000000e-10 -6.362469325195e-01 
+ 3.528000000000e-10 -5.032364212786e-01 
+ 3.628000000000e-10 -3.051350358226e-01 
+ 3.728000000000e-10 -6.762904380973e-02 
+ 3.828000000000e-10  1.763878132349e-01 
+ 3.928000000000e-10  3.951284969670e-01 
+ 4.028000000000e-10  5.545978983505e-01 
+ 4.128000000000e-10  6.566315830069e-01 
+ 4.228000000000e-10  7.089962487465e-01 
+ 4.328000000000e-10  7.042633111532e-01 
+ 4.428000000000e-10  6.365365170049e-01 
+ 4.528000000000e-10  5.037912579488e-01 
+ 4.628000000000e-10  3.056253251435e-01 
+ 4.728000000000e-10  6.823087043489e-02 
+ 4.828000000000e-10 -1.759620590786e-01 
+ 4.928000000000e-10 -3.946766675460e-01 
+ 5.028000000000e-10 -5.543918551335e-01 
+ 5.128000000000e-10 -6.564106038653e-01 
+ 5.228000000000e-10 -7.089804674794e-01 
+ 5.328000000000e-10 -7.042284637667e-01 
+ 5.428000000000e-10 -6.366831677063e-01 
+ 5.528000000000e-10 -5.038654128054e-01 
+ 5.628000000000e-10 -3.058301627321e-01 
+ 5.728000000000e-10 -6.832081314378e-02 
+ 5.828000000000e-10  1.757744687450e-01 
+ 5.928000000000e-10  3.946207346164e-01 
+ 6.028000000000e-10  5.542681653143e-01 
+ 6.128000000000e-10  6.564162326939e-01 
+ 6.228000000000e-10  7.089102158365e-01 
+ 6.328000000000e-10  7.042850183822e-01 
+ 6.428000000000e-10  6.366586213363e-01 
+ 6.528000000000e-10  5.039505543903e-01 
+ 6.628000000000e-10  3.058219717524e-01 
+ 6.728000000000e-10  6.840961740524e-02 
+ 6.828000000000e-10 -1.757862033444e-01 
+ 6.928000000000e-10 -3.945467987447e-01 
+ 7.028000000000e-10 -5.542929102277e-01 
+ 7.128000000000e-10 -6.563603422698e-01 
+ 7.228000000000e-10 -7.089481650220e-01 
+ 7.328000000000e-10 -7.042424683005e-01 
+ 7.428000000000e-10 -6.367078290897e-01 
+ 7.528000000000e-10 -5.039165471509e-01 
+ 7.628000000000e-10 -3.058753018579e-01 
+ 7.728000000000e-10 -6.837707225292e-02 
+ 7.828000000000e-10  1.757345833407e-01 
+ 7.928000000000e-10  3.945785215449e-01 
+ 8.028000000000e-10  5.542482652542e-01 
+ 8.128000000000e-10  6.563959408481e-01 
+ 8.228000000000e-10  7.089082113076e-01 
+ 8.328000000000e-10  7.042817797830e-01 
+ 8.428000000000e-10  6.366719399828e-01 
+ 8.528000000000e-10  5.039573608246e-01 
+ 8.628000000000e-10  3.058408732486e-01 
+ 8.728000000000e-10  6.841772818469e-02 
+ 8.828000000000e-10 -1.757686495942e-01 
+ 8.928000000000e-10 -3.945419964750e-01 
+ 9.028000000000e-10 -5.542809328797e-01 
+ 9.128000000000e-10 -6.563614885531e-01 
+ 9.228000000000e-10 -7.089411806967e-01 
+ 9.328000000000e-10 -7.042479976407e-01 
+ 9.428000000000e-10 -6.367051444468e-01 
+ 9.528000000000e-10 -5.039245834310e-01 
+ 9.628000000000e-10 -3.058742220339e-01 
+ 9.728000000000e-10 -6.838526492007e-02 
+ 9.828000000000e-10  1.757358039920e-01 
+ 9.928000000000e-10  3.945718167364e-01 
+ 1.000000000000e-09  5.155910006549e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/conditions.yaml
new file mode 100644
index 00000000..61941c26
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 0
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_00
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb.sch
new file mode 100644
index 00000000..17574ff5
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb_1.data
new file mode 100644
index 00000000..94a2849c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_core_tb_1.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.647956442563e-01 
+ 1.728000000000e-10 -3.672466403620e-02 
+ 1.828000000000e-10  1.978055322165e-01 
+ 1.928000000000e-10  4.056017943518e-01 
+ 2.028000000000e-10  5.547344088879e-01 
+ 2.128000000000e-10  6.487490848065e-01 
+ 2.228000000000e-10  6.923653634957e-01 
+ 2.328000000000e-10  6.780886353961e-01 
+ 2.428000000000e-10  6.039598047192e-01 
+ 2.528000000000e-10  4.698168410475e-01 
+ 2.628000000000e-10  2.751260896566e-01 
+ 2.728000000000e-10  4.430157580526e-02 
+ 2.828000000000e-10 -1.925038311834e-01 
+ 2.928000000000e-10 -4.023301580756e-01 
+ 3.028000000000e-10 -5.533152551340e-01 
+ 3.128000000000e-10 -6.481954476962e-01 
+ 3.228000000000e-10 -6.930655672739e-01 
+ 3.328000000000e-10 -6.800540209913e-01 
+ 3.428000000000e-10 -6.070129146880e-01 
+ 3.528000000000e-10 -4.732295235615e-01 
+ 3.628000000000e-10 -2.788311309623e-01 
+ 3.728000000000e-10 -4.769207273318e-02 
+ 3.828000000000e-10  1.893739393663e-01 
+ 3.928000000000e-10  3.999895682405e-01 
+ 4.028000000000e-10  5.516914161753e-01 
+ 4.128000000000e-10  6.473194453459e-01 
+ 4.228000000000e-10  6.926967113745e-01 
+ 4.328000000000e-10  6.804409619078e-01 
+ 4.428000000000e-10  6.077344291363e-01 
+ 4.528000000000e-10  4.743209278754e-01 
+ 4.628000000000e-10  2.799315218230e-01 
+ 4.728000000000e-10  4.887682675205e-02 
+ 4.828000000000e-10 -1.884058832182e-01 
+ 4.928000000000e-10 -3.991237321070e-01 
+ 5.028000000000e-10 -5.511979674959e-01 
+ 5.128000000000e-10 -6.469402879887e-01 
+ 5.228000000000e-10 -6.926225993557e-01 
+ 5.328000000000e-10 -6.804805060919e-01 
+ 5.428000000000e-10 -6.080204415279e-01 
+ 5.528000000000e-10 -4.745961817340e-01 
+ 5.628000000000e-10 -2.803459413605e-01 
+ 5.728000000000e-10 -4.918721233066e-02 
+ 5.828000000000e-10  1.880320213273e-01 
+ 5.928000000000e-10  3.989072784961e-01 
+ 6.028000000000e-10  5.509784832100e-01 
+ 6.128000000000e-10  6.468776696433e-01 
+ 6.228000000000e-10  6.925382949500e-01 
+ 6.328000000000e-10  6.805520167761e-01 
+ 6.428000000000e-10  6.080522625696e-01 
+ 6.528000000000e-10  4.747422384222e-01 
+ 6.628000000000e-10  2.804194075907e-01 
+ 6.728000000000e-10  4.934414267879e-02 
+ 6.828000000000e-10 -1.879699706397e-01 
+ 6.928000000000e-10 -3.987854446736e-01 
+ 7.028000000000e-10 -5.509613139230e-01 
+ 7.128000000000e-10 -6.468062697707e-01 
+ 7.228000000000e-10 -6.925630874809e-01 
+ 7.328000000000e-10 -6.805223964692e-01 
+ 7.428000000000e-10 -6.081132322697e-01 
+ 7.528000000000e-10 -4.747366406660e-01 
+ 7.628000000000e-10 -2.804933490724e-01 
+ 7.728000000000e-10 -4.934235519722e-02 
+ 7.828000000000e-10  1.879006367827e-01 
+ 7.928000000000e-10  3.987938070562e-01 
+ 8.028000000000e-10  5.509093463144e-01 
+ 8.128000000000e-10  6.468293959909e-01 
+ 8.228000000000e-10  6.925252291894e-01 
+ 8.328000000000e-10  6.805590879185e-01 
+ 8.428000000000e-10  6.080875904937e-01 
+ 8.528000000000e-10  4.747803907956e-01 
+ 8.628000000000e-10  2.804721530083e-01 
+ 8.728000000000e-10  4.938687520288e-02 
+ 8.828000000000e-10 -1.879222775604e-01 
+ 8.928000000000e-10 -3.987554695640e-01 
+ 9.028000000000e-10 -5.509333914335e-01 
+ 9.128000000000e-10 -6.467969990881e-01 
+ 9.228000000000e-10 -6.925530415231e-01 
+ 9.328000000000e-10 -6.805304150604e-01 
+ 9.428000000000e-10 -6.081187600045e-01 
+ 9.528000000000e-10 -4.747542418837e-01 
+ 9.628000000000e-10 -2.805045225794e-01 
+ 9.728000000000e-10 -4.936125388638e-02 
+ 9.828000000000e-10  1.878908530872e-01 
+ 9.928000000000e-10  3.987795364060e-01 
+ 1.000000000000e-09  5.142017254263e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/conditions.yaml
new file mode 100644
index 00000000..eee3a944
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 1
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_01
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb.sch
new file mode 100644
index 00000000..e5054b24
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb_2.data
new file mode 100644
index 00000000..cdbb156b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_core_tb_2.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.226907107526e-01 
+ 1.728000000000e-10 -8.539968284410e-02 
+ 1.828000000000e-10  1.614480909662e-01 
+ 1.928000000000e-10  3.869191924745e-01 
+ 2.028000000000e-10  5.540483396157e-01 
+ 2.128000000000e-10  6.620167995175e-01 
+ 2.228000000000e-10  7.202634748901e-01 
+ 2.328000000000e-10  7.212523007105e-01 
+ 2.428000000000e-10  6.566979396260e-01 
+ 2.528000000000e-10  5.250303609426e-01 
+ 2.628000000000e-10  3.265092852166e-01 
+ 2.728000000000e-10  8.707604756770e-02 
+ 2.828000000000e-10 -1.611600424348e-01 
+ 2.928000000000e-10 -3.873238626333e-01 
+ 3.028000000000e-10 -5.550746884823e-01 
+ 3.128000000000e-10 -6.629366269634e-01 
+ 3.228000000000e-10 -7.212894794449e-01 
+ 3.328000000000e-10 -7.220878341254e-01 
+ 3.428000000000e-10 -6.576651735802e-01 
+ 3.528000000000e-10 -5.257535323793e-01 
+ 3.628000000000e-10 -3.273054874384e-01 
+ 3.728000000000e-10 -8.759901468451e-02 
+ 3.828000000000e-10  1.605580394287e-01 
+ 3.928000000000e-10  3.869863823107e-01 
+ 4.028000000000e-10  5.547303069787e-01 
+ 4.128000000000e-10  6.628461833305e-01 
+ 4.228000000000e-10  7.211466820779e-01 
+ 4.328000000000e-10  7.221995653822e-01 
+ 4.428000000000e-10  6.577128147927e-01 
+ 4.528000000000e-10  5.259884868760e-01 
+ 4.628000000000e-10  3.274163471898e-01 
+ 4.728000000000e-10  8.784541550780e-02 
+ 4.828000000000e-10 -1.604682108624e-01 
+ 4.928000000000e-10 -3.867888973241e-01 
+ 5.028000000000e-10 -5.547066546217e-01 
+ 5.128000000000e-10 -6.627253094524e-01 
+ 5.228000000000e-10 -7.211826888209e-01 
+ 5.328000000000e-10 -7.221369141817e-01 
+ 5.428000000000e-10 -6.577994031943e-01 
+ 5.528000000000e-10 -5.259620192587e-01 
+ 5.628000000000e-10 -3.275201865204e-01 
+ 5.728000000000e-10 -8.782404636233e-02 
+ 5.828000000000e-10  1.603689538405e-01 
+ 5.928000000000e-10  3.868153343854e-01 
+ 6.028000000000e-10  5.546284247412e-01 
+ 6.128000000000e-10  6.627691182366e-01 
+ 6.228000000000e-10  7.211205707397e-01 
+ 6.328000000000e-10  7.221945096033e-01 
+ 6.428000000000e-10  6.577508134366e-01 
+ 6.528000000000e-10  5.260261908485e-01 
+ 6.628000000000e-10  3.274760111912e-01 
+ 6.728000000000e-10  8.788851273295e-02 
+ 6.828000000000e-10 -1.604138329037e-01 
+ 6.928000000000e-10 -3.867579820075e-01 
+ 7.028000000000e-10 -5.546733587088e-01 
+ 7.128000000000e-10 -6.627166397254e-01 
+ 7.228000000000e-10 -7.211676696649e-01 
+ 7.328000000000e-10 -7.221448613305e-01 
+ 7.428000000000e-10 -6.577993970261e-01 
+ 7.528000000000e-10 -5.259796511606e-01 
+ 7.628000000000e-10 -3.275252420812e-01 
+ 7.728000000000e-10 -8.784270745333e-02 
+ 7.828000000000e-10  1.603648729372e-01 
+ 7.928000000000e-10  3.868003178892e-01 
+ 8.028000000000e-10  5.546284703905e-01 
+ 8.128000000000e-10  6.627594909397e-01 
+ 8.228000000000e-10  7.211247368625e-01 
+ 8.328000000000e-10  7.221884517678e-01 
+ 8.428000000000e-10  6.577581123739e-01 
+ 8.528000000000e-10  5.260226393584e-01 
+ 8.628000000000e-10  3.274844581735e-01 
+ 8.728000000000e-10  8.788515759553e-02 
+ 8.828000000000e-10 -1.604054537172e-01 
+ 8.928000000000e-10 -3.867616376768e-01 
+ 9.028000000000e-10 -5.546662826942e-01 
+ 9.128000000000e-10 -6.627215467888e-01 
+ 9.228000000000e-10 -7.211618152183e-01 
+ 9.328000000000e-10 -7.221504122635e-01 
+ 9.428000000000e-10 -6.577943183983e-01 
+ 9.528000000000e-10 -5.259856282734e-01 
+ 9.628000000000e-10 -3.275204867996e-01 
+ 9.728000000000e-10 -8.784851998896e-02 
+ 9.828000000000e-10  1.603694682536e-01 
+ 9.928000000000e-10  3.867951846118e-01 
+ 1.000000000000e-09  5.139507493642e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/conditions.yaml
new file mode 100644
index 00000000..a71e07da
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 2
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_02
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb.sch
new file mode 100644
index 00000000..83f6cb3a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb_3.data
new file mode 100644
index 00000000..a5b707e1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_core_tb_3.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.752371518652e-01 
+ 1.728000000000e-10 -5.371376319542e-02 
+ 1.828000000000e-10  1.789877413053e-01 
+ 1.928000000000e-10  3.904548691103e-01 
+ 2.028000000000e-10  5.481842948229e-01 
+ 2.128000000000e-10  6.473880529986e-01 
+ 2.228000000000e-10  6.910106576952e-01 
+ 2.328000000000e-10  6.747515328639e-01 
+ 2.428000000000e-10  5.993982850131e-01 
+ 2.528000000000e-10  4.678235295331e-01 
+ 2.628000000000e-10  2.811940191144e-01 
+ 2.728000000000e-10  5.749892092429e-02 
+ 2.828000000000e-10 -1.768703468756e-01 
+ 2.928000000000e-10 -3.894327299011e-01 
+ 3.028000000000e-10 -5.481462871223e-01 
+ 3.128000000000e-10 -6.476233959034e-01 
+ 3.228000000000e-10 -6.918267741740e-01 
+ 3.328000000000e-10 -6.759891610513e-01 
+ 3.428000000000e-10 -6.011477081233e-01 
+ 3.528000000000e-10 -4.695436066175e-01 
+ 3.628000000000e-10 -2.830251877311e-01 
+ 3.728000000000e-10 -5.907673776650e-02 
+ 3.828000000000e-10  1.753349861707e-01 
+ 3.928000000000e-10  3.883274219019e-01 
+ 4.028000000000e-10  5.473035177189e-01 
+ 4.128000000000e-10  6.472356324664e-01 
+ 4.228000000000e-10  6.916308158427e-01 
+ 4.328000000000e-10  6.762268077787e-01 
+ 4.428000000000e-10  6.014684070962e-01 
+ 4.528000000000e-10  4.700895666681e-01 
+ 4.628000000000e-10  2.834862741746e-01 
+ 4.728000000000e-10  5.964855757083e-02 
+ 4.828000000000e-10 -1.749274761915e-01 
+ 4.928000000000e-10 -3.878897710558e-01 
+ 5.028000000000e-10 -5.470986037433e-01 
+ 5.128000000000e-10 -6.470272164409e-01 
+ 5.228000000000e-10 -6.916322065746e-01 
+ 5.328000000000e-10 -6.762158687864e-01 
+ 5.428000000000e-10 -6.016311330158e-01 
+ 5.528000000000e-10 -4.701782346337e-01 
+ 5.628000000000e-10 -2.836941639082e-01 
+ 5.728000000000e-10 -5.974768838544e-02 
+ 5.828000000000e-10  1.747352099095e-01 
+ 5.928000000000e-10  3.878245260251e-01 
+ 6.028000000000e-10  5.469715931678e-01 
+ 6.128000000000e-10  6.470284806517e-01 
+ 6.228000000000e-10  6.915679621080e-01 
+ 6.328000000000e-10  6.762768333485e-01 
+ 6.428000000000e-10  6.016163496453e-01 
+ 6.528000000000e-10  4.702674812943e-01 
+ 6.628000000000e-10  2.836938506434e-01 
+ 6.728000000000e-10  5.983990401354e-02 
+ 6.828000000000e-10 -1.747391664584e-01 
+ 6.928000000000e-10 -3.877472828580e-01 
+ 7.028000000000e-10 -5.469903889528e-01 
+ 7.128000000000e-10 -6.469730360721e-01 
+ 7.228000000000e-10 -6.916047287716e-01 
+ 7.328000000000e-10 -6.762386026180e-01 
+ 7.428000000000e-10 -6.016669907082e-01 
+ 7.528000000000e-10 -4.702390118128e-01 
+ 7.628000000000e-10 -2.837481181728e-01 
+ 7.728000000000e-10 -5.981248689037e-02 
+ 7.828000000000e-10  1.746867337354e-01 
+ 7.928000000000e-10  3.877749638679e-01 
+ 8.028000000000e-10  5.469462314077e-01 
+ 8.128000000000e-10  6.470055622974e-01 
+ 8.228000000000e-10  6.915665740520e-01 
+ 8.328000000000e-10  6.762766371031e-01 
+ 8.428000000000e-10  6.016337946720e-01 
+ 8.528000000000e-10  4.702787360349e-01 
+ 8.628000000000e-10  2.837166478210e-01 
+ 8.728000000000e-10  5.985233152723e-02 
+ 8.828000000000e-10 -1.747180248353e-01 
+ 8.928000000000e-10 -3.877389392165e-01 
+ 9.028000000000e-10 -5.469764940938e-01 
+ 9.128000000000e-10 -6.469724949526e-01 
+ 9.228000000000e-10 -6.915980610397e-01 
+ 9.328000000000e-10 -6.762447762615e-01 
+ 9.428000000000e-10 -6.016660865709e-01 
+ 9.528000000000e-10 -4.702484057793e-01 
+ 9.628000000000e-10 -2.837489236123e-01 
+ 9.728000000000e-10 -5.982216431619e-02 
+ 9.828000000000e-10  1.746862818107e-01 
+ 9.928000000000e-10  3.877670239311e-01 
+ 1.000000000000e-09  5.084292112944e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/conditions.yaml
new file mode 100644
index 00000000..d9659250
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 3
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_03
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb.sch
new file mode 100644
index 00000000..345ea94d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb_4.data
new file mode 100644
index 00000000..8dbaf881
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_core_tb_4.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.482257947455e-01 
+ 1.728000000000e-10 -3.259266550035e-02 
+ 1.828000000000e-10  1.930322087844e-01 
+ 1.928000000000e-10  3.960886599474e-01 
+ 2.028000000000e-10  5.450058997505e-01 
+ 2.128000000000e-10  6.360387116800e-01 
+ 2.228000000000e-10  6.712975422190e-01 
+ 2.328000000000e-10  6.474938983982e-01 
+ 2.428000000000e-10  5.679706274704e-01 
+ 2.528000000000e-10  4.364781736218e-01 
+ 2.628000000000e-10  2.536409133725e-01 
+ 2.728000000000e-10  3.555786929817e-02 
+ 2.828000000000e-10 -1.919150168478e-01 
+ 2.928000000000e-10 -3.960490843585e-01 
+ 3.028000000000e-10 -5.456465197220e-01 
+ 3.128000000000e-10 -6.367232933250e-01 
+ 3.228000000000e-10 -6.725166925877e-01 
+ 3.328000000000e-10 -6.491812984547e-01 
+ 3.428000000000e-10 -5.701612342484e-01 
+ 3.528000000000e-10 -4.386195239579e-01 
+ 3.628000000000e-10 -2.558666299298e-01 
+ 3.728000000000e-10 -3.750940439386e-02 
+ 3.828000000000e-10  1.900731677010e-01 
+ 3.928000000000e-10  3.947279065049e-01 
+ 4.028000000000e-10  5.446879536498e-01 
+ 4.128000000000e-10  6.362937598492e-01 
+ 4.228000000000e-10  6.723764816130e-01 
+ 4.328000000000e-10  6.495551727740e-01 
+ 4.428000000000e-10  5.706690754638e-01 
+ 4.528000000000e-10  4.393690386281e-01 
+ 4.628000000000e-10  2.565445890136e-01 
+ 4.728000000000e-10  3.828939038748e-02 
+ 4.828000000000e-10 -1.894747026650e-01 
+ 4.928000000000e-10 -3.941469427019e-01 
+ 5.028000000000e-10 -5.443881652157e-01 
+ 5.128000000000e-10 -6.360424686566e-01 
+ 5.228000000000e-10 -6.723795425302e-01 
+ 5.328000000000e-10 -6.495951074105e-01 
+ 5.428000000000e-10 -5.709049111673e-01 
+ 5.528000000000e-10 -4.395480856777e-01 
+ 5.628000000000e-10 -2.568451405700e-01 
+ 5.728000000000e-10 -3.848386295174e-02 
+ 5.828000000000e-10  1.891998017504e-01 
+ 5.928000000000e-10  3.940128253458e-01 
+ 6.028000000000e-10  5.442195759360e-01 
+ 6.128000000000e-10  6.360190076123e-01 
+ 6.228000000000e-10  6.723154692419e-01 
+ 6.328000000000e-10  6.496722035130e-01 
+ 6.428000000000e-10  5.709215560836e-01 
+ 6.528000000000e-10  4.396716365902e-01 
+ 6.628000000000e-10  2.568848555761e-01 
+ 6.728000000000e-10  3.861258812938e-02 
+ 6.828000000000e-10 -1.891673406027e-01 
+ 6.928000000000e-10 -3.939096487469e-01 
+ 7.028000000000e-10 -5.442185154541e-01 
+ 7.128000000000e-10 -6.359555029215e-01 
+ 7.228000000000e-10 -6.723494769467e-01 
+ 7.328000000000e-10 -6.496420384079e-01 
+ 7.428000000000e-10 -5.709822816025e-01 
+ 7.528000000000e-10 -4.396582995671e-01 
+ 7.628000000000e-10 -2.569529185106e-01 
+ 7.728000000000e-10 -3.860128053097e-02 
+ 7.828000000000e-10  1.891028165048e-01 
+ 7.928000000000e-10  3.939252197739e-01 
+ 8.028000000000e-10  5.441685861906e-01 
+ 8.128000000000e-10  6.359828023137e-01 
+ 8.228000000000e-10  6.723118712615e-01 
+ 8.328000000000e-10  6.496812709937e-01 
+ 8.428000000000e-10  5.709544657577e-01 
+ 8.528000000000e-10  4.397022527784e-01 
+ 8.628000000000e-10  2.569280980597e-01 
+ 8.728000000000e-10  3.864565597286e-02 
+ 8.828000000000e-10 -1.891278298806e-01 
+ 8.928000000000e-10 -3.938862165142e-01 
+ 9.028000000000e-10 -5.441949734698e-01 
+ 9.128000000000e-10 -6.359493781265e-01 
+ 9.228000000000e-10 -6.723420888760e-01 
+ 9.328000000000e-10 -6.496512561522e-01 
+ 9.428000000000e-10 -5.709874488604e-01 
+ 9.528000000000e-10 -4.396746422576e-01 
+ 9.628000000000e-10 -2.569616958772e-01 
+ 9.728000000000e-10 -3.861839939192e-02 
+ 9.828000000000e-10  1.890951489097e-01 
+ 9.928000000000e-10  3.939119089870e-01 
+ 1.000000000000e-09  5.081084039478e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/conditions.yaml
new file mode 100644
index 00000000..7fe81e1e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 4
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_04
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb.sch
new file mode 100644
index 00000000..7c161102
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb_5.data
new file mode 100644
index 00000000..72d71163
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_core_tb_5.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.026592886865e-01 
+ 1.728000000000e-10 -8.046058591213e-02 
+ 1.828000000000e-10  1.560684489845e-01 
+ 1.928000000000e-10  3.758215815324e-01 
+ 2.028000000000e-10  5.441825187720e-01 
+ 2.128000000000e-10  6.527787402061e-01 
+ 2.228000000000e-10  7.054162779080e-01 
+ 2.328000000000e-10  6.966940307878e-01 
+ 2.428000000000e-10  6.251719997267e-01 
+ 2.528000000000e-10  4.948986245243e-01 
+ 2.628000000000e-10  3.088338841037e-01 
+ 2.728000000000e-10  8.463582249819e-02 
+ 2.828000000000e-10 -1.534379373390e-01 
+ 2.928000000000e-10 -3.742382678981e-01 
+ 3.028000000000e-10 -5.437587344983e-01 
+ 3.128000000000e-10 -6.527795869025e-01 
+ 3.228000000000e-10 -7.060578401775e-01 
+ 3.328000000000e-10 -6.977288800308e-01 
+ 3.428000000000e-10 -6.267241220561e-01 
+ 3.528000000000e-10 -4.964034573067e-01 
+ 3.628000000000e-10 -3.104523257846e-01 
+ 3.728000000000e-10 -8.599843693100e-02 
+ 3.828000000000e-10  1.520614001089e-01 
+ 3.928000000000e-10  3.732327292359e-01 
+ 4.028000000000e-10  5.429530946109e-01 
+ 4.128000000000e-10  6.523997728799e-01 
+ 4.228000000000e-10  7.058202145507e-01 
+ 4.328000000000e-10  6.979022558405e-01 
+ 4.428000000000e-10  6.269588593419e-01 
+ 4.528000000000e-10  4.968624227466e-01 
+ 4.628000000000e-10  3.108132149603e-01 
+ 4.728000000000e-10  8.648038785746e-02 
+ 4.828000000000e-10 -1.517384677919e-01 
+ 4.928000000000e-10 -3.728474794484e-01 
+ 5.028000000000e-10 -5.427866011842e-01 
+ 5.128000000000e-10 -6.522022614009e-01 
+ 5.228000000000e-10 -7.058208822479e-01 
+ 5.328000000000e-10 -6.978651082200e-01 
+ 5.428000000000e-10 -6.270935668997e-01 
+ 5.528000000000e-10 -4.969096569281e-01 
+ 5.628000000000e-10 -3.109835748750e-01 
+ 5.728000000000e-10 -8.653572716924e-02 
+ 5.828000000000e-10  1.515778681972e-01 
+ 5.928000000000e-10  3.728127447205e-01 
+ 6.028000000000e-10  5.426739415091e-01 
+ 6.128000000000e-10  6.522162007318e-01 
+ 6.228000000000e-10  7.057544179932e-01 
+ 6.328000000000e-10  6.979224304337e-01 
+ 6.428000000000e-10  6.270641898671e-01 
+ 6.528000000000e-10  4.969874144680e-01 
+ 6.628000000000e-10  3.109648292365e-01 
+ 6.728000000000e-10  8.661535651254e-02 
+ 6.828000000000e-10 -1.515990397030e-01 
+ 6.928000000000e-10 -3.727433125293e-01 
+ 7.028000000000e-10 -5.427028559119e-01 
+ 7.128000000000e-10 -6.521615488134e-01 
+ 7.228000000000e-10 -7.057946841560e-01 
+ 7.328000000000e-10 -6.978790263426e-01 
+ 7.428000000000e-10 -6.271133848792e-01 
+ 7.528000000000e-10 -4.969513861012e-01 
+ 7.628000000000e-10 -3.110159233563e-01 
+ 7.728000000000e-10 -8.658006676818e-02 
+ 7.828000000000e-10  1.515487071721e-01 
+ 7.928000000000e-10  3.727772980737e-01 
+ 8.028000000000e-10  5.426589701450e-01 
+ 8.128000000000e-10  6.521979789832e-01 
+ 8.228000000000e-10  7.057547305503e-01 
+ 8.328000000000e-10  6.979187185021e-01 
+ 8.428000000000e-10  6.270767072939e-01 
+ 8.528000000000e-10  4.969913946096e-01 
+ 8.628000000000e-10  3.109805885282e-01 
+ 8.728000000000e-10  8.662004567696e-02 
+ 8.828000000000e-10 -1.515841004471e-01 
+ 8.928000000000e-10 -3.727405314049e-01 
+ 9.028000000000e-10 -5.426922302859e-01 
+ 9.128000000000e-10 -6.521632231968e-01 
+ 9.228000000000e-10 -7.057882763540e-01 
+ 9.328000000000e-10 -6.978845659833e-01 
+ 9.428000000000e-10 -6.271103709374e-01 
+ 9.528000000000e-10 -4.969587868574e-01 
+ 9.628000000000e-10 -3.110138943909e-01 
+ 9.728000000000e-10 -8.658760475646e-02 
+ 9.828000000000e-10  1.515508999036e-01 
+ 9.928000000000e-10  3.727707590510e-01 
+ 1.000000000000e-09  5.012730784879e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/conditions.yaml
new file mode 100644
index 00000000..9263549c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 5
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_05
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb.sch
new file mode 100644
index 00000000..371a05d0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb_6.data
new file mode 100644
index 00000000..2ac25b32
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_core_tb_6.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.658991355482e-01 
+ 1.728000000000e-10 -5.658971746101e-02 
+ 1.828000000000e-10  1.665652322471e-01 
+ 1.928000000000e-10  3.726189743475e-01 
+ 2.028000000000e-10  5.303705116758e-01 
+ 2.128000000000e-10  6.287796796090e-01 
+ 2.228000000000e-10  6.685380236864e-01 
+ 2.328000000000e-10  6.490234756137e-01 
+ 2.428000000000e-10  5.737092070140e-01 
+ 2.528000000000e-10  4.474825535463e-01 
+ 2.628000000000e-10  2.725242795062e-01 
+ 2.728000000000e-10  6.117177433707e-02 
+ 2.828000000000e-10 -1.637031734923e-01 
+ 2.928000000000e-10 -3.708935568747e-01 
+ 3.028000000000e-10 -5.297756369707e-01 
+ 3.128000000000e-10 -6.287017384995e-01 
+ 3.228000000000e-10 -6.693265533929e-01 
+ 3.328000000000e-10 -6.504570398323e-01 
+ 3.428000000000e-10 -5.758168078022e-01 
+ 3.528000000000e-10 -4.496242973413e-01 
+ 3.628000000000e-10 -2.747981275605e-01 
+ 3.728000000000e-10 -6.319393908833e-02 
+ 3.828000000000e-10  1.617439470913e-01 
+ 3.928000000000e-10  3.694169588634e-01 
+ 4.028000000000e-10  5.286499307585e-01 
+ 4.128000000000e-10  6.281722098808e-01 
+ 4.228000000000e-10  6.691184385543e-01 
+ 4.328000000000e-10  6.507901751637e-01 
+ 4.428000000000e-10  5.762974118946e-01 
+ 4.528000000000e-10  4.503608294114e-01 
+ 4.628000000000e-10  2.754522690623e-01 
+ 4.728000000000e-10  6.396306731359e-02 
+ 4.828000000000e-10 -1.611542650007e-01 
+ 4.928000000000e-10 -3.688169747432e-01 
+ 5.028000000000e-10 -5.283292872594e-01 
+ 5.128000000000e-10 -6.279003852563e-01 
+ 5.228000000000e-10 -6.691136918962e-01 
+ 5.328000000000e-10 -6.508124831570e-01 
+ 5.428000000000e-10 -5.765249280825e-01 
+ 5.528000000000e-10 -4.505225248069e-01 
+ 5.628000000000e-10 -2.757393848954e-01 
+ 5.728000000000e-10 -6.413835118523e-02 
+ 5.828000000000e-10  1.608879015274e-01 
+ 5.928000000000e-10  3.686909867212e-01 
+ 6.028000000000e-10  5.281558224884e-01 
+ 6.128000000000e-10  6.278785795680e-01 
+ 6.228000000000e-10  6.690442760911e-01 
+ 6.328000000000e-10  6.508870303825e-01 
+ 6.428000000000e-10  5.765321271449e-01 
+ 6.528000000000e-10  4.506407637839e-01 
+ 6.628000000000e-10  2.757670228304e-01 
+ 6.728000000000e-10  6.426080532693e-02 
+ 6.828000000000e-10 -1.608659404084e-01 
+ 6.928000000000e-10 -3.685888330346e-01 
+ 7.028000000000e-10 -5.281591419234e-01 
+ 7.128000000000e-10 -6.278127091451e-01 
+ 7.228000000000e-10 -6.690805910819e-01 
+ 7.328000000000e-10 -6.508520944992e-01 
+ 7.428000000000e-10 -5.765925476372e-01 
+ 7.528000000000e-10 -4.506215704207e-01 
+ 7.628000000000e-10 -2.758332595929e-01 
+ 7.728000000000e-10 -6.424327491403e-02 
+ 7.828000000000e-10  1.608024320318e-01 
+ 7.928000000000e-10  3.686091606456e-01 
+ 8.028000000000e-10  5.281080947303e-01 
+ 8.128000000000e-10  6.278426474070e-01 
+ 8.228000000000e-10  6.690409470235e-01 
+ 8.328000000000e-10  6.508923982303e-01 
+ 8.428000000000e-10  5.765614162070e-01 
+ 8.528000000000e-10  4.506656063053e-01 
+ 8.628000000000e-10  2.758047260180e-01 
+ 8.728000000000e-10  6.428762429922e-02 
+ 8.828000000000e-10 -1.608310872580e-01 
+ 8.928000000000e-10 -3.685690211775e-01 
+ 9.028000000000e-10 -5.281370864240e-01 
+ 9.128000000000e-10 -6.278075066251e-01 
+ 9.228000000000e-10 -6.690730291835e-01 
+ 9.328000000000e-10 -6.508603444096e-01 
+ 9.428000000000e-10 -5.765956636587e-01 
+ 9.528000000000e-10 -4.506359555730e-01 
+ 9.628000000000e-10 -2.758391852585e-01 
+ 9.728000000000e-10 -6.425829353036e-02 
+ 9.828000000000e-10  1.607973448132e-01 
+ 9.928000000000e-10  3.685968285070e-01 
+ 1.000000000000e-09  4.894958047088e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/conditions.yaml
new file mode 100644
index 00000000..999004cd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 6
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_06
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb.sch
new file mode 100644
index 00000000..10b8e80e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb_7.data
new file mode 100644
index 00000000..8cc8eec2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_core_tb_7.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.411371086013e-01 
+ 1.728000000000e-10 -3.745255924116e-02 
+ 1.828000000000e-10  1.789428987452e-01 
+ 1.928000000000e-10  3.769558934840e-01 
+ 2.028000000000e-10  5.255858783541e-01 
+ 2.128000000000e-10  6.150086513683e-01 
+ 2.228000000000e-10  6.463506095909e-01 
+ 2.328000000000e-10  6.202014565113e-01 
+ 2.428000000000e-10  5.417075102450e-01 
+ 2.528000000000e-10  4.161519970610e-01 
+ 2.628000000000e-10  2.448960905686e-01 
+ 2.728000000000e-10  3.892968213965e-02 
+ 2.828000000000e-10 -1.791505445505e-01 
+ 2.928000000000e-10 -3.778686664383e-01 
+ 3.028000000000e-10 -5.268093330033e-01 
+ 3.128000000000e-10 -6.159877416348e-01 
+ 3.228000000000e-10 -6.476195951568e-01 
+ 3.328000000000e-10 -6.216667221790e-01 
+ 3.428000000000e-10 -5.435382878554e-01 
+ 3.528000000000e-10 -4.178448923887e-01 
+ 3.628000000000e-10 -2.466531390426e-01 
+ 3.728000000000e-10 -4.041876256606e-02 
+ 3.828000000000e-10  1.777092594525e-01 
+ 3.928000000000e-10  3.768542192180e-01 
+ 4.028000000000e-10  5.260351926041e-01 
+ 4.128000000000e-10  6.156923491854e-01 
+ 4.228000000000e-10  6.475364165656e-01 
+ 4.328000000000e-10  6.220253224816e-01 
+ 4.428000000000e-10  5.439681165412e-01 
+ 4.528000000000e-10  4.184919515643e-01 
+ 4.628000000000e-10  2.472032785778e-01 
+ 4.728000000000e-10  4.108392377197e-02 
+ 4.828000000000e-10 -1.772209974541e-01 
+ 4.928000000000e-10 -3.763464849454e-01 
+ 5.028000000000e-10 -5.257893585276e-01 
+ 5.128000000000e-10 -6.154751208437e-01 
+ 5.228000000000e-10 -6.475677164184e-01 
+ 5.328000000000e-10 -6.220637777790e-01 
+ 5.428000000000e-10 -5.441970040997e-01 
+ 5.528000000000e-10 -4.186454653208e-01 
+ 5.628000000000e-10 -2.474812841152e-01 
+ 5.728000000000e-10 -4.124875776275e-02 
+ 5.828000000000e-10  1.769646369358e-01 
+ 5.928000000000e-10  3.762321495571e-01 
+ 6.028000000000e-10  5.256270530622e-01 
+ 6.128000000000e-10  6.154644314175e-01 
+ 6.228000000000e-10  6.475079392204e-01 
+ 6.328000000000e-10  6.221477255403e-01 
+ 6.428000000000e-10  5.442104878297e-01 
+ 6.528000000000e-10  4.187701859554e-01 
+ 6.628000000000e-10  2.475138621783e-01 
+ 6.728000000000e-10  4.137738638918e-02 
+ 6.828000000000e-10 -1.769383615791e-01 
+ 6.928000000000e-10 -3.761265802968e-01 
+ 7.028000000000e-10 -5.256298366366e-01 
+ 7.128000000000e-10 -6.153992750277e-01 
+ 7.228000000000e-10 -6.475476374408e-01 
+ 7.328000000000e-10 -6.221164421539e-01 
+ 7.428000000000e-10 -5.442762390873e-01 
+ 7.528000000000e-10 -4.187551150856e-01 
+ 7.628000000000e-10 -2.475858208222e-01 
+ 7.728000000000e-10 -4.136415856981e-02 
+ 7.828000000000e-10  1.768699557901e-01 
+ 7.928000000000e-10  3.761440347995e-01 
+ 8.028000000000e-10  5.255765528630e-01 
+ 8.128000000000e-10  6.154291154928e-01 
+ 8.228000000000e-10  6.475082015932e-01 
+ 8.328000000000e-10  6.221591874056e-01 
+ 8.428000000000e-10  5.442468649409e-01 
+ 8.528000000000e-10  4.188025713318e-01 
+ 8.628000000000e-10  2.475593730203e-01 
+ 8.728000000000e-10  4.141194467582e-02 
+ 8.828000000000e-10 -1.768965906206e-01 
+ 8.928000000000e-10 -3.761014263264e-01 
+ 9.028000000000e-10 -5.256047249426e-01 
+ 9.128000000000e-10 -6.153930400649e-01 
+ 9.228000000000e-10 -6.475410523019e-01 
+ 9.328000000000e-10 -6.221273229309e-01 
+ 9.428000000000e-10 -5.442828742825e-01 
+ 9.528000000000e-10 -4.187734552047e-01 
+ 9.628000000000e-10 -2.475958588134e-01 
+ 9.728000000000e-10 -4.138326223977e-02 
+ 9.828000000000e-10  1.768611473522e-01 
+ 9.928000000000e-10  3.761288017358e-01 
+ 1.000000000000e-09  4.898465656484e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/conditions.yaml
new file mode 100644
index 00000000..12457833
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 7
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_07
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb.sch
new file mode 100644
index 00000000..3b1a3f45
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb_8.data
new file mode 100644
index 00000000..2ec9911e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_core_tb_8.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.915574653990e-01 
+ 1.728000000000e-10 -8.207206468644e-02 
+ 1.828000000000e-10  1.443140454917e-01 
+ 1.928000000000e-10  3.578501059917e-01 
+ 2.028000000000e-10  5.264102614641e-01 
+ 2.128000000000e-10  6.356033847750e-01 
+ 2.228000000000e-10  6.852124516173e-01 
+ 2.328000000000e-10  6.731697751231e-01 
+ 2.428000000000e-10  6.014680860110e-01 
+ 2.528000000000e-10  4.762934940598e-01 
+ 2.628000000000e-10  3.019743151843e-01 
+ 2.728000000000e-10  9.052768843264e-02 
+ 2.828000000000e-10 -1.376882496508e-01 
+ 2.928000000000e-10 -3.528073773591e-01 
+ 3.028000000000e-10 -5.234244166185e-01 
+ 3.128000000000e-10 -6.340851318675e-01 
+ 3.228000000000e-10 -6.854084589569e-01 
+ 3.328000000000e-10 -6.747695956588e-01 
+ 3.428000000000e-10 -6.042844418494e-01 
+ 3.528000000000e-10 -4.793995649692e-01 
+ 3.628000000000e-10 -3.052822644166e-01 
+ 3.728000000000e-10 -9.358407685982e-02 
+ 3.828000000000e-10  1.347194202511e-01 
+ 3.928000000000e-10  3.504174847188e-01 
+ 4.028000000000e-10  5.215924623562e-01 
+ 4.128000000000e-10  6.330900225454e-01 
+ 4.228000000000e-10  6.849701135730e-01 
+ 4.328000000000e-10  6.751037342439e-01 
+ 4.428000000000e-10  6.049384750133e-01 
+ 4.528000000000e-10  4.803914109079e-01 
+ 4.628000000000e-10  3.062148923158e-01 
+ 4.728000000000e-10  9.463220881739e-02 
+ 4.828000000000e-10 -1.338572933423e-01 
+ 4.928000000000e-10 -3.495689260045e-01 
+ 5.028000000000e-10 -5.210792449240e-01 
+ 5.128000000000e-10 -6.326887195405e-01 
+ 5.228000000000e-10 -6.848983576670e-01 
+ 5.328000000000e-10 -6.751198274713e-01 
+ 5.428000000000e-10 -6.052060952211e-01 
+ 5.528000000000e-10 -4.806148207689e-01 
+ 5.628000000000e-10 -3.065686575138e-01 
+ 5.728000000000e-10 -9.487468231530e-02 
+ 5.828000000000e-10  1.335246601606e-01 
+ 5.928000000000e-10  3.493821792388e-01 
+ 6.028000000000e-10  5.208575371198e-01 
+ 6.128000000000e-10  6.326338805716e-01 
+ 6.228000000000e-10  6.848108600046e-01 
+ 6.328000000000e-10  6.751907109187e-01 
+ 6.428000000000e-10  6.052214841565e-01 
+ 6.528000000000e-10  4.807458450129e-01 
+ 6.628000000000e-10  3.066111422989e-01 
+ 6.728000000000e-10  9.501122064621e-02 
+ 6.828000000000e-10 -1.334882175614e-01 
+ 6.928000000000e-10 -3.492660352924e-01 
+ 7.028000000000e-10 -5.208495294585e-01 
+ 7.128000000000e-10 -6.325598499367e-01 
+ 7.228000000000e-10 -6.848421004985e-01 
+ 7.328000000000e-10 -6.751543080912e-01 
+ 7.428000000000e-10 -6.052828258645e-01 
+ 7.528000000000e-10 -4.807293659120e-01 
+ 7.628000000000e-10 -3.066794924108e-01 
+ 7.728000000000e-10 -9.499664108150e-02 
+ 7.828000000000e-10  1.334220275121e-01 
+ 7.928000000000e-10  3.492835018463e-01 
+ 8.028000000000e-10  5.207961769649e-01 
+ 8.128000000000e-10  6.325876998525e-01 
+ 8.228000000000e-10  6.848014468222e-01 
+ 8.328000000000e-10  6.751935994962e-01 
+ 8.428000000000e-10  6.052518981308e-01 
+ 8.528000000000e-10  4.807729857688e-01 
+ 8.628000000000e-10  3.066516205185e-01 
+ 8.728000000000e-10  9.504068447267e-02 
+ 8.828000000000e-10 -1.334502935734e-01 
+ 8.928000000000e-10 -3.492430994753e-01 
+ 9.028000000000e-10 -5.208246106410e-01 
+ 9.128000000000e-10 -6.325523513325e-01 
+ 9.228000000000e-10 -6.848328984481e-01 
+ 9.328000000000e-10 -6.751615848536e-01 
+ 9.428000000000e-10 -6.052856721640e-01 
+ 9.528000000000e-10 -4.807436971446e-01 
+ 9.628000000000e-10 -3.066854569150e-01 
+ 9.728000000000e-10 -9.501170247959e-02 
+ 9.828000000000e-10  1.334168358063e-01 
+ 9.928000000000e-10  3.492707284922e-01 
+ 1.000000000000e-09  4.787459694615e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/conditions.yaml
new file mode 100644
index 00000000..95a41dea
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 8
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_08
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb.sch
new file mode 100644
index 00000000..dde89224
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb_9.data
new file mode 100644
index 00000000..1eb23e09
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_core_tb_9.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.397443385003e-01 
+ 1.728000000000e-10 -2.045536352810e-01 
+ 1.828000000000e-10  1.313863393294e-01 
+ 1.928000000000e-10  3.838209275603e-01 
+ 2.028000000000e-10  5.347375940933e-01 
+ 2.128000000000e-10  6.276591932156e-01 
+ 2.228000000000e-10  7.115621702194e-01 
+ 2.328000000000e-10  7.798611559065e-01 
+ 2.428000000000e-10  8.066497785728e-01 
+ 2.528000000000e-10  7.447444131165e-01 
+ 2.628000000000e-10  5.331798214247e-01 
+ 2.728000000000e-10  1.991243487461e-01 
+ 2.828000000000e-10 -1.352153251063e-01 
+ 2.928000000000e-10 -3.864762984078e-01 
+ 3.028000000000e-10 -5.369168929595e-01 
+ 3.128000000000e-10 -6.290603792866e-01 
+ 3.228000000000e-10 -7.126196515736e-01 
+ 3.328000000000e-10 -7.804415576126e-01 
+ 3.428000000000e-10 -8.071911048716e-01 
+ 3.528000000000e-10 -7.450481751688e-01 
+ 3.628000000000e-10 -5.336055963763e-01 
+ 3.728000000000e-10 -1.993198332358e-01 
+ 3.828000000000e-10  1.349559401886e-01 
+ 3.928000000000e-10  3.864112742700e-01 
+ 4.028000000000e-10  5.367351878370e-01 
+ 4.128000000000e-10  6.290489992071e-01 
+ 4.228000000000e-10  7.124864782962e-01 
+ 4.328000000000e-10  7.804750739895e-01 
+ 4.428000000000e-10  8.070933947437e-01 
+ 4.528000000000e-10  7.451033689318e-01 
+ 4.628000000000e-10  5.335168975820e-01 
+ 4.728000000000e-10  1.993807368925e-01 
+ 4.828000000000e-10 -1.350304895400e-01 
+ 4.928000000000e-10 -3.863532554681e-01 
+ 5.028000000000e-10 -5.368040585560e-01 
+ 5.128000000000e-10 -6.289909078772e-01 
+ 5.228000000000e-10 -7.125533448218e-01 
+ 5.328000000000e-10 -7.804160897110e-01 
+ 5.428000000000e-10 -8.071554863663e-01 
+ 5.528000000000e-10 -7.450422465689e-01 
+ 5.628000000000e-10 -5.335838460974e-01 
+ 5.728000000000e-10 -1.993167730115e-01 
+ 5.828000000000e-10  1.349726890253e-01 
+ 5.928000000000e-10  3.864109858256e-01 
+ 6.028000000000e-10  5.367479691018e-01 
+ 6.128000000000e-10  6.290476980128e-01 
+ 6.228000000000e-10  7.124950121919e-01 
+ 6.328000000000e-10  7.804717191606e-01 
+ 6.428000000000e-10  8.070994779138e-01 
+ 6.528000000000e-10  7.450975613250e-01 
+ 6.628000000000e-10  5.335259065522e-01 
+ 6.728000000000e-10  1.993734548210e-01 
+ 6.828000000000e-10 -1.350242777574e-01 
+ 6.928000000000e-10 -3.863605033303e-01 
+ 7.028000000000e-10 -5.367975294074e-01 
+ 7.128000000000e-10 -6.289982763959e-01 
+ 7.228000000000e-10 -7.125455111440e-01 
+ 7.328000000000e-10 -7.804238043085e-01 
+ 7.428000000000e-10 -8.071473680780e-01 
+ 7.528000000000e-10 -7.450494772754e-01 
+ 7.628000000000e-10 -5.335773499054e-01 
+ 7.728000000000e-10 -1.993230348361e-01 
+ 7.828000000000e-10  1.349793746975e-01 
+ 7.928000000000e-10  3.864055722387e-01 
+ 8.028000000000e-10  5.367539279153e-01 
+ 8.128000000000e-10  6.290427569852e-01 
+ 8.228000000000e-10  7.125002063044e-01 
+ 8.328000000000e-10  7.804668926767e-01 
+ 8.428000000000e-10  8.071042297758e-01 
+ 8.528000000000e-10  7.450922570276e-01 
+ 8.628000000000e-10  5.335323457615e-01 
+ 8.728000000000e-10  1.993673584870e-01 
+ 8.828000000000e-10 -1.350193573750e-01 
+ 8.928000000000e-10 -3.863660901230e-01 
+ 9.028000000000e-10 -5.367925035482e-01 
+ 9.128000000000e-10 -6.290039875175e-01 
+ 9.228000000000e-10 -7.125398122704e-01 
+ 9.328000000000e-10 -7.804294363608e-01 
+ 9.428000000000e-10 -8.071416857778e-01 
+ 9.528000000000e-10 -7.450548065452e-01 
+ 9.628000000000e-10 -5.335722743766e-01 
+ 9.728000000000e-10 -1.993280329539e-01 
+ 9.828000000000e-10  1.349843549639e-01 
+ 9.928000000000e-10  3.864011317450e-01 
+ 1.000000000000e-09  5.028020863733e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/conditions.yaml
new file mode 100644
index 00000000..fd2b1fae
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 9
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_09
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb.sch
new file mode 100644
index 00000000..fe3742cb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb_10.data
new file mode 100644
index 00000000..973ede5e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_core_tb_10.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.293189432094e-01 
+ 1.728000000000e-10 -2.034299929592e-01 
+ 1.828000000000e-10  1.254532736892e-01 
+ 1.928000000000e-10  3.744603520131e-01 
+ 2.028000000000e-10  5.220595086358e-01 
+ 2.128000000000e-10  6.139346231694e-01 
+ 2.228000000000e-10  6.977077768020e-01 
+ 2.328000000000e-10  7.638951530454e-01 
+ 2.428000000000e-10  7.881008470503e-01 
+ 2.528000000000e-10  7.271434956617e-01 
+ 2.628000000000e-10  5.227259392947e-01 
+ 2.728000000000e-10  1.977807095317e-01 
+ 2.828000000000e-10 -1.296557480667e-01 
+ 2.928000000000e-10 -3.774966254092e-01 
+ 3.028000000000e-10 -5.245506032311e-01 
+ 3.128000000000e-10 -6.155925798862e-01 
+ 3.228000000000e-10 -6.989490114600e-01 
+ 3.328000000000e-10 -7.646204924296e-01 
+ 3.428000000000e-10 -7.887093478172e-01 
+ 3.528000000000e-10 -7.274783648153e-01 
+ 3.628000000000e-10 -5.231513423786e-01 
+ 3.728000000000e-10 -1.979863018154e-01 
+ 3.828000000000e-10  1.294013660930e-01 
+ 3.928000000000e-10  3.774276121382e-01 
+ 4.028000000000e-10  5.243833105689e-01 
+ 4.128000000000e-10  6.155813660155e-01 
+ 4.228000000000e-10  6.988272077165e-01 
+ 4.328000000000e-10  7.646509984988e-01 
+ 4.428000000000e-10  7.886185007607e-01 
+ 4.528000000000e-10  7.275266613790e-01 
+ 4.628000000000e-10  5.230676681296e-01 
+ 4.728000000000e-10  1.980405747385e-01 
+ 4.828000000000e-10 -1.294713662253e-01 
+ 4.928000000000e-10 -3.773761496757e-01 
+ 5.028000000000e-10 -5.244469821379e-01 
+ 5.128000000000e-10 -6.155294307936e-01 
+ 5.228000000000e-10 -6.988887956355e-01 
+ 5.328000000000e-10 -7.645972449904e-01 
+ 5.428000000000e-10 -7.886754254295e-01 
+ 5.528000000000e-10 -7.274706677122e-01 
+ 5.628000000000e-10 -5.231295350854e-01 
+ 5.728000000000e-10 -1.979806299381e-01 
+ 5.828000000000e-10  1.294187696545e-01 
+ 5.928000000000e-10  3.774292707563e-01 
+ 6.028000000000e-10  5.243961595933e-01 
+ 6.128000000000e-10  6.155814701559e-01 
+ 6.228000000000e-10  6.988355515168e-01 
+ 6.328000000000e-10  7.646484599731e-01 
+ 6.428000000000e-10  7.886243100181e-01 
+ 6.528000000000e-10  7.275215569265e-01 
+ 6.628000000000e-10  5.230764840752e-01 
+ 6.728000000000e-10  1.980332799823e-01 
+ 6.828000000000e-10 -1.294660192513e-01 
+ 6.928000000000e-10 -3.773827405650e-01 
+ 7.028000000000e-10 -5.244413520748e-01 
+ 7.128000000000e-10 -6.155361997798e-01 
+ 7.228000000000e-10 -6.988817029216e-01 
+ 7.328000000000e-10 -7.646043204444e-01 
+ 7.428000000000e-10 -7.886680576572e-01 
+ 7.528000000000e-10 -7.274772120684e-01 
+ 7.628000000000e-10 -5.231238849653e-01 
+ 7.728000000000e-10 -1.979860775160e-01 
+ 7.828000000000e-10  1.294249237809e-01 
+ 7.928000000000e-10  3.774244918330e-01 
+ 8.028000000000e-10  5.244015690321e-01 
+ 8.128000000000e-10  6.155771739165e-01 
+ 8.228000000000e-10  6.988402156207e-01 
+ 8.328000000000e-10  7.646441380646e-01 
+ 8.428000000000e-10  7.886285892332e-01 
+ 8.528000000000e-10  7.275167248781e-01 
+ 8.628000000000e-10  5.230825202638e-01 
+ 8.728000000000e-10  1.980273627479e-01 
+ 8.828000000000e-10 -1.294617038455e-01 
+ 8.928000000000e-10 -3.773878907236e-01 
+ 9.028000000000e-10 -5.244369215985e-01 
+ 9.128000000000e-10 -6.155414802599e-01 
+ 9.228000000000e-10 -6.988765421320e-01 
+ 9.328000000000e-10 -7.646094975483e-01 
+ 9.428000000000e-10 -7.886629049186e-01 
+ 9.528000000000e-10 -7.274820443091e-01 
+ 9.628000000000e-10 -5.231193961018e-01 
+ 9.728000000000e-10 -1.979905037884e-01 
+ 9.828000000000e-10  1.294294922144e-01 
+ 9.928000000000e-10  3.774205018001e-01 
+ 1.000000000000e-09  4.912603506308e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/conditions.yaml
new file mode 100644
index 00000000..3113a09b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 10
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_10
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb.sch
new file mode 100644
index 00000000..397774de
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb_11.data
new file mode 100644
index 00000000..799f8459
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_core_tb_11.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.473675478550e-01 
+ 1.728000000000e-10 -2.087893101739e-01 
+ 1.828000000000e-10  1.310494751476e-01 
+ 1.928000000000e-10  3.871555645678e-01 
+ 2.028000000000e-10  5.437689230363e-01 
+ 2.128000000000e-10  6.391330299748e-01 
+ 2.228000000000e-10  7.213082317981e-01 
+ 2.328000000000e-10  7.903248370025e-01 
+ 2.428000000000e-10  8.187618792919e-01 
+ 2.528000000000e-10  7.555729663838e-01 
+ 2.628000000000e-10  5.409345054541e-01 
+ 2.728000000000e-10  2.036912835862e-01 
+ 2.828000000000e-10 -1.345140506878e-01 
+ 2.928000000000e-10 -3.895370892644e-01 
+ 3.028000000000e-10 -5.457400052530e-01 
+ 3.128000000000e-10 -6.403498057265e-01 
+ 3.228000000000e-10 -7.222286336937e-01 
+ 3.328000000000e-10 -7.907911780827e-01 
+ 3.428000000000e-10 -8.192361080664e-01 
+ 3.528000000000e-10 -7.558198978931e-01 
+ 3.628000000000e-10 -5.413206307136e-01 
+ 3.728000000000e-10 -2.038438399825e-01 
+ 3.828000000000e-10  1.342763346632e-01 
+ 3.928000000000e-10  3.894921044587e-01 
+ 4.028000000000e-10  5.455616788274e-01 
+ 4.128000000000e-10  6.403489734683e-01 
+ 4.228000000000e-10  7.220944352324e-01 
+ 4.328000000000e-10  7.908322596821e-01 
+ 4.428000000000e-10  8.191363162855e-01 
+ 4.528000000000e-10  7.558824803046e-01 
+ 4.628000000000e-10  5.412307821184e-01 
+ 4.728000000000e-10  2.039121351986e-01 
+ 4.828000000000e-10 -1.343528713892e-01 
+ 4.928000000000e-10 -3.894290190191e-01 
+ 5.028000000000e-10 -5.456335562174e-01 
+ 5.128000000000e-10 -6.402860869065e-01 
+ 5.228000000000e-10 -7.221652152444e-01 
+ 5.328000000000e-10 -7.907686614943e-01 
+ 5.428000000000e-10 -8.192023796026e-01 
+ 5.528000000000e-10 -7.558173441778e-01 
+ 5.628000000000e-10 -5.413004970284e-01 
+ 5.728000000000e-10 -2.038447386050e-01 
+ 5.828000000000e-10  1.342913524064e-01 
+ 5.928000000000e-10  3.894897157728e-01 
+ 6.028000000000e-10  5.455737058766e-01 
+ 6.128000000000e-10  6.403462778603e-01 
+ 6.228000000000e-10  7.221032530671e-01 
+ 6.328000000000e-10  7.908278354740e-01 
+ 6.428000000000e-10  8.191430293573e-01 
+ 6.528000000000e-10  7.558759446864e-01 
+ 6.628000000000e-10  5.412396296665e-01 
+ 6.728000000000e-10  2.039046702204e-01 
+ 6.828000000000e-10 -1.343459163903e-01 
+ 6.928000000000e-10 -3.894366779769e-01 
+ 7.028000000000e-10 -5.456262483653e-01 
+ 7.128000000000e-10 -6.402940065215e-01 
+ 7.228000000000e-10 -7.221570137640e-01 
+ 7.328000000000e-10 -7.907769448806e-01 
+ 7.428000000000e-10 -8.191938542033e-01 
+ 7.528000000000e-10 -7.558251320231e-01 
+ 7.628000000000e-10 -5.412933191298e-01 
+ 7.728000000000e-10 -2.038518419443e-01 
+ 7.828000000000e-10  1.342982918430e-01 
+ 7.928000000000e-10  3.894837914532e-01 
+ 8.028000000000e-10  5.455799247329e-01 
+ 8.128000000000e-10  6.403408689327e-01 
+ 8.228000000000e-10  7.221089932485e-01 
+ 8.328000000000e-10  7.908225333386e-01 
+ 8.428000000000e-10  8.191482615363e-01 
+ 8.528000000000e-10  7.558702665648e-01 
+ 8.628000000000e-10  5.412462517638e-01 
+ 8.728000000000e-10  2.038984202104e-01 
+ 8.828000000000e-10 -1.343404705774e-01 
+ 8.928000000000e-10 -3.894425333092e-01 
+ 9.028000000000e-10 -5.456206778041e-01 
+ 9.128000000000e-10 -6.403000729433e-01 
+ 9.228000000000e-10 -7.221509667404e-01 
+ 9.328000000000e-10 -7.907829740936e-01 
+ 9.428000000000e-10 -8.191877974471e-01 
+ 9.528000000000e-10 -7.558308764830e-01 
+ 9.628000000000e-10 -5.412878201925e-01 
+ 9.728000000000e-10 -2.038573569097e-01 
+ 9.828000000000e-10  1.343035264203e-01 
+ 9.928000000000e-10  3.894790170617e-01 
+ 1.000000000000e-09  5.100069898815e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/conditions.yaml
new file mode 100644
index 00000000..5b32d934
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 11
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_11
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb.sch
new file mode 100644
index 00000000..4341a240
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb_12.data
new file mode 100644
index 00000000..db4e4cce
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_core_tb_12.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.049557277618e-01 
+ 1.728000000000e-10 -1.958466480437e-01 
+ 1.828000000000e-10  1.196319367700e-01 
+ 1.928000000000e-10  3.700244189406e-01 
+ 2.028000000000e-10  5.308067637731e-01 
+ 2.128000000000e-10  6.311299202315e-01 
+ 2.228000000000e-10  7.086540860403e-01 
+ 2.328000000000e-10  7.625529356493e-01 
+ 2.428000000000e-10  7.708473475114e-01 
+ 2.528000000000e-10  6.980446990655e-01 
+ 2.628000000000e-10  4.981026307256e-01 
+ 2.728000000000e-10  1.904449044265e-01 
+ 2.828000000000e-10 -1.236510258628e-01 
+ 2.928000000000e-10 -3.730975798774e-01 
+ 3.028000000000e-10 -5.333436235403e-01 
+ 3.128000000000e-10 -6.328422885796e-01 
+ 3.228000000000e-10 -7.099622515515e-01 
+ 3.328000000000e-10 -7.633093670089e-01 
+ 3.428000000000e-10 -7.714462858000e-01 
+ 3.528000000000e-10 -6.983543456334e-01 
+ 3.628000000000e-10 -4.984830350414e-01 
+ 3.728000000000e-10 -1.906133898346e-01 
+ 3.828000000000e-10  1.234140438752e-01 
+ 3.928000000000e-10  3.730258572177e-01 
+ 4.028000000000e-10  5.331667972487e-01 
+ 4.128000000000e-10  6.328214645319e-01 
+ 4.228000000000e-10  7.098336990067e-01 
+ 4.328000000000e-10  7.633335528675e-01 
+ 4.428000000000e-10  7.713603033543e-01 
+ 4.528000000000e-10  6.984040906368e-01 
+ 4.628000000000e-10  4.984087981115e-01 
+ 4.728000000000e-10  1.906698925098e-01 
+ 4.828000000000e-10 -1.234792426423e-01 
+ 4.928000000000e-10 -3.729733539485e-01 
+ 5.028000000000e-10 -5.332277682129e-01 
+ 5.128000000000e-10 -6.327690017914e-01 
+ 5.228000000000e-10 -7.098933602520e-01 
+ 5.328000000000e-10 -7.632805035294e-01 
+ 5.428000000000e-10 -7.714147767047e-01 
+ 5.528000000000e-10 -6.983493927960e-01 
+ 5.628000000000e-10 -4.984657326360e-01 
+ 5.728000000000e-10 -1.906133403657e-01 
+ 5.828000000000e-10  1.234275058651e-01 
+ 5.928000000000e-10  3.730246636548e-01 
+ 6.028000000000e-10  5.331775888699e-01 
+ 6.128000000000e-10  6.328197652536e-01 
+ 6.228000000000e-10  7.098419058182e-01 
+ 6.328000000000e-10  7.633301342197e-01 
+ 6.428000000000e-10  7.713661487972e-01 
+ 6.528000000000e-10  6.983986251010e-01 
+ 6.628000000000e-10  4.984160910452e-01 
+ 6.728000000000e-10  1.906635868460e-01 
+ 6.828000000000e-10 -1.234734747225e-01 
+ 6.928000000000e-10 -3.729797013887e-01 
+ 7.028000000000e-10 -5.332215969565e-01 
+ 7.128000000000e-10 -6.327757131741e-01 
+ 7.228000000000e-10 -7.098865351622e-01 
+ 7.328000000000e-10 -7.632871392149e-01 
+ 7.428000000000e-10 -7.714081948986e-01 
+ 7.528000000000e-10 -6.983555969606e-01 
+ 7.628000000000e-10 -4.984601688237e-01 
+ 7.728000000000e-10 -1.906192454806e-01 
+ 7.828000000000e-10  1.234332321656e-01 
+ 7.928000000000e-10  3.730195983111e-01 
+ 8.028000000000e-10  5.331826746949e-01 
+ 8.128000000000e-10  6.328151783475e-01 
+ 8.228000000000e-10  7.098466992587e-01 
+ 8.328000000000e-10  7.633256332241e-01 
+ 8.428000000000e-10  7.713705417094e-01 
+ 8.528000000000e-10  6.983937777920e-01 
+ 8.628000000000e-10  4.984215072239e-01 
+ 8.728000000000e-10  1.906583322627e-01 
+ 8.828000000000e-10 -1.234689419945e-01 
+ 8.928000000000e-10 -3.729845695752e-01 
+ 9.028000000000e-10 -5.332169477613e-01 
+ 9.128000000000e-10 -6.327807857544e-01 
+ 9.228000000000e-10 -7.098815617208e-01 
+ 9.328000000000e-10 -7.632920474235e-01 
+ 9.428000000000e-10 -7.714033753149e-01 
+ 9.528000000000e-10 -6.983602366678e-01 
+ 9.628000000000e-10 -4.984557776243e-01 
+ 9.728000000000e-10 -1.906237729891e-01 
+ 9.828000000000e-10  1.234375916302e-01 
+ 9.928000000000e-10  3.730155682884e-01 
+ 1.000000000000e-09  4.959193237551e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/conditions.yaml
new file mode 100644
index 00000000..7de6eb46
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 12
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_12
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb.sch
new file mode 100644
index 00000000..f7a1d543
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb_13.data
new file mode 100644
index 00000000..abbd3617
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_core_tb_13.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.935497259980e-01 
+ 1.728000000000e-10 -1.928633983658e-01 
+ 1.828000000000e-10  1.160949240371e-01 
+ 1.928000000000e-10  3.619360857197e-01 
+ 2.028000000000e-10  5.185143131218e-01 
+ 2.128000000000e-10  6.170086772416e-01 
+ 2.228000000000e-10  6.939063598865e-01 
+ 2.328000000000e-10  7.457993341265e-01 
+ 2.428000000000e-10  7.520509596304e-01 
+ 2.528000000000e-10  6.804739824857e-01 
+ 2.628000000000e-10  4.870426149481e-01 
+ 2.728000000000e-10  1.875308246798e-01 
+ 2.828000000000e-10 -1.202389208092e-01 
+ 2.928000000000e-10 -3.651754434827e-01 
+ 3.028000000000e-10 -5.211918880427e-01 
+ 3.128000000000e-10 -6.188469707889e-01 
+ 3.228000000000e-10 -6.953072467312e-01 
+ 3.328000000000e-10 -7.466129151979e-01 
+ 3.428000000000e-10 -7.526565311823e-01 
+ 3.528000000000e-10 -6.807675409917e-01 
+ 3.628000000000e-10 -4.873945801883e-01 
+ 3.728000000000e-10 -1.876809763872e-01 
+ 3.828000000000e-10  1.200199744899e-01 
+ 3.928000000000e-10  3.651151173578e-01 
+ 4.028000000000e-10  5.210322421793e-01 
+ 4.128000000000e-10  6.188330192958e-01 
+ 4.228000000000e-10  6.951893716680e-01 
+ 4.328000000000e-10  7.466394998986e-01 
+ 4.428000000000e-10  7.525773069027e-01 
+ 4.528000000000e-10  6.808165070916e-01 
+ 4.628000000000e-10  4.873248087716e-01 
+ 4.728000000000e-10  1.877358679741e-01 
+ 4.828000000000e-10 -1.200819840902e-01 
+ 4.928000000000e-10 -3.650646413699e-01 
+ 5.028000000000e-10 -5.210903047408e-01 
+ 5.128000000000e-10 -6.187830156405e-01 
+ 5.228000000000e-10 -6.952462050643e-01 
+ 5.328000000000e-10 -7.465883056072e-01 
+ 5.428000000000e-10 -7.526293067125e-01 
+ 5.528000000000e-10 -6.807638103361e-01 
+ 5.628000000000e-10 -4.873795115625e-01 
+ 5.728000000000e-10 -1.876807689254e-01 
+ 5.828000000000e-10  1.200326256254e-01 
+ 5.928000000000e-10  3.651139754788e-01 
+ 6.028000000000e-10  5.210426454606e-01 
+ 6.128000000000e-10  6.188315227579e-01 
+ 6.228000000000e-10  6.951972695911e-01 
+ 6.328000000000e-10  7.466359762403e-01 
+ 6.428000000000e-10  7.525829976005e-01 
+ 6.528000000000e-10  6.808110143898e-01 
+ 6.628000000000e-10  4.873318873720e-01 
+ 6.728000000000e-10  1.877292356433e-01 
+ 6.828000000000e-10 -1.200767202072e-01 
+ 6.928000000000e-10 -3.650706499628e-01 
+ 7.028000000000e-10 -5.210847183857e-01 
+ 7.128000000000e-10 -6.187893543189e-01 
+ 7.228000000000e-10 -6.952399017798e-01 
+ 7.328000000000e-10 -7.465944604664e-01 
+ 7.428000000000e-10 -7.526232942576e-01 
+ 7.528000000000e-10 -6.807695137827e-01 
+ 7.628000000000e-10 -4.873744121182e-01 
+ 7.728000000000e-10 -1.876860880622e-01 
+ 7.828000000000e-10  1.200380835632e-01 
+ 7.928000000000e-10  3.651091778387e-01 
+ 8.028000000000e-10  5.210475167171e-01 
+ 8.128000000000e-10  6.188272213187e-01 
+ 8.228000000000e-10  6.952018279574e-01 
+ 8.328000000000e-10  7.466316140292e-01 
+ 8.428000000000e-10  7.525872528114e-01 
+ 8.528000000000e-10  6.808063071094e-01 
+ 8.628000000000e-10  4.873371355126e-01 
+ 8.728000000000e-10  1.877239857571e-01 
+ 8.828000000000e-10 -1.200724809112e-01 
+ 8.928000000000e-10 -3.650752679165e-01 
+ 9.028000000000e-10 -5.210804068397e-01 
+ 9.128000000000e-10 -6.187941569931e-01 
+ 9.228000000000e-10 -6.952352466105e-01 
+ 9.328000000000e-10 -7.465990720366e-01 
+ 9.428000000000e-10 -7.526188226163e-01 
+ 9.528000000000e-10 -6.807738360998e-01 
+ 9.628000000000e-10 -4.873703126609e-01 
+ 9.728000000000e-10 -1.876902725775e-01 
+ 9.828000000000e-10  1.200422409457e-01 
+ 9.928000000000e-10  3.651053453859e-01 
+ 1.000000000000e-09  4.847952698035e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/conditions.yaml
new file mode 100644
index 00000000..7e7f43da
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 13
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_13
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb.sch
new file mode 100644
index 00000000..ff92c0fe
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb_14.data
new file mode 100644
index 00000000..3796cea3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_core_tb_14.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.133282675634e-01 
+ 1.728000000000e-10 -2.031582081928e-01 
+ 1.828000000000e-10  1.144804838339e-01 
+ 1.928000000000e-10  3.698591588516e-01 
+ 2.028000000000e-10  5.380258146680e-01 
+ 2.128000000000e-10  6.422542980920e-01 
+ 2.228000000000e-10  7.191574927620e-01 
+ 2.328000000000e-10  7.734390216007e-01 
+ 2.428000000000e-10  7.823512104827e-01 
+ 2.528000000000e-10  7.081342613122e-01 
+ 2.628000000000e-10  5.065809773945e-01 
+ 2.728000000000e-10  1.980707374060e-01 
+ 2.828000000000e-10 -1.181831896095e-01 
+ 2.928000000000e-10 -3.727163876319e-01 
+ 3.028000000000e-10 -5.404428949084e-01 
+ 3.128000000000e-10 -6.438704305572e-01 
+ 3.228000000000e-10 -7.204145434420e-01 
+ 3.328000000000e-10 -7.741471374370e-01 
+ 3.428000000000e-10 -7.829309638154e-01 
+ 3.528000000000e-10 -7.084110972821e-01 
+ 3.628000000000e-10 -5.069426471107e-01 
+ 3.728000000000e-10 -1.982066720174e-01 
+ 3.828000000000e-10  1.179564926067e-01 
+ 3.928000000000e-10  3.726621714283e-01 
+ 4.028000000000e-10  5.402630628674e-01 
+ 4.128000000000e-10  6.438601752956e-01 
+ 4.228000000000e-10  7.202791375194e-01 
+ 4.328000000000e-10  7.741793827377e-01 
+ 4.428000000000e-10  7.828380754967e-01 
+ 4.528000000000e-10  7.084693803333e-01 
+ 4.628000000000e-10  5.068627667504e-01 
+ 4.728000000000e-10  1.982719515445e-01 
+ 4.828000000000e-10 -1.180275895897e-01 
+ 4.928000000000e-10 -3.726028735362e-01 
+ 5.028000000000e-10 -5.403301024789e-01 
+ 5.128000000000e-10 -6.438008084190e-01 
+ 5.228000000000e-10 -7.203455420725e-01 
+ 5.328000000000e-10 -7.741198297783e-01 
+ 5.428000000000e-10 -7.828987326701e-01 
+ 5.528000000000e-10 -7.084084859242e-01 
+ 5.628000000000e-10 -5.069251044876e-01 
+ 5.728000000000e-10 -1.982094732584e-01 
+ 5.828000000000e-10  1.179697981212e-01 
+ 5.928000000000e-10  3.726595322461e-01 
+ 6.028000000000e-10  5.402739437431e-01 
+ 6.128000000000e-10  6.438573026479e-01 
+ 6.228000000000e-10  7.202880216174e-01 
+ 6.328000000000e-10  7.741750830136e-01 
+ 6.428000000000e-10  7.828445699494e-01 
+ 6.528000000000e-10  7.084631989914e-01 
+ 6.628000000000e-10  5.068703543607e-01 
+ 6.728000000000e-10  1.982651160797e-01 
+ 6.828000000000e-10 -1.180209524418e-01 
+ 6.928000000000e-10 -3.726100259571e-01 
+ 7.028000000000e-10 -5.403229404029e-01 
+ 7.128000000000e-10 -6.438083895554e-01 
+ 7.228000000000e-10 -7.203378638829e-01 
+ 7.328000000000e-10 -7.741273273776e-01 
+ 7.428000000000e-10 -7.828912312659e-01 
+ 7.528000000000e-10 -7.084155733246e-01 
+ 7.628000000000e-10 -5.069185371484e-01 
+ 7.728000000000e-10 -1.982163796445e-01 
+ 7.828000000000e-10  1.179761824049e-01 
+ 7.928000000000e-10  3.726538824343e-01 
+ 8.028000000000e-10  5.402795684719e-01 
+ 8.128000000000e-10  6.438520994328e-01 
+ 8.228000000000e-10  7.202935093188e-01 
+ 8.328000000000e-10  7.741699689895e-01 
+ 8.428000000000e-10  7.828494756723e-01 
+ 8.528000000000e-10  7.084578188073e-01 
+ 8.628000000000e-10  5.068761410729e-01 
+ 8.728000000000e-10  1.982594122387e-01 
+ 8.828000000000e-10 -1.180157633845e-01 
+ 8.928000000000e-10 -3.726154653834e-01 
+ 9.028000000000e-10 -5.403175771302e-01 
+ 9.128000000000e-10 -6.438140825829e-01 
+ 9.228000000000e-10 -7.203322576361e-01 
+ 9.328000000000e-10 -7.741328388949e-01 
+ 9.428000000000e-10 -7.828857350121e-01 
+ 9.528000000000e-10 -7.084208512479e-01 
+ 9.628000000000e-10 -5.069134738545e-01 
+ 9.728000000000e-10 -1.982215797151e-01 
+ 9.828000000000e-10  1.179810466336e-01 
+ 9.928000000000e-10  3.726493985613e-01 
+ 1.000000000000e-09  5.010433738758e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/conditions.yaml
new file mode 100644
index 00000000..ec458589
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 14
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_14
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb.sch
new file mode 100644
index 00000000..f5d44dfb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb_15.data
new file mode 100644
index 00000000..a18684b0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_core_tb_15.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.764925698370e-01 
+ 1.728000000000e-10 -1.934019301872e-01 
+ 1.828000000000e-10  1.027850457497e-01 
+ 1.928000000000e-10  3.499528968595e-01 
+ 2.028000000000e-10  5.186059326128e-01 
+ 2.128000000000e-10  6.254912177700e-01 
+ 2.228000000000e-10  6.994356057335e-01 
+ 2.328000000000e-10  7.419604616039e-01 
+ 2.428000000000e-10  7.366001230119e-01 
+ 2.528000000000e-10  6.575586826882e-01 
+ 2.628000000000e-10  4.703480039804e-01 
+ 2.728000000000e-10  1.887311437228e-01 
+ 2.828000000000e-10 -1.064955609068e-01 
+ 2.928000000000e-10 -3.530674432656e-01 
+ 3.028000000000e-10 -5.214103928852e-01 
+ 3.128000000000e-10 -6.276329249236e-01 
+ 3.228000000000e-10 -7.010919569868e-01 
+ 3.328000000000e-10 -7.428528846984e-01 
+ 3.428000000000e-10 -7.371070425945e-01 
+ 3.528000000000e-10 -6.576931102984e-01 
+ 3.628000000000e-10 -4.705213908487e-01 
+ 3.728000000000e-10 -1.887451417089e-01 
+ 3.828000000000e-10  1.063771169054e-01 
+ 3.928000000000e-10  3.530644558224e-01 
+ 4.028000000000e-10  5.212882945537e-01 
+ 4.128000000000e-10  6.276273956697e-01 
+ 4.228000000000e-10  7.009872983885e-01 
+ 4.328000000000e-10  7.428850006835e-01 
+ 4.428000000000e-10  7.370483197885e-01 
+ 4.528000000000e-10  6.577532995019e-01 
+ 4.628000000000e-10  4.704734311564e-01 
+ 4.728000000000e-10  1.888066765622e-01 
+ 4.828000000000e-10 -1.064251900033e-01 
+ 4.928000000000e-10 -3.530110058012e-01 
+ 5.028000000000e-10 -5.213363794122e-01 
+ 5.128000000000e-10 -6.275779961821e-01 
+ 5.228000000000e-10 -7.010367362436e-01 
+ 5.328000000000e-10 -7.428359180794e-01 
+ 5.428000000000e-10 -7.370946234404e-01 
+ 5.528000000000e-10 -6.577041924295e-01 
+ 5.628000000000e-10 -4.705211118057e-01 
+ 5.728000000000e-10 -1.887571402743e-01 
+ 5.828000000000e-10  1.063798390696e-01 
+ 5.928000000000e-10  3.530562876751e-01 
+ 6.028000000000e-10  5.212929538773e-01 
+ 6.128000000000e-10  6.276223718978e-01 
+ 6.228000000000e-10  7.009927681762e-01 
+ 6.328000000000e-10  7.428797293753e-01 
+ 6.428000000000e-10  7.370526578677e-01 
+ 6.528000000000e-10  6.577470674825e-01 
+ 6.628000000000e-10  4.704784998901e-01 
+ 6.728000000000e-10  1.888003575241e-01 
+ 6.828000000000e-10 -1.064204487643e-01 
+ 6.928000000000e-10 -3.530168946500e-01 
+ 7.028000000000e-10 -5.213312567329e-01 
+ 7.128000000000e-10 -6.275838929681e-01 
+ 7.228000000000e-10 -7.010312441909e-01 
+ 7.328000000000e-10 -7.428415937954e-01 
+ 7.428000000000e-10 -7.370893810626e-01 
+ 7.528000000000e-10 -6.577094889087e-01 
+ 7.628000000000e-10 -4.705162397262e-01 
+ 7.728000000000e-10 -1.887623115300e-01 
+ 7.828000000000e-10  1.063847513579e-01 
+ 7.928000000000e-10  3.530516705381e-01 
+ 8.028000000000e-10  5.212973590939e-01 
+ 8.128000000000e-10  6.276181223045e-01 
+ 8.228000000000e-10  7.009970786285e-01 
+ 8.328000000000e-10  7.428754735512e-01 
+ 8.428000000000e-10  7.370567570344e-01 
+ 8.528000000000e-10  6.577427030952e-01 
+ 8.628000000000e-10  4.704830497474e-01 
+ 8.728000000000e-10  1.887958404937e-01 
+ 8.828000000000e-10 -1.064163174914e-01 
+ 8.928000000000e-10 -3.530210908451e-01 
+ 9.028000000000e-10 -5.213271590930e-01 
+ 9.128000000000e-10 -6.275881896870e-01 
+ 9.228000000000e-10 -7.010270518598e-01 
+ 9.328000000000e-10 -7.428457852801e-01 
+ 9.428000000000e-10 -7.370853633469e-01 
+ 9.528000000000e-10 -6.577134719194e-01 
+ 9.628000000000e-10 -4.705123783357e-01 
+ 9.728000000000e-10 -1.887662540331e-01 
+ 9.828000000000e-10  1.063885555413e-01 
+ 9.928000000000e-10  3.530480784075e-01 
+ 1.000000000000e-09  4.814572085440e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/conditions.yaml
new file mode 100644
index 00000000..72976e82
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 15
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_15
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb.sch
new file mode 100644
index 00000000..a044fcea
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb_16.data
new file mode 100644
index 00000000..5b9b7365
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_core_tb_16.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.643042367579e-01 
+ 1.728000000000e-10 -1.889536448800e-01 
+ 1.828000000000e-10  1.011027156160e-01 
+ 1.928000000000e-10  3.431119917378e-01 
+ 2.028000000000e-10  5.070519088353e-01 
+ 2.128000000000e-10  6.112991757094e-01 
+ 2.228000000000e-10  6.838020209744e-01 
+ 2.328000000000e-10  7.242864479517e-01 
+ 2.428000000000e-10  7.174167448313e-01 
+ 2.528000000000e-10  6.398083866093e-01 
+ 2.628000000000e-10  4.585166519927e-01 
+ 2.728000000000e-10  1.844271573483e-01 
+ 2.828000000000e-10 -1.048019054065e-01 
+ 2.928000000000e-10 -3.462317584687e-01 
+ 3.028000000000e-10 -5.098344721858e-01 
+ 3.128000000000e-10 -6.133899227371e-01 
+ 3.228000000000e-10 -6.853968517792e-01 
+ 3.328000000000e-10 -7.251059393871e-01 
+ 3.428000000000e-10 -7.178642533065e-01 
+ 3.528000000000e-10 -6.398898931720e-01 
+ 3.628000000000e-10 -4.586473976402e-01 
+ 3.728000000000e-10 -1.843989570585e-01 
+ 3.828000000000e-10  1.047140758745e-01 
+ 3.928000000000e-10  3.462576483703e-01 
+ 4.028000000000e-10  5.097333770465e-01 
+ 4.128000000000e-10  6.134023110554e-01 
+ 4.228000000000e-10  6.853047053340e-01 
+ 4.328000000000e-10  7.251501511308e-01 
+ 4.428000000000e-10  7.178117501486e-01 
+ 4.528000000000e-10  6.399568281317e-01 
+ 4.628000000000e-10  4.586017943502e-01 
+ 4.728000000000e-10  1.844658494373e-01 
+ 4.828000000000e-10 -1.047609876408e-01 
+ 4.928000000000e-10 -3.462003104379e-01 
+ 5.028000000000e-10 -5.097813732572e-01 
+ 5.128000000000e-10 -6.133504189098e-01 
+ 5.228000000000e-10 -6.853547602223e-01 
+ 5.328000000000e-10 -7.250985458364e-01 
+ 5.428000000000e-10 -7.178593251267e-01 
+ 5.528000000000e-10 -6.399055102013e-01 
+ 5.628000000000e-10 -4.586511534755e-01 
+ 5.728000000000e-10 -1.844138975484e-01 
+ 5.828000000000e-10  1.047143295024e-01 
+ 5.928000000000e-10  3.462472486482e-01 
+ 6.028000000000e-10  5.097369504642e-01 
+ 6.128000000000e-10  6.133959963639e-01 
+ 6.228000000000e-10  6.853096740322e-01 
+ 6.328000000000e-10  7.251438129543e-01 
+ 6.428000000000e-10  7.178160816468e-01 
+ 6.528000000000e-10  6.399498616471e-01 
+ 6.628000000000e-10  4.586069220749e-01 
+ 6.728000000000e-10  1.844588245643e-01 
+ 6.828000000000e-10 -1.047563687876e-01 
+ 6.928000000000e-10 -3.462063328010e-01 
+ 7.028000000000e-10 -5.097765086741e-01 
+ 7.128000000000e-10 -6.133562893232e-01 
+ 7.228000000000e-10 -6.853494321266e-01 
+ 7.328000000000e-10 -7.251041291885e-01 
+ 7.428000000000e-10 -7.178542203751e-01 
+ 7.528000000000e-10 -6.399107355976e-01 
+ 7.628000000000e-10 -4.586462738291e-01 
+ 7.728000000000e-10 -1.844190131957e-01 
+ 7.828000000000e-10  1.047193339603e-01 
+ 7.928000000000e-10  3.462424630766e-01 
+ 8.028000000000e-10  5.097415276109e-01 
+ 8.128000000000e-10  6.133915881396e-01 
+ 8.228000000000e-10  6.853141467162e-01 
+ 8.328000000000e-10  7.251393167662e-01 
+ 8.428000000000e-10  7.178204152808e-01 
+ 8.528000000000e-10  6.399452651751e-01 
+ 8.628000000000e-10  4.586116651576e-01 
+ 8.728000000000e-10  1.844540563551e-01 
+ 8.828000000000e-10 -1.047521530128e-01 
+ 8.928000000000e-10 -3.462105768541e-01 
+ 9.028000000000e-10 -5.097724238353e-01 
+ 9.128000000000e-10 -6.133605792288e-01 
+ 9.228000000000e-10 -6.853452315529e-01 
+ 9.328000000000e-10 -7.251083207568e-01 
+ 9.428000000000e-10 -7.178502144615e-01 
+ 9.528000000000e-10 -6.399147306347e-01 
+ 9.628000000000e-10 -4.586423495280e-01 
+ 9.728000000000e-10 -1.844229988419e-01 
+ 9.828000000000e-10  1.047232268776e-01 
+ 9.928000000000e-10  3.462387497741e-01 
+ 1.000000000000e-09  4.710752262880e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/conditions.yaml
new file mode 100644
index 00000000..178ac9dd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 16
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_16
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb.sch
new file mode 100644
index 00000000..f915ac12
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb_17.data
new file mode 100644
index 00000000..15600382
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_core_tb_17.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.852886719505e-01 
+ 1.728000000000e-10 -2.023606658915e-01 
+ 1.828000000000e-10  9.500407548716e-02 
+ 1.928000000000e-10  3.473018630854e-01 
+ 2.028000000000e-10  5.238539974445e-01 
+ 2.128000000000e-10  6.356942626004e-01 
+ 2.228000000000e-10  7.106560719901e-01 
+ 2.328000000000e-10  7.539243132234e-01 
+ 2.428000000000e-10  7.486736309564e-01 
+ 2.528000000000e-10  6.681985082542e-01 
+ 2.628000000000e-10  4.800908099257e-01 
+ 2.728000000000e-10  1.985903293754e-01 
+ 2.828000000000e-10 -9.801965724844e-02 
+ 2.928000000000e-10 -3.499456539083e-01 
+ 3.028000000000e-10 -5.264166063204e-01 
+ 3.128000000000e-10 -6.377599985577e-01 
+ 3.228000000000e-10 -7.123258227204e-01 
+ 3.328000000000e-10 -7.548386637736e-01 
+ 3.428000000000e-10 -7.491646196322e-01 
+ 3.528000000000e-10 -6.682802381819e-01 
+ 3.628000000000e-10 -4.802044877583e-01 
+ 3.728000000000e-10 -1.985554586747e-01 
+ 3.828000000000e-10  9.793570714348e-02 
+ 3.928000000000e-10  3.499705083814e-01 
+ 4.028000000000e-10  5.263126851869e-01 
+ 4.128000000000e-10  6.377668221774e-01 
+ 4.228000000000e-10  7.122256281615e-01 
+ 4.328000000000e-10  7.548735616237e-01 
+ 4.428000000000e-10  7.491068615558e-01 
+ 4.528000000000e-10  6.683430307676e-01 
+ 4.628000000000e-10  4.801581700099e-01 
+ 4.728000000000e-10  1.986186025664e-01 
+ 4.828000000000e-10 -9.798359332438e-02 
+ 4.928000000000e-10 -3.499159407959e-01 
+ 5.028000000000e-10 -5.263605524234e-01 
+ 5.128000000000e-10 -6.377159898188e-01 
+ 5.228000000000e-10 -7.122753084256e-01 
+ 5.328000000000e-10 -7.548237332543e-01 
+ 5.428000000000e-10 -7.491535548765e-01 
+ 5.528000000000e-10 -6.682936663178e-01 
+ 5.628000000000e-10 -4.802057994081e-01 
+ 5.728000000000e-10 -1.985692377738e-01 
+ 5.828000000000e-10  9.793754425938e-02 
+ 5.928000000000e-10  3.499612594703e-01 
+ 6.028000000000e-10  5.263165540334e-01 
+ 6.128000000000e-10  6.377608692391e-01 
+ 6.228000000000e-10  7.122309292959e-01 
+ 6.328000000000e-10  7.548679483739e-01 
+ 6.428000000000e-10  7.491113260135e-01 
+ 6.528000000000e-10  6.683367510584e-01 
+ 6.628000000000e-10  4.801631540398e-01 
+ 6.728000000000e-10  1.986123746205e-01 
+ 6.828000000000e-10 -9.797860547701e-02 
+ 6.928000000000e-10 -3.499219086015e-01 
+ 7.028000000000e-10 -5.263552271330e-01 
+ 7.128000000000e-10 -6.377219921840e-01 
+ 7.228000000000e-10 -7.122696952774e-01 
+ 7.328000000000e-10 -7.548295298651e-01 
+ 7.428000000000e-10 -7.491481908175e-01 
+ 7.528000000000e-10 -6.682991221138e-01 
+ 7.628000000000e-10 -4.802006967346e-01 
+ 7.728000000000e-10 -1.985745887274e-01 
+ 7.828000000000e-10  9.794256695295e-02 
+ 7.928000000000e-10  3.499565849765e-01 
+ 8.028000000000e-10  5.263210489698e-01 
+ 8.128000000000e-10  6.377564579322e-01 
+ 8.228000000000e-10  7.122353719246e-01 
+ 8.328000000000e-10  7.548635649925e-01 
+ 8.428000000000e-10  7.491155123701e-01 
+ 8.528000000000e-10  6.683323549155e-01 
+ 8.628000000000e-10  4.801676539865e-01 
+ 8.728000000000e-10  1.986078923136e-01 
+ 8.828000000000e-10 -9.797434132868e-02 
+ 8.928000000000e-10 -3.499261582655e-01 
+ 9.028000000000e-10 -5.263510069851e-01 
+ 9.128000000000e-10 -6.377263524572e-01 
+ 9.228000000000e-10 -7.122654282965e-01 
+ 9.328000000000e-10 -7.548337908470e-01 
+ 9.428000000000e-10 -7.491440991364e-01 
+ 9.528000000000e-10 -6.683032069827e-01 
+ 9.628000000000e-10 -4.801967157057e-01 
+ 9.728000000000e-10 -1.985786291727e-01 
+ 9.828000000000e-10  9.794644208878e-02 
+ 9.928000000000e-10  3.499529545785e-01 
+ 1.000000000000e-09  4.843355885316e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/conditions.yaml
new file mode 100644
index 00000000..4932bffd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 17
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_17
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb.sch
new file mode 100644
index 00000000..23448941
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb_18.data
new file mode 100644
index 00000000..6bdb4a2e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_core_tb_18.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.747244840755e-01 
+ 1.728000000000e-10  2.031348680811e-01 
+ 1.828000000000e-10 -1.640358346053e-01 
+ 1.928000000000e-10 -4.121983890365e-01 
+ 2.028000000000e-10 -5.403960481430e-01 
+ 2.128000000000e-10 -6.175267008304e-01 
+ 2.228000000000e-10 -7.185181164841e-01 
+ 2.328000000000e-10 -8.111835866476e-01 
+ 2.428000000000e-10 -8.505757111821e-01 
+ 2.528000000000e-10 -7.941523888433e-01 
+ 2.628000000000e-10 -5.697557803605e-01 
+ 2.728000000000e-10 -1.993901761575e-01 
+ 2.828000000000e-10  1.667454340744e-01 
+ 2.928000000000e-10  4.143424459307e-01 
+ 3.028000000000e-10  5.421310172268e-01 
+ 3.128000000000e-10  6.189024162340e-01 
+ 3.228000000000e-10  7.194369498053e-01 
+ 3.328000000000e-10  8.117600127730e-01 
+ 3.428000000000e-10  8.508336653308e-01 
+ 3.528000000000e-10  7.942656656211e-01 
+ 3.628000000000e-10  5.697751550033e-01 
+ 3.728000000000e-10  1.994135726672e-01 
+ 3.828000000000e-10 -1.667386419247e-01 
+ 3.928000000000e-10 -4.143148464313e-01 
+ 4.028000000000e-10 -5.421262038320e-01 
+ 4.128000000000e-10 -6.188832903749e-01 
+ 4.228000000000e-10 -7.194346712496e-01 
+ 4.328000000000e-10 -8.117442314974e-01 
+ 4.428000000000e-10 -8.508381039982e-01 
+ 4.528000000000e-10 -7.942559196005e-01 
+ 4.628000000000e-10 -5.697859373045e-01 
+ 4.728000000000e-10 -1.993975895742e-01 
+ 4.828000000000e-10  1.667322235508e-01 
+ 4.928000000000e-10  4.143280512458e-01 
+ 5.028000000000e-10  5.421195877560e-01 
+ 5.128000000000e-10  6.188968586913e-01 
+ 5.228000000000e-10  7.194236426239e-01 
+ 5.328000000000e-10  8.117540342679e-01 
+ 5.428000000000e-10  8.508266757829e-01 
+ 5.528000000000e-10  7.942652287581e-01 
+ 5.628000000000e-10  5.697754142960e-01 
+ 5.728000000000e-10  1.994033695962e-01 
+ 5.828000000000e-10 -1.667424669503e-01 
+ 5.928000000000e-10 -4.143216611718e-01 
+ 6.028000000000e-10 -5.421291067647e-01 
+ 6.128000000000e-10 -6.188909595847e-01 
+ 6.228000000000e-10 -7.194310352535e-01 
+ 6.328000000000e-10 -8.117467342350e-01 
+ 6.428000000000e-10 -8.508333273630e-01 
+ 6.528000000000e-10 -7.942577903765e-01 
+ 6.628000000000e-10 -5.697836419865e-01 
+ 6.728000000000e-10 -1.993929431350e-01 
+ 6.828000000000e-10  1.667361734044e-01 
+ 6.928000000000e-10  4.143307053824e-01 
+ 7.028000000000e-10  5.421226813799e-01 
+ 7.128000000000e-10  6.189001833416e-01 
+ 7.228000000000e-10  7.194227358993e-01 
+ 7.328000000000e-10  8.117542266055e-01 
+ 7.428000000000e-10  8.508251070290e-01 
+ 7.528000000000e-10  7.942649966766e-01 
+ 7.628000000000e-10  5.697756363247e-01 
+ 7.728000000000e-10  1.993989977467e-01 
+ 7.828000000000e-10 -1.667434615441e-01 
+ 7.928000000000e-10 -4.143248161746e-01 
+ 8.028000000000e-10 -5.421295610790e-01 
+ 8.128000000000e-10 -6.188945163710e-01 
+ 8.228000000000e-10 -7.194289229798e-01 
+ 8.328000000000e-10 -8.117483413843e-01 
+ 8.428000000000e-10 -8.508308647988e-01 
+ 8.528000000000e-10 -7.942590780393e-01 
+ 8.628000000000e-10 -5.697822347435e-01 
+ 8.728000000000e-10 -1.993917000580e-01 
+ 8.828000000000e-10  1.667380255271e-01 
+ 8.928000000000e-10  4.143314131245e-01 
+ 9.028000000000e-10  5.421241182927e-01 
+ 9.128000000000e-10  6.189011822630e-01 
+ 9.228000000000e-10  7.194226089303e-01 
+ 9.328000000000e-10  8.117540798381e-01 
+ 9.428000000000e-10  8.508247577722e-01 
+ 9.528000000000e-10  7.942646412254e-01 
+ 9.628000000000e-10  5.697760282588e-01 
+ 9.728000000000e-10  1.993969946892e-01 
+ 9.828000000000e-10 -1.667434796269e-01 
+ 9.928000000000e-10 -4.143264352220e-01 
+ 1.000000000000e-09 -5.150731751424e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/conditions.yaml
new file mode 100644
index 00000000..35485a45
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 18
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_18
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb.sch
new file mode 100644
index 00000000..8d68286d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb_19.data
new file mode 100644
index 00000000..cfa0d051
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_core_tb_19.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.707988120441e-01 
+ 1.728000000000e-10  2.050562196689e-01 
+ 1.828000000000e-10 -1.568083182045e-01 
+ 1.928000000000e-10 -4.020696229917e-01 
+ 2.028000000000e-10 -5.270997867267e-01 
+ 2.128000000000e-10 -6.030122328411e-01 
+ 2.228000000000e-10 -7.060404303518e-01 
+ 2.328000000000e-10 -7.977729548420e-01 
+ 2.428000000000e-10 -8.357087979117e-01 
+ 2.528000000000e-10 -7.823438332914e-01 
+ 2.628000000000e-10 -5.641015035384e-01 
+ 2.728000000000e-10 -1.996979729386e-01 
+ 2.828000000000e-10  1.605395493177e-01 
+ 2.928000000000e-10  4.049019788065e-01 
+ 3.028000000000e-10  5.293349858313e-01 
+ 3.128000000000e-10  6.047755538782e-01 
+ 3.228000000000e-10  7.072083327509e-01 
+ 3.328000000000e-10  7.985177439850e-01 
+ 3.428000000000e-10  8.360745897587e-01 
+ 3.528000000000e-10  7.825643018760e-01 
+ 3.628000000000e-10  5.642043953033e-01 
+ 3.728000000000e-10  1.998026918934e-01 
+ 3.828000000000e-10 -1.604858693758e-01 
+ 3.928000000000e-10 -4.048299316522e-01 
+ 4.028000000000e-10 -5.293048172022e-01 
+ 4.128000000000e-10 -6.047267733392e-01 
+ 4.228000000000e-10 -7.071932602489e-01 
+ 4.328000000000e-10 -7.984844304353e-01 
+ 4.428000000000e-10 -8.360789616419e-01 
+ 4.528000000000e-10 -7.825446968704e-01 
+ 4.628000000000e-10 -5.642205462461e-01 
+ 4.728000000000e-10 -1.997755595675e-01 
+ 4.828000000000e-10  1.604765943145e-01 
+ 4.928000000000e-10  4.048512691297e-01 
+ 5.028000000000e-10  5.292953655278e-01 
+ 5.128000000000e-10  6.047472585148e-01 
+ 5.228000000000e-10  7.071773753770e-01 
+ 5.328000000000e-10  7.985008103891e-01 
+ 5.428000000000e-10  8.360621173440e-01 
+ 5.528000000000e-10  7.825604957102e-01 
+ 5.628000000000e-10  5.642042607216e-01 
+ 5.728000000000e-10  1.997857962408e-01 
+ 5.828000000000e-10 -1.604926267251e-01 
+ 5.928000000000e-10 -4.048407079574e-01 
+ 6.028000000000e-10 -5.293103597207e-01 
+ 6.128000000000e-10 -6.047374718328e-01 
+ 6.228000000000e-10 -7.071895246392e-01 
+ 6.328000000000e-10 -7.984887922220e-01 
+ 6.428000000000e-10 -8.360735876941e-01 
+ 6.528000000000e-10 -7.825482507809e-01 
+ 6.628000000000e-10 -5.642183473935e-01 
+ 6.728000000000e-10 -1.997692084041e-01 
+ 6.828000000000e-10  1.604823178167e-01 
+ 6.928000000000e-10  4.048548923992e-01 
+ 7.028000000000e-10  5.293001528657e-01 
+ 7.128000000000e-10  6.047514904939e-01 
+ 7.228000000000e-10  7.071767775245e-01 
+ 7.328000000000e-10  7.985010886851e-01 
+ 7.428000000000e-10  8.360609061049e-01 
+ 7.528000000000e-10  7.825602391468e-01 
+ 7.628000000000e-10  5.642057995328e-01 
+ 7.728000000000e-10  1.997793833692e-01 
+ 7.828000000000e-10 -1.604939026989e-01 
+ 7.928000000000e-10 -4.048452814924e-01 
+ 8.028000000000e-10 -5.293110935611e-01 
+ 8.128000000000e-10 -6.047422910037e-01 
+ 8.228000000000e-10 -7.071868576548e-01 
+ 8.328000000000e-10 -7.984914661054e-01 
+ 8.428000000000e-10 -8.360704549701e-01 
+ 8.528000000000e-10 -7.825505283213e-01 
+ 8.628000000000e-10 -5.642168951425e-01 
+ 8.728000000000e-10 -1.997675829904e-01 
+ 8.828000000000e-10  1.604850893678e-01 
+ 8.928000000000e-10  4.048557791622e-01 
+ 9.028000000000e-10  5.293024006551e-01 
+ 9.128000000000e-10  6.047526676189e-01 
+ 9.228000000000e-10  7.071769813422e-01 
+ 9.328000000000e-10  7.985009240492e-01 
+ 9.428000000000e-10  8.360608174754e-01 
+ 9.528000000000e-10  7.825597625659e-01 
+ 9.628000000000e-10  5.642070937767e-01 
+ 9.728000000000e-10  1.997763618165e-01 
+ 9.828000000000e-10 -1.604938267743e-01 
+ 9.928000000000e-10 -4.048476936234e-01 
+ 1.000000000000e-09 -5.033604123532e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/conditions.yaml
new file mode 100644
index 00000000..19fa5343
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 19
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_19
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb.sch
new file mode 100644
index 00000000..e7bdc939
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb_20.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb_20.data
new file mode 100644
index 00000000..696f2b8b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_core_tb_20.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.787258342535e-01 
+ 1.728000000000e-10  2.078017915173e-01 
+ 1.828000000000e-10 -1.622649468476e-01 
+ 1.928000000000e-10 -4.154784848215e-01 
+ 2.028000000000e-10 -5.503628241592e-01 
+ 2.128000000000e-10 -6.299323770996e-01 
+ 2.228000000000e-10 -7.254942323191e-01 
+ 2.328000000000e-10 -8.176578932007e-01 
+ 2.428000000000e-10 -8.600222409410e-01 
+ 2.528000000000e-10 -8.019093712422e-01 
+ 2.628000000000e-10 -5.756893793886e-01 
+ 2.728000000000e-10 -2.057606209176e-01 
+ 2.828000000000e-10  1.639197157563e-01 
+ 2.928000000000e-10  4.168841038800e-01 
+ 3.028000000000e-10  5.515424627408e-01 
+ 3.128000000000e-10  6.308336221978e-01 
+ 3.228000000000e-10  7.261208861559e-01 
+ 3.328000000000e-10  8.180354096547e-01 
+ 3.428000000000e-10  8.601969327831e-01 
+ 3.528000000000e-10  8.019450515145e-01 
+ 3.628000000000e-10  5.756806762770e-01 
+ 3.728000000000e-10  2.057351595047e-01 
+ 3.828000000000e-10 -1.639234125928e-01 
+ 3.928000000000e-10 -4.168916689126e-01 
+ 4.028000000000e-10 -5.515399403849e-01 
+ 4.128000000000e-10 -6.308421950132e-01 
+ 4.228000000000e-10 -7.261151591955e-01 
+ 4.328000000000e-10 -8.180409257235e-01 
+ 4.428000000000e-10 -8.601903753395e-01 
+ 4.528000000000e-10 -8.019506024478e-01 
+ 4.628000000000e-10 -5.756757498169e-01 
+ 4.728000000000e-10 -2.057370812605e-01 
+ 4.828000000000e-10  1.639284669376e-01 
+ 4.928000000000e-10  4.168895758092e-01 
+ 5.028000000000e-10  5.515444733402e-01 
+ 5.128000000000e-10  6.308408648378e-01 
+ 5.228000000000e-10  7.261175778597e-01 
+ 5.328000000000e-10  8.180376908128e-01 
+ 5.428000000000e-10  8.601923700088e-01 
+ 5.528000000000e-10  8.019470527506e-01 
+ 5.628000000000e-10  5.756789455974e-01 
+ 5.728000000000e-10  2.057316537746e-01 
+ 5.828000000000e-10 -1.639258645561e-01 
+ 5.928000000000e-10 -4.168940343704e-01 
+ 6.028000000000e-10 -5.515416140289e-01 
+ 6.128000000000e-10 -6.308456056710e-01 
+ 6.228000000000e-10 -7.261132930683e-01 
+ 6.328000000000e-10 -8.180415890619e-01 
+ 6.428000000000e-10 -8.601877913845e-01 
+ 6.528000000000e-10 -8.019507055326e-01 
+ 6.628000000000e-10 -5.756748223597e-01 
+ 6.728000000000e-10 -2.057339330851e-01 
+ 6.828000000000e-10  1.639294327626e-01 
+ 6.928000000000e-10  4.168918933453e-01 
+ 7.028000000000e-10  5.515448110547e-01 
+ 7.128000000000e-10  6.308438013344e-01 
+ 7.228000000000e-10  7.261156471026e-01 
+ 7.328000000000e-10  8.180389426729e-01 
+ 7.428000000000e-10  8.601899882644e-01 
+ 7.528000000000e-10  8.019478991926e-01 
+ 7.628000000000e-10  5.756775488816e-01 
+ 7.728000000000e-10  2.057303912125e-01 
+ 7.828000000000e-10 -1.639270777727e-01 
+ 7.928000000000e-10 -4.168949361223e-01 
+ 8.028000000000e-10 -5.515423789761e-01 
+ 8.128000000000e-10 -6.308469511551e-01 
+ 8.228000000000e-10 -7.261125857103e-01 
+ 8.328000000000e-10 -8.180418172660e-01 
+ 8.428000000000e-10 -8.601868536640e-01 
+ 8.528000000000e-10 -8.019506539776e-01 
+ 8.628000000000e-10 -5.756745040863e-01 
+ 8.728000000000e-10 -2.057325997968e-01 
+ 8.828000000000e-10  1.639296206310e-01 
+ 8.928000000000e-10  4.168929982528e-01 
+ 9.028000000000e-10  5.515447184418e-01 
+ 9.128000000000e-10  6.308451859194e-01 
+ 9.228000000000e-10  7.261146020976e-01 
+ 9.328000000000e-10  8.180396416883e-01 
+ 9.428000000000e-10  8.601888436252e-01 
+ 9.528000000000e-10  8.019484098509e-01 
+ 9.628000000000e-10  5.756767177581e-01 
+ 9.728000000000e-10  2.057300830001e-01 
+ 9.828000000000e-10 -1.639276725752e-01 
+ 9.928000000000e-10 -4.168951851932e-01 
+ 1.000000000000e-09 -5.223291820834e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/conditions.yaml
new file mode 100644
index 00000000..5ec3e86f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 20
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_20
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb.sch
new file mode 100644
index 00000000..fad2ff6b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb_21.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb_21.data
new file mode 100644
index 00000000..b199692b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_core_tb_21.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.573501255338e-01 
+ 1.728000000000e-10  2.075317226020e-01 
+ 1.828000000000e-10 -1.459750710281e-01 
+ 1.928000000000e-10 -3.981214724862e-01 
+ 2.028000000000e-10 -5.378144391949e-01 
+ 2.128000000000e-10 -6.222071778117e-01 
+ 2.228000000000e-10 -7.144656924256e-01 
+ 2.328000000000e-10 -7.957588475985e-01 
+ 2.428000000000e-10 -8.259944634024e-01 
+ 2.528000000000e-10 -7.639419051023e-01 
+ 2.628000000000e-10 -5.499582313836e-01 
+ 2.728000000000e-10 -2.015822705639e-01 
+ 2.828000000000e-10  1.503547149045e-01 
+ 2.928000000000e-10  4.016725871885e-01 
+ 3.028000000000e-10  5.406529598204e-01 
+ 3.128000000000e-10  6.244429748136e-01 
+ 3.228000000000e-10  7.159703736038e-01 
+ 3.328000000000e-10  7.967442303644e-01 
+ 3.428000000000e-10  8.264465978318e-01 
+ 3.528000000000e-10  7.642028659706e-01 
+ 3.628000000000e-10  5.500598536778e-01 
+ 3.728000000000e-10  2.017167809837e-01 
+ 3.828000000000e-10 -1.502994036069e-01 
+ 3.928000000000e-10 -4.015772846450e-01 
+ 4.028000000000e-10 -5.406194194587e-01 
+ 4.128000000000e-10 -6.243734224937e-01 
+ 4.228000000000e-10 -7.159615996115e-01 
+ 4.328000000000e-10 -7.966982014285e-01 
+ 4.428000000000e-10 -8.264613960108e-01 
+ 4.528000000000e-10 -7.641725666632e-01 
+ 4.628000000000e-10 -5.500862997678e-01 
+ 4.728000000000e-10 -2.016863380222e-01 
+ 4.828000000000e-10  1.502773228882e-01 
+ 4.928000000000e-10  4.016041852700e-01 
+ 5.028000000000e-10  5.405973091915e-01 
+ 5.128000000000e-10  6.243995261147e-01 
+ 5.228000000000e-10  7.159367954986e-01 
+ 5.328000000000e-10  7.967237369409e-01 
+ 5.428000000000e-10  8.264362767952e-01 
+ 5.528000000000e-10  7.641972989051e-01 
+ 5.628000000000e-10  5.500612169320e-01 
+ 5.728000000000e-10  2.017098008556e-01 
+ 5.828000000000e-10 -1.502994747055e-01 
+ 5.928000000000e-10 -4.015836624598e-01 
+ 6.028000000000e-10 -5.406181129288e-01 
+ 6.128000000000e-10 -6.243799299897e-01 
+ 6.228000000000e-10 -7.159574419629e-01 
+ 6.328000000000e-10 -7.967036557443e-01 
+ 6.428000000000e-10 -8.264562124237e-01 
+ 6.528000000000e-10 -7.641768324224e-01 
+ 6.628000000000e-10 -5.500832409355e-01 
+ 6.728000000000e-10 -2.016878835950e-01 
+ 6.828000000000e-10  1.502805147690e-01 
+ 6.928000000000e-10  4.016033959904e-01 
+ 7.028000000000e-10  5.405993862387e-01 
+ 7.128000000000e-10  6.243994053085e-01 
+ 7.228000000000e-10  7.159375001908e-01 
+ 7.328000000000e-10  7.967227911979e-01 
+ 7.428000000000e-10  8.264369695557e-01 
+ 7.528000000000e-10  7.641957504677e-01 
+ 7.628000000000e-10  5.500638388088e-01 
+ 7.728000000000e-10  2.017065810231e-01 
+ 7.828000000000e-10 -1.502977706940e-01 
+ 7.928000000000e-10 -4.015868518817e-01 
+ 8.028000000000e-10 -5.406159021220e-01 
+ 8.128000000000e-10 -6.243834226598e-01 
+ 8.228000000000e-10 -7.159542700032e-01 
+ 8.328000000000e-10 -7.967069113699e-01 
+ 8.428000000000e-10 -8.264528986398e-01 
+ 8.528000000000e-10 -7.641796598358e-01 
+ 8.628000000000e-10 -5.500810114131e-01 
+ 8.728000000000e-10 -2.016895461018e-01 
+ 8.828000000000e-10  1.502827695530e-01 
+ 8.928000000000e-10  4.016022282365e-01 
+ 9.028000000000e-10  5.406011687872e-01 
+ 9.128000000000e-10  6.243986267121e-01 
+ 9.228000000000e-10  7.159387803359e-01 
+ 9.328000000000e-10  7.967217157361e-01 
+ 9.428000000000e-10  8.264380732409e-01 
+ 9.528000000000e-10  7.641943142595e-01 
+ 9.628000000000e-10  5.500658668163e-01 
+ 9.728000000000e-10  2.017043552905e-01 
+ 9.828000000000e-10 -1.502962363926e-01 
+ 9.928000000000e-10 -4.015890294030e-01 
+ 1.000000000000e-09 -5.098048460363e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/conditions.yaml
new file mode 100644
index 00000000..ce8c1ed6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 21
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_21
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb.sch
new file mode 100644
index 00000000..4df7b4c3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb_22.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb_22.data
new file mode 100644
index 00000000..60989baa
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_core_tb_22.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.539342660958e-01 
+ 1.728000000000e-10  2.092356958505e-01 
+ 1.828000000000e-10 -1.399589402437e-01 
+ 1.928000000000e-10 -3.887664135754e-01 
+ 2.028000000000e-10 -5.242925922458e-01 
+ 2.128000000000e-10 -6.069418933180e-01 
+ 2.228000000000e-10 -7.009344183633e-01 
+ 2.328000000000e-10 -7.819154973681e-01 
+ 2.428000000000e-10 -8.115011787752e-01 
+ 2.528000000000e-10 -7.528782125237e-01 
+ 2.628000000000e-10 -5.449881732974e-01 
+ 2.728000000000e-10 -2.018085669996e-01 
+ 2.828000000000e-10  1.453371294429e-01 
+ 2.928000000000e-10  3.930046196046e-01 
+ 3.028000000000e-10  5.275952350978e-01 
+ 3.128000000000e-10  6.094983923496e-01 
+ 3.228000000000e-10  7.026430994561e-01 
+ 3.328000000000e-10  7.830459101342e-01 
+ 3.428000000000e-10  8.120643124066e-01 
+ 3.528000000000e-10  7.532542388222e-01 
+ 3.628000000000e-10  5.451889146656e-01 
+ 3.728000000000e-10  2.020380161925e-01 
+ 3.828000000000e-10 -1.452202245966e-01 
+ 3.928000000000e-10 -3.928550396378e-01 
+ 4.028000000000e-10 -5.275272038156e-01 
+ 4.128000000000e-10 -6.093963788491e-01 
+ 4.228000000000e-10 -7.026185076638e-01 
+ 4.328000000000e-10 -7.829822343256e-01 
+ 4.428000000000e-10 -8.120760322925e-01 
+ 4.528000000000e-10 -7.532137307257e-01 
+ 4.628000000000e-10 -5.452168897181e-01 
+ 4.728000000000e-10 -2.019975663161e-01 
+ 4.828000000000e-10  1.451970774770e-01 
+ 4.928000000000e-10  3.928886426712e-01 
+ 5.028000000000e-10  5.275035947470e-01 
+ 5.128000000000e-10  6.094279224341e-01 
+ 5.228000000000e-10  7.025906785817e-01 
+ 5.328000000000e-10  7.830125874729e-01 
+ 5.428000000000e-10  8.120474298427e-01 
+ 5.528000000000e-10  7.532431353399e-01 
+ 5.628000000000e-10  5.451877569897e-01 
+ 5.728000000000e-10  2.020249691554e-01 
+ 5.828000000000e-10 -1.452230860448e-01 
+ 5.928000000000e-10 -3.928644448798e-01 
+ 6.028000000000e-10 -5.275279936983e-01 
+ 6.128000000000e-10 -6.094050782075e-01 
+ 6.228000000000e-10 -7.026148963104e-01 
+ 6.328000000000e-10 -7.829886841749e-01 
+ 6.428000000000e-10 -8.120708569069e-01 
+ 6.528000000000e-10 -7.532187757848e-01 
+ 6.628000000000e-10 -5.452139572157e-01 
+ 6.728000000000e-10 -2.019983459359e-01 
+ 6.828000000000e-10  1.452010057661e-01 
+ 6.928000000000e-10  3.928879698340e-01 
+ 7.028000000000e-10  5.275064479083e-01 
+ 7.128000000000e-10  6.094280990005e-01 
+ 7.228000000000e-10  7.025917879356e-01 
+ 7.328000000000e-10  7.830113821989e-01 
+ 7.428000000000e-10  8.120485256383e-01 
+ 7.528000000000e-10  7.532412367972e-01 
+ 7.628000000000e-10  5.451912171970e-01 
+ 7.728000000000e-10  2.020204953427e-01 
+ 7.828000000000e-10 -1.452213117732e-01 
+ 7.928000000000e-10 -3.928683087954e-01 
+ 8.028000000000e-10 -5.275257546899e-01 
+ 8.128000000000e-10 -6.094092443434e-01 
+ 8.228000000000e-10 -7.026114152643e-01 
+ 8.328000000000e-10 -7.829924127838e-01 
+ 8.428000000000e-10 -8.120671951794e-01 
+ 8.528000000000e-10 -7.532220607865e-01 
+ 8.628000000000e-10 -5.452116115033e-01 
+ 8.728000000000e-10 -2.019999026099e-01 
+ 8.828000000000e-10  1.452037268076e-01 
+ 8.928000000000e-10  3.928866787286e-01 
+ 9.028000000000e-10  5.275085793908e-01 
+ 9.128000000000e-10  6.094272189130e-01 
+ 9.228000000000e-10  7.025932924679e-01 
+ 9.328000000000e-10  7.830100596429e-01 
+ 9.428000000000e-10  8.120498613680e-01 
+ 9.528000000000e-10  7.532395420815e-01 
+ 9.628000000000e-10  5.451937902395e-01 
+ 9.728000000000e-10  2.020175827840e-01 
+ 9.828000000000e-10 -1.452196157349e-01 
+ 9.928000000000e-10 -3.928709378362e-01 
+ 1.000000000000e-09 -4.979849828547e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/conditions.yaml
new file mode 100644
index 00000000..5cd09398
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 22
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_22
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb.sch
new file mode 100644
index 00000000..e2bfe757
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb_23.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb_23.data
new file mode 100644
index 00000000..208aa09a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_core_tb_23.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.609932954578e-01 
+ 1.728000000000e-10  2.135803595156e-01 
+ 1.828000000000e-10 -1.406795105233e-01 
+ 1.928000000000e-10 -3.985242549940e-01 
+ 2.028000000000e-10 -5.467902250198e-01 
+ 2.128000000000e-10 -6.349197102047e-01 
+ 2.228000000000e-10 -7.225601155251e-01 
+ 2.328000000000e-10 -8.022847270862e-01 
+ 2.428000000000e-10 -8.341174139963e-01 
+ 2.528000000000e-10 -7.703472968512e-01 
+ 2.628000000000e-10 -5.554753546701e-01 
+ 2.728000000000e-10 -2.092959847468e-01 
+ 2.828000000000e-10  1.439827087572e-01 
+ 2.928000000000e-10  4.013409764958e-01 
+ 3.028000000000e-10  5.491103575815e-01 
+ 3.128000000000e-10  6.367736171292e-01 
+ 3.228000000000e-10  7.238327114492e-01 
+ 3.328000000000e-10  8.031250424519e-01 
+ 3.428000000000e-10  8.344898451807e-01 
+ 3.528000000000e-10  7.705288945959e-01 
+ 3.628000000000e-10  5.555161552443e-01 
+ 3.728000000000e-10  2.093659332353e-01 
+ 3.828000000000e-10 -1.439645708780e-01 
+ 3.928000000000e-10 -4.012864243472e-01 
+ 4.028000000000e-10 -5.490981432908e-01 
+ 4.128000000000e-10 -6.367310776976e-01 
+ 4.228000000000e-10 -7.238327358891e-01 
+ 4.328000000000e-10 -8.030945225544e-01 
+ 4.428000000000e-10 -8.345032641498e-01 
+ 4.528000000000e-10 -7.705076814073e-01 
+ 4.628000000000e-10 -5.555368200040e-01 
+ 4.728000000000e-10 -2.093450233604e-01 
+ 4.828000000000e-10  1.439466188317e-01 
+ 4.928000000000e-10  4.013057839415e-01 
+ 5.028000000000e-10  5.490801810840e-01 
+ 5.128000000000e-10  6.367502973173e-01 
+ 5.228000000000e-10  7.238134370273e-01 
+ 5.328000000000e-10  8.031142213064e-01 
+ 5.428000000000e-10  8.344836920712e-01 
+ 5.528000000000e-10  7.705267055682e-01 
+ 5.628000000000e-10  5.555176728822e-01 
+ 5.728000000000e-10  2.093634169255e-01 
+ 5.828000000000e-10 -1.439633135713e-01 
+ 5.928000000000e-10 -4.012903718012e-01 
+ 6.028000000000e-10 -5.490957661747e-01 
+ 6.128000000000e-10 -6.367354259501e-01 
+ 6.228000000000e-10 -7.238289911799e-01 
+ 6.328000000000e-10 -8.030991093312e-01 
+ 6.428000000000e-10 -8.344987261970e-01 
+ 6.528000000000e-10 -7.705113506628e-01 
+ 6.628000000000e-10 -5.555339922038e-01 
+ 6.728000000000e-10 -2.093472747699e-01 
+ 6.828000000000e-10  1.439488143392e-01 
+ 6.928000000000e-10  4.013051006454e-01 
+ 7.028000000000e-10  5.490813620131e-01 
+ 7.128000000000e-10  6.367501696447e-01 
+ 7.228000000000e-10  7.238138408460e-01 
+ 7.328000000000e-10  8.031138234310e-01 
+ 7.428000000000e-10  8.344840024625e-01 
+ 7.528000000000e-10  7.705257750612e-01 
+ 7.628000000000e-10  5.555193682491e-01 
+ 7.728000000000e-10  2.093616154732e-01 
+ 7.828000000000e-10 -1.439618235384e-01 
+ 7.928000000000e-10 -4.012927107128e-01 
+ 8.028000000000e-10 -5.490937463184e-01 
+ 8.128000000000e-10 -6.367380404539e-01 
+ 8.228000000000e-10 -7.238264478501e-01 
+ 8.328000000000e-10 -8.031018435980e-01 
+ 8.428000000000e-10 -8.344959687989e-01 
+ 8.528000000000e-10 -7.705137100306e-01 
+ 8.628000000000e-10 -5.555321098787e-01 
+ 8.728000000000e-10 -2.093489927492e-01 
+ 8.828000000000e-10  1.439504269532e-01 
+ 8.928000000000e-10  4.013041525432e-01 
+ 9.028000000000e-10  5.490824887692e-01 
+ 9.128000000000e-10  6.367494882502e-01 
+ 9.228000000000e-10  7.238146944607e-01 
+ 9.328000000000e-10  8.031131051507e-01 
+ 9.428000000000e-10  8.344847147049e-01 
+ 9.528000000000e-10  7.705248067970e-01 
+ 9.628000000000e-10  5.555207970002e-01 
+ 9.728000000000e-10  2.093601819839e-01 
+ 9.828000000000e-10 -1.439605753448e-01 
+ 9.928000000000e-10 -4.012943342775e-01 
+ 1.000000000000e-09 -5.158218772706e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/conditions.yaml
new file mode 100644
index 00000000..4225835a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 23
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_23
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb.sch
new file mode 100644
index 00000000..5eb6d235
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb_24.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb_24.data
new file mode 100644
index 00000000..a8519464
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_core_tb_24.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.405028365217e-01 
+ 1.728000000000e-10  2.142897527484e-01 
+ 1.828000000000e-10 -1.231353412434e-01 
+ 1.928000000000e-10 -3.782847553257e-01 
+ 2.028000000000e-10 -5.290944707244e-01 
+ 2.128000000000e-10 -6.207435846591e-01 
+ 2.228000000000e-10 -7.069850917784e-01 
+ 2.328000000000e-10 -7.774395392863e-01 
+ 2.428000000000e-10 -7.982183108700e-01 
+ 2.528000000000e-10 -7.327456021571e-01 
+ 2.628000000000e-10 -5.310063164445e-01 
+ 2.728000000000e-10 -2.063297175293e-01 
+ 2.828000000000e-10  1.293176468137e-01 
+ 2.928000000000e-10  3.835270490977e-01 
+ 3.028000000000e-10  5.333180257023e-01 
+ 3.128000000000e-10  6.240938619865e-01 
+ 3.228000000000e-10  7.092802493907e-01 
+ 3.328000000000e-10  7.789607942300e-01 
+ 3.428000000000e-10  7.989234313230e-01 
+ 3.528000000000e-10  7.331763415294e-01 
+ 3.628000000000e-10  5.312045040772e-01 
+ 3.728000000000e-10  2.065847902134e-01 
+ 3.828000000000e-10 -1.291958906021e-01 
+ 3.928000000000e-10 -3.833411283085e-01 
+ 4.028000000000e-10 -5.332389173297e-01 
+ 4.128000000000e-10 -6.239588708494e-01 
+ 4.228000000000e-10 -7.092541595355e-01 
+ 4.328000000000e-10 -7.788766619073e-01 
+ 4.428000000000e-10 -7.989439817890e-01 
+ 4.528000000000e-10 -7.331237184970e-01 
+ 4.628000000000e-10 -5.312431858800e-01 
+ 4.728000000000e-10 -2.065354720445e-01 
+ 4.828000000000e-10  1.291604530900e-01 
+ 4.928000000000e-10  3.833851407049e-01 
+ 5.028000000000e-10  5.332033925163e-01 
+ 5.128000000000e-10  6.240009303805e-01 
+ 5.228000000000e-10  7.092156296740e-01 
+ 5.328000000000e-10  7.789178950697e-01 
+ 5.428000000000e-10  7.989050835748e-01 
+ 5.528000000000e-10  7.331635644704e-01 
+ 5.628000000000e-10  5.312038508238e-01 
+ 5.728000000000e-10  2.065745538625e-01 
+ 5.828000000000e-10 -1.291960705945e-01 
+ 5.928000000000e-10 -3.833509278886e-01 
+ 6.028000000000e-10 -5.332368573592e-01 
+ 6.128000000000e-10 -6.239679712691e-01 
+ 6.228000000000e-10 -7.092497084655e-01 
+ 6.328000000000e-10 -7.788845366535e-01 
+ 6.428000000000e-10 -7.989377629672e-01 
+ 6.528000000000e-10 -7.331298791234e-01 
+ 6.628000000000e-10 -5.312385744549e-01 
+ 6.728000000000e-10 -2.065399094583e-01 
+ 6.828000000000e-10  1.291646812354e-01 
+ 6.928000000000e-10  3.833822988637e-01 
+ 7.028000000000e-10  5.332062833028e-01 
+ 7.128000000000e-10  6.239988652624e-01 
+ 7.228000000000e-10  7.092181343784e-01 
+ 7.328000000000e-10  7.789155267181e-01 
+ 7.428000000000e-10  7.989074545455e-01 
+ 7.528000000000e-10  7.331605295450e-01 
+ 7.628000000000e-10  5.312080087648e-01 
+ 7.728000000000e-10  2.065705039315e-01 
+ 7.828000000000e-10 -1.291926212165e-01 
+ 7.928000000000e-10 -3.833551733065e-01 
+ 8.028000000000e-10 -5.332328436976e-01 
+ 8.128000000000e-10 -6.239725200032e-01 
+ 8.228000000000e-10 -7.092452956008e-01 
+ 8.328000000000e-10 -7.788891439389e-01 
+ 8.428000000000e-10 -7.989331916474e-01 
+ 8.528000000000e-10 -7.331340451631e-01 
+ 8.628000000000e-10 -5.312350772815e-01 
+ 8.728000000000e-10 -2.065433053799e-01 
+ 8.828000000000e-10  1.291679984852e-01 
+ 8.928000000000e-10  3.833797175156e-01 
+ 9.028000000000e-10  5.332088978421e-01 
+ 9.128000000000e-10  6.239966795455e-01 
+ 9.228000000000e-10  7.092206518532e-01 
+ 9.328000000000e-10  7.789132522577e-01 
+ 9.428000000000e-10  7.989096829455e-01 
+ 9.528000000000e-10  7.331579091452e-01 
+ 9.628000000000e-10  5.312112407565e-01 
+ 9.728000000000e-10  2.065672983353e-01 
+ 9.828000000000e-10 -1.291898675297e-01 
+ 9.928000000000e-10 -3.833583124064e-01 
+ 1.000000000000e-09 -4.991705375338e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/conditions.yaml
new file mode 100644
index 00000000..67c930af
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 24
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_24
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb.sch
new file mode 100644
index 00000000..b7993f6a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb_25.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb_25.data
new file mode 100644
index 00000000..39c04d30
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_core_tb_25.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.368449571564e-01 
+ 1.728000000000e-10  2.154696494615e-01 
+ 1.828000000000e-10 -1.180750667507e-01 
+ 1.928000000000e-10 -3.694801437498e-01 
+ 2.028000000000e-10 -5.157339685643e-01 
+ 2.128000000000e-10 -6.051803608378e-01 
+ 2.228000000000e-10 -6.923688047900e-01 
+ 2.328000000000e-10 -7.627278516708e-01 
+ 2.428000000000e-10 -7.836324050269e-01 
+ 2.528000000000e-10 -7.217390774868e-01 
+ 2.628000000000e-10 -5.258344598842e-01 
+ 2.728000000000e-10 -2.060622799160e-01 
+ 2.828000000000e-10  1.253068918672e-01 
+ 2.928000000000e-10  3.754763463876e-01 
+ 3.028000000000e-10  5.204513706872e-01 
+ 3.128000000000e-10  6.088547126517e-01 
+ 3.228000000000e-10  6.948747427610e-01 
+ 3.328000000000e-10  7.643967320598e-01 
+ 3.428000000000e-10  7.844541546789e-01 
+ 3.528000000000e-10  7.222905371020e-01 
+ 3.628000000000e-10  5.261436989659e-01 
+ 3.728000000000e-10  2.064244494061e-01 
+ 3.828000000000e-10 -1.251087630482e-01 
+ 3.928000000000e-10 -3.752230316774e-01 
+ 4.028000000000e-10 -5.203274407129e-01 
+ 4.128000000000e-10 -6.086807930540e-01 
+ 4.228000000000e-10 -6.948278459755e-01 
+ 4.328000000000e-10 -7.642927444658e-01 
+ 4.428000000000e-10 -7.844689558048e-01 
+ 4.528000000000e-10 -7.222270537973e-01 
+ 4.628000000000e-10 -5.261810188038e-01 
+ 4.728000000000e-10 -2.063649367923e-01 
+ 4.828000000000e-10  1.250740150254e-01 
+ 4.928000000000e-10  3.752740624702e-01 
+ 5.028000000000e-10  5.202917067072e-01 
+ 5.128000000000e-10  6.087280474834e-01 
+ 5.228000000000e-10  6.947875493975e-01 
+ 5.328000000000e-10  7.643381446772e-01 
+ 5.428000000000e-10  7.844278436925e-01 
+ 5.528000000000e-10  7.222707134126e-01 
+ 5.628000000000e-10  5.261386731045e-01 
+ 5.728000000000e-10  2.064078101390e-01 
+ 5.828000000000e-10 -1.251125509614e-01 
+ 5.928000000000e-10 -3.752362786491e-01 
+ 6.028000000000e-10 -5.203279553884e-01 
+ 6.128000000000e-10 -6.086920089480e-01 
+ 6.228000000000e-10 -6.948246280643e-01 
+ 6.328000000000e-10 -7.643013046090e-01 
+ 6.428000000000e-10 -7.844633201903e-01 
+ 6.528000000000e-10 -7.222336042293e-01 
+ 6.628000000000e-10 -5.261766512068e-01 
+ 6.728000000000e-10 -2.063691829929e-01 
+ 6.828000000000e-10  1.250784814444e-01 
+ 6.928000000000e-10  3.752708432251e-01 
+ 7.028000000000e-10  5.202949527958e-01 
+ 7.128000000000e-10  6.087256874770e-01 
+ 7.228000000000e-10  6.947904319095e-01 
+ 7.328000000000e-10  7.643352365607e-01 
+ 7.428000000000e-10  7.844306677783e-01 
+ 7.528000000000e-10  7.222672114429e-01 
+ 7.628000000000e-10  5.261433781551e-01 
+ 7.728000000000e-10  2.064029029490e-01 
+ 7.828000000000e-10 -1.251089390610e-01 
+ 7.928000000000e-10 -3.752408867518e-01 
+ 8.028000000000e-10 -5.203238706374e-01 
+ 8.128000000000e-10 -6.086968714396e-01 
+ 8.228000000000e-10 -6.948200705245e-01 
+ 8.328000000000e-10 -7.643060605343e-01 
+ 8.428000000000e-10 -7.844586734539e-01 
+ 8.528000000000e-10 -7.222379683755e-01 
+ 8.628000000000e-10 -5.261730442965e-01 
+ 8.728000000000e-10 -2.063725681788e-01 
+ 8.828000000000e-10  1.250820910423e-01 
+ 8.928000000000e-10  3.752680406761e-01 
+ 9.028000000000e-10  5.202978581562e-01 
+ 9.128000000000e-10  6.087233210610e-01 
+ 9.228000000000e-10  6.947932359489e-01 
+ 9.328000000000e-10  7.643326365950e-01 
+ 9.428000000000e-10  7.844331791786e-01 
+ 9.528000000000e-10  7.222642751837e-01 
+ 9.628000000000e-10  5.261469613157e-01 
+ 9.728000000000e-10  2.063991803079e-01 
+ 9.828000000000e-10 -1.251060220915e-01 
+ 9.928000000000e-10 -3.752443155305e-01 
+ 1.000000000000e-09 -4.875704709340e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/conditions.yaml
new file mode 100644
index 00000000..cba761bd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 25
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_25
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb.sch
new file mode 100644
index 00000000..3cfb1a1d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb.sch
@@ -0,0 +1,71 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb_26.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 0.3 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 0.3 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb_26.data
new file mode 100644
index 00000000..894f4c67
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_core_tb_26.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.436948212736e-01 
+ 1.728000000000e-10  2.205877879634e-01 
+ 1.828000000000e-10 -1.163348151974e-01 
+ 1.928000000000e-10 -3.771420921807e-01 
+ 2.028000000000e-10 -5.370108455130e-01 
+ 2.128000000000e-10 -6.331888427572e-01 
+ 2.228000000000e-10 -7.164762236683e-01 
+ 2.328000000000e-10 -7.851286946760e-01 
+ 2.428000000000e-10 -8.059531868761e-01 
+ 2.528000000000e-10 -7.384564800459e-01 
+ 2.628000000000e-10 -5.363144999221e-01 
+ 2.728000000000e-10 -2.144637665285e-01 
+ 2.828000000000e-10  1.212929793685e-01 
+ 2.928000000000e-10  3.815418180812e-01 
+ 3.028000000000e-10  5.406606883043e-01 
+ 3.128000000000e-10  6.361475176918e-01 
+ 3.228000000000e-10  7.185360719894e-01 
+ 3.328000000000e-10  7.865091736067e-01 
+ 3.428000000000e-10  8.065713749450e-01 
+ 3.528000000000e-10  7.387921596039e-01 
+ 3.628000000000e-10  5.364259512539e-01 
+ 3.728000000000e-10  2.146317863835e-01 
+ 3.828000000000e-10 -1.212295238309e-01 
+ 3.928000000000e-10 -3.814110096077e-01 
+ 4.028000000000e-10 -5.406166203788e-01 
+ 4.128000000000e-10 -6.360467438854e-01 
+ 4.228000000000e-10 -7.185257686739e-01 
+ 4.328000000000e-10 -7.864422304189e-01 
+ 4.428000000000e-10 -8.065937411296e-01 
+ 4.528000000000e-10 -7.387487319623e-01 
+ 4.628000000000e-10 -5.364619855530e-01 
+ 4.728000000000e-10 -2.145913861363e-01 
+ 4.828000000000e-10  1.211959412322e-01 
+ 4.928000000000e-10  3.814481551476e-01 
+ 5.028000000000e-10  5.405833390120e-01 
+ 5.128000000000e-10  6.360831449777e-01 
+ 5.228000000000e-10  7.184907253890e-01 
+ 5.328000000000e-10  7.864786648334e-01 
+ 5.428000000000e-10  8.065585198321e-01 
+ 5.528000000000e-10  7.387840006966e-01 
+ 5.628000000000e-10  5.364270346085e-01 
+ 5.728000000000e-10  2.146260338484e-01 
+ 5.828000000000e-10 -1.212277001077e-01 
+ 5.928000000000e-10 -3.814182410321e-01 
+ 6.028000000000e-10 -5.406130595607e-01 
+ 6.128000000000e-10 -6.360540210765e-01 
+ 6.228000000000e-10 -7.185209180994e-01 
+ 6.328000000000e-10 -7.864492678158e-01 
+ 6.428000000000e-10 -8.065874846616e-01 
+ 6.528000000000e-10 -7.387544794760e-01 
+ 6.628000000000e-10 -5.364572547805e-01 
+ 6.728000000000e-10 -2.145959871001e-01 
+ 6.828000000000e-10  1.211997934696e-01 
+ 6.928000000000e-10  3.814456726213e-01 
+ 7.028000000000e-10  5.405857946323e-01 
+ 7.128000000000e-10  6.360813265814e-01 
+ 7.228000000000e-10  7.184929266665e-01 
+ 7.328000000000e-10  7.864767243186e-01 
+ 7.428000000000e-10  8.065604357181e-01 
+ 7.528000000000e-10  7.387815158779e-01 
+ 7.628000000000e-10  5.364303644926e-01 
+ 7.728000000000e-10  2.146228844142e-01 
+ 7.828000000000e-10 -1.212245339809e-01 
+ 7.928000000000e-10 -3.814220075435e-01 
+ 8.028000000000e-10 -5.406092538148e-01 
+ 8.128000000000e-10 -6.360581238583e-01 
+ 8.228000000000e-10 -7.185168954112e-01 
+ 8.328000000000e-10 -7.864535273883e-01 
+ 8.428000000000e-10 -8.065831328643e-01 
+ 8.528000000000e-10 -7.387583532284e-01 
+ 8.628000000000e-10 -5.364538735708e-01 
+ 8.728000000000e-10 -2.145992968151e-01 
+ 8.828000000000e-10  1.212027591883e-01 
+ 8.928000000000e-10  3.814433789143e-01 
+ 9.028000000000e-10  5.405880431190e-01 
+ 9.128000000000e-10  6.360793794818e-01 
+ 9.228000000000e-10  7.184951630330e-01 
+ 9.328000000000e-10  7.864747526663e-01 
+ 9.428000000000e-10  8.065622905723e-01 
+ 9.528000000000e-10  7.387792872630e-01 
+ 9.628000000000e-10  5.364330391099e-01 
+ 9.728000000000e-10  2.146202349236e-01 
+ 9.828000000000e-10 -1.212220310216e-01 
+ 9.928000000000e-10 -3.814247853449e-01 
+ 1.000000000000e-09 -5.040490090913e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/conditions.yaml
new file mode 100644
index 00000000..9057abc1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 26
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/run_26
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/simulation_summary.csv
new file mode 100644
index 00000000..2f5f947b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/simulation_summary.csv
@@ -0,0 +1,28 @@
+run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing
+run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.952e-01, -6.044e-02, 0.182, …]",4.722e+09,0.709,1.418
+run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.648e-01, -3.672e-02, 0.198, …]",4.722e+09,0.693,1.386
+run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.227e-01, -8.540e-02, 0.161, …]",4.722e+09,0.722,1.444
+run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.752e-01, -5.371e-02, 0.179, …]",4.722e+09,0.692,1.383
+run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.482e-01, -3.259e-02, 0.193, …]",4.722e+09,0.672,1.345
+run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.027e-01, -8.046e-02, 0.156, …]",4.722e+09,0.706,1.412
+run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.659e-01, -5.659e-02, 0.167, …]",4.722e+09,0.669,1.338
+run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.411e-01, -3.745e-02, 0.179, …]",4.722e+09,0.648,1.295
+run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.916e-01, -8.207e-02, 0.144, …]",4.722e+09,0.685,1.371
+run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.397e-01, -2.046e-01, 0.131, …]",4.722e+09,0.807,1.614
+run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.293e-01, -2.034e-01, 0.125, …]",4.722e+09,0.789,1.577
+run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.474e-01, -2.088e-01, 0.131, …]",4.722e+09,0.819,1.638
+run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.050e-01, -1.958e-01, 0.120, …]",4.722e+09,0.771,1.543
+run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.935e-01, -1.929e-01, 0.116, …]",4.722e+09,0.753,1.505
+run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.133e-01, -2.032e-01, 0.114, …]",4.722e+09,0.783,1.566
+run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.765e-01, -1.934e-01, 0.103, …]",4.722e+09,0.743,1.486
+run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.643e-01, -1.890e-01, 0.101, …]",4.722e+09,0.725,1.450
+run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.853e-01, -2.024e-01, 9.500e-02, …]",4.722e+09,0.755,1.510
+run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.575, 0.203, -1.640e-01, …]",4.722e+09,0.851,1.702
+run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.571, 0.205, -1.568e-01, …]",4.722e+09,0.836,1.672
+run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.579, 0.208, -1.623e-01, …]",4.722e+09,0.860,1.720
+run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.557, 0.208, -1.460e-01, …]",4.722e+09,0.826,1.653
+run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.554, 0.209, -1.400e-01, …]",4.722e+09,0.812,1.624
+run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.561, 0.214, -1.407e-01, …]",4.722e+09,0.834,1.669
+run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.541, 0.214, -1.231e-01, …]",4.722e+09,0.799,1.598
+run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.537, 0.215, -1.181e-01, …]",4.722e+09,0.784,1.569
+run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.544, 0.221, -1.163e-01, …]",4.722e+09,0.807,1.613
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/simulation_summary.md
new file mode 100644
index 00000000..6401031e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/simulation_summary.md
@@ -0,0 +1,31 @@
+# Simulation Summary for CML divider frequency response
+
+| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing |
+| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: |
+| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.952e-01, -6.044e-02, 0.182, …] | 4.722e+09 | 0.709 | 1.418 |
+| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.648e-01, -3.672e-02, 0.198, …] | 4.722e+09 | 0.693 | 1.386 |
+| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.227e-01, -8.540e-02, 0.161, …] | 4.722e+09 | 0.722 | 1.444 |
+| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.752e-01, -5.371e-02, 0.179, …] | 4.722e+09 | 0.692 | 1.383 |
+| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.482e-01, -3.259e-02, 0.193, …] | 4.722e+09 | 0.672 | 1.345 |
+| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.027e-01, -8.046e-02, 0.156, …] | 4.722e+09 | 0.706 | 1.412 |
+| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.659e-01, -5.659e-02, 0.167, …] | 4.722e+09 | 0.669 | 1.338 |
+| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.411e-01, -3.745e-02, 0.179, …] | 4.722e+09 | 0.648 | 1.295 |
+| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.916e-01, -8.207e-02, 0.144, …] | 4.722e+09 | 0.685 | 1.371 |
+| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.397e-01, -2.046e-01, 0.131, …] | 4.722e+09 | 0.807 | 1.614 |
+| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.293e-01, -2.034e-01, 0.125, …] | 4.722e+09 | 0.789 | 1.577 |
+| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.474e-01, -2.088e-01, 0.131, …] | 4.722e+09 | 0.819 | 1.638 |
+| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.050e-01, -1.958e-01, 0.120, …] | 4.722e+09 | 0.771 | 1.543 |
+| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.935e-01, -1.929e-01, 0.116, …] | 4.722e+09 | 0.753 | 1.505 |
+| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.133e-01, -2.032e-01, 0.114, …] | 4.722e+09 | 0.783 | 1.566 |
+| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.765e-01, -1.934e-01, 0.103, …] | 4.722e+09 | 0.743 | 1.486 |
+| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.643e-01, -1.890e-01, 0.101, …] | 4.722e+09 | 0.725 | 1.450 |
+| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.853e-01, -2.024e-01, 9.500e-02, …] | 4.722e+09 | 0.755 | 1.510 |
+| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.575, 0.203, -1.640e-01, …] | 4.722e+09 | 0.851 | 1.702 |
+| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.571, 0.205, -1.568e-01, …] | 4.722e+09 | 0.836 | 1.672 |
+| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.579, 0.208, -1.623e-01, …] | 4.722e+09 | 0.860 | 1.720 |
+| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.557, 0.208, -1.460e-01, …] | 4.722e+09 | 0.826 | 1.653 |
+| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.554, 0.209, -1.400e-01, …] | 4.722e+09 | 0.812 | 1.624 |
+| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.561, 0.214, -1.407e-01, …] | 4.722e+09 | 0.834 | 1.669 |
+| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.541, 0.214, -1.231e-01, …] | 4.722e+09 | 0.799 | 1.598 |
+| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.537, 0.215, -1.181e-01, …] | 4.722e+09 | 0.784 | 1.569 |
+| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.544, 0.221, -1.163e-01, …] | 4.722e+09 | 0.807 | 1.613 |
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/vo_diff_vs_time.png
new file mode 100644
index 00000000..64d1b808
Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/parameters/ac_params/vo_diff_vs_time.png differ
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/summary.md
new file mode 100644
index 00000000..a11c2c65
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-40-01/summary.md
@@ -0,0 +1,11 @@
+
+# CACE Summary for CML_divider
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |  4.722 GHz |      5.0 GHz |  4.722 GHz |      5.2 GHz |  4.722 GHz |   Pass ✅    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |    0.648 V |        0.4 V |    0.771 V |        0.6 V |    0.860 V |   Fail ❌    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |    1.295 V |        0.8 V |    1.543 V |        1.2 V |    1.720 V |   Fail ❌    |
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/CML_core_tb.sch
new file mode 100644
index 00000000..4f2cfbbf
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb.sch
new file mode 100644
index 00000000..8da9de98
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb_0.data
new file mode 100644
index 00000000..f59ab2f0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_core_tb_0.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.952325246460e-01 
+ 1.728000000000e-10 -6.043942197180e-02 
+ 1.828000000000e-10  1.817064006719e-01 
+ 1.928000000000e-10  3.985392356515e-01 
+ 2.028000000000e-10  5.562505249699e-01 
+ 2.128000000000e-10  6.572874178466e-01 
+ 2.228000000000e-10  7.087352858161e-01 
+ 2.328000000000e-10  7.029522511861e-01 
+ 2.428000000000e-10  6.344368312078e-01 
+ 2.528000000000e-10  5.013241237787e-01 
+ 2.628000000000e-10  3.030080742176e-01 
+ 2.728000000000e-10  6.578821975768e-02 
+ 2.828000000000e-10 -1.781586778972e-01 
+ 2.928000000000e-10 -3.964040373442e-01 
+ 3.028000000000e-10 -5.555461653242e-01 
+ 3.128000000000e-10 -6.571022283471e-01 
+ 3.228000000000e-10 -7.092808909864e-01 
+ 3.328000000000e-10 -7.040843150938e-01 
+ 3.428000000000e-10 -6.362469325195e-01 
+ 3.528000000000e-10 -5.032364212786e-01 
+ 3.628000000000e-10 -3.051350358226e-01 
+ 3.728000000000e-10 -6.762904380974e-02 
+ 3.828000000000e-10  1.763878132349e-01 
+ 3.928000000000e-10  3.951284969670e-01 
+ 4.028000000000e-10  5.545978983505e-01 
+ 4.128000000000e-10  6.566315830069e-01 
+ 4.228000000000e-10  7.089962487465e-01 
+ 4.328000000000e-10  7.042633111532e-01 
+ 4.428000000000e-10  6.365365170049e-01 
+ 4.528000000000e-10  5.037912579488e-01 
+ 4.628000000000e-10  3.056253251435e-01 
+ 4.728000000000e-10  6.823087043489e-02 
+ 4.828000000000e-10 -1.759620590786e-01 
+ 4.928000000000e-10 -3.946766675460e-01 
+ 5.028000000000e-10 -5.543918551335e-01 
+ 5.128000000000e-10 -6.564106038653e-01 
+ 5.228000000000e-10 -7.089804674794e-01 
+ 5.328000000000e-10 -7.042284637667e-01 
+ 5.428000000000e-10 -6.366831677063e-01 
+ 5.528000000000e-10 -5.038654128054e-01 
+ 5.628000000000e-10 -3.058301627321e-01 
+ 5.728000000000e-10 -6.832081314378e-02 
+ 5.828000000000e-10  1.757744687450e-01 
+ 5.928000000000e-10  3.946207346164e-01 
+ 6.028000000000e-10  5.542681653143e-01 
+ 6.128000000000e-10  6.564162326939e-01 
+ 6.228000000000e-10  7.089102158365e-01 
+ 6.328000000000e-10  7.042850183822e-01 
+ 6.428000000000e-10  6.366586213363e-01 
+ 6.528000000000e-10  5.039505543903e-01 
+ 6.628000000000e-10  3.058219717524e-01 
+ 6.728000000000e-10  6.840961740524e-02 
+ 6.828000000000e-10 -1.757862033444e-01 
+ 6.928000000000e-10 -3.945467987447e-01 
+ 7.028000000000e-10 -5.542929102277e-01 
+ 7.128000000000e-10 -6.563603422698e-01 
+ 7.228000000000e-10 -7.089481650220e-01 
+ 7.328000000000e-10 -7.042424683005e-01 
+ 7.428000000000e-10 -6.367078290897e-01 
+ 7.528000000000e-10 -5.039165471509e-01 
+ 7.628000000000e-10 -3.058753018579e-01 
+ 7.728000000000e-10 -6.837707225292e-02 
+ 7.828000000000e-10  1.757345833407e-01 
+ 7.928000000000e-10  3.945785215449e-01 
+ 8.028000000000e-10  5.542482652542e-01 
+ 8.128000000000e-10  6.563959408481e-01 
+ 8.228000000000e-10  7.089082113076e-01 
+ 8.328000000000e-10  7.042817797830e-01 
+ 8.428000000000e-10  6.366719399828e-01 
+ 8.528000000000e-10  5.039573608246e-01 
+ 8.628000000000e-10  3.058408732486e-01 
+ 8.728000000000e-10  6.841772818469e-02 
+ 8.828000000000e-10 -1.757686495942e-01 
+ 8.928000000000e-10 -3.945419964750e-01 
+ 9.028000000000e-10 -5.542809328797e-01 
+ 9.128000000000e-10 -6.563614885531e-01 
+ 9.228000000000e-10 -7.089411806967e-01 
+ 9.328000000000e-10 -7.042479976407e-01 
+ 9.428000000000e-10 -6.367051444468e-01 
+ 9.528000000000e-10 -5.039245834310e-01 
+ 9.628000000000e-10 -3.058742220339e-01 
+ 9.728000000000e-10 -6.838526492008e-02 
+ 9.828000000000e-10  1.757358039920e-01 
+ 9.928000000000e-10  3.945718167364e-01 
+ 1.000000000000e-09  5.155910006549e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/conditions.yaml
new file mode 100644
index 00000000..92224cf6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 0
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_00
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb.sch
new file mode 100644
index 00000000..a33acfdf
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb_1.data
new file mode 100644
index 00000000..e3f59bbb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_core_tb_1.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.647956442563e-01 
+ 1.728000000000e-10 -3.672466403620e-02 
+ 1.828000000000e-10  1.978055322165e-01 
+ 1.928000000000e-10  4.056017943518e-01 
+ 2.028000000000e-10  5.547344088879e-01 
+ 2.128000000000e-10  6.487490848065e-01 
+ 2.228000000000e-10  6.923653634957e-01 
+ 2.328000000000e-10  6.780886353961e-01 
+ 2.428000000000e-10  6.039598047192e-01 
+ 2.528000000000e-10  4.698168410475e-01 
+ 2.628000000000e-10  2.751260896566e-01 
+ 2.728000000000e-10  4.430157580525e-02 
+ 2.828000000000e-10 -1.925038311835e-01 
+ 2.928000000000e-10 -4.023301580756e-01 
+ 3.028000000000e-10 -5.533152551341e-01 
+ 3.128000000000e-10 -6.481954476962e-01 
+ 3.228000000000e-10 -6.930655672739e-01 
+ 3.328000000000e-10 -6.800540209913e-01 
+ 3.428000000000e-10 -6.070129146880e-01 
+ 3.528000000000e-10 -4.732295235615e-01 
+ 3.628000000000e-10 -2.788311309623e-01 
+ 3.728000000000e-10 -4.769207273319e-02 
+ 3.828000000000e-10  1.893739393662e-01 
+ 3.928000000000e-10  3.999895682405e-01 
+ 4.028000000000e-10  5.516914161753e-01 
+ 4.128000000000e-10  6.473194453459e-01 
+ 4.228000000000e-10  6.926967113745e-01 
+ 4.328000000000e-10  6.804409619078e-01 
+ 4.428000000000e-10  6.077344291363e-01 
+ 4.528000000000e-10  4.743209278754e-01 
+ 4.628000000000e-10  2.799315218230e-01 
+ 4.728000000000e-10  4.887682675205e-02 
+ 4.828000000000e-10 -1.884058832182e-01 
+ 4.928000000000e-10 -3.991237321070e-01 
+ 5.028000000000e-10 -5.511979674959e-01 
+ 5.128000000000e-10 -6.469402879887e-01 
+ 5.228000000000e-10 -6.926225993557e-01 
+ 5.328000000000e-10 -6.804805060919e-01 
+ 5.428000000000e-10 -6.080204415279e-01 
+ 5.528000000000e-10 -4.745961817340e-01 
+ 5.628000000000e-10 -2.803459413605e-01 
+ 5.728000000000e-10 -4.918721233066e-02 
+ 5.828000000000e-10  1.880320213273e-01 
+ 5.928000000000e-10  3.989072784961e-01 
+ 6.028000000000e-10  5.509784832100e-01 
+ 6.128000000000e-10  6.468776696433e-01 
+ 6.228000000000e-10  6.925382949500e-01 
+ 6.328000000000e-10  6.805520167761e-01 
+ 6.428000000000e-10  6.080522625696e-01 
+ 6.528000000000e-10  4.747422384222e-01 
+ 6.628000000000e-10  2.804194075907e-01 
+ 6.728000000000e-10  4.934414267878e-02 
+ 6.828000000000e-10 -1.879699706397e-01 
+ 6.928000000000e-10 -3.987854446736e-01 
+ 7.028000000000e-10 -5.509613139230e-01 
+ 7.128000000000e-10 -6.468062697707e-01 
+ 7.228000000000e-10 -6.925630874809e-01 
+ 7.328000000000e-10 -6.805223964692e-01 
+ 7.428000000000e-10 -6.081132322697e-01 
+ 7.528000000000e-10 -4.747366406660e-01 
+ 7.628000000000e-10 -2.804933490724e-01 
+ 7.728000000000e-10 -4.934235519722e-02 
+ 7.828000000000e-10  1.879006367827e-01 
+ 7.928000000000e-10  3.987938070562e-01 
+ 8.028000000000e-10  5.509093463144e-01 
+ 8.128000000000e-10  6.468293959909e-01 
+ 8.228000000000e-10  6.925252291894e-01 
+ 8.328000000000e-10  6.805590879185e-01 
+ 8.428000000000e-10  6.080875904937e-01 
+ 8.528000000000e-10  4.747803907956e-01 
+ 8.628000000000e-10  2.804721530083e-01 
+ 8.728000000000e-10  4.938687520288e-02 
+ 8.828000000000e-10 -1.879222775604e-01 
+ 8.928000000000e-10 -3.987554695640e-01 
+ 9.028000000000e-10 -5.509333914335e-01 
+ 9.128000000000e-10 -6.467969990881e-01 
+ 9.228000000000e-10 -6.925530415231e-01 
+ 9.328000000000e-10 -6.805304150604e-01 
+ 9.428000000000e-10 -6.081187600045e-01 
+ 9.528000000000e-10 -4.747542418837e-01 
+ 9.628000000000e-10 -2.805045225795e-01 
+ 9.728000000000e-10 -4.936125388638e-02 
+ 9.828000000000e-10  1.878908530872e-01 
+ 9.928000000000e-10  3.987795364060e-01 
+ 1.000000000000e-09  5.142017254263e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/conditions.yaml
new file mode 100644
index 00000000..6f7af265
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 1
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_01
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb.sch
new file mode 100644
index 00000000..df03a06a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb_2.data
new file mode 100644
index 00000000..69b4790a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_core_tb_2.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.226907107526e-01 
+ 1.728000000000e-10 -8.539968284410e-02 
+ 1.828000000000e-10  1.614480909662e-01 
+ 1.928000000000e-10  3.869191924745e-01 
+ 2.028000000000e-10  5.540483396157e-01 
+ 2.128000000000e-10  6.620167995175e-01 
+ 2.228000000000e-10  7.202634748901e-01 
+ 2.328000000000e-10  7.212523007105e-01 
+ 2.428000000000e-10  6.566979396260e-01 
+ 2.528000000000e-10  5.250303609426e-01 
+ 2.628000000000e-10  3.265092852166e-01 
+ 2.728000000000e-10  8.707604756771e-02 
+ 2.828000000000e-10 -1.611600424348e-01 
+ 2.928000000000e-10 -3.873238626333e-01 
+ 3.028000000000e-10 -5.550746884823e-01 
+ 3.128000000000e-10 -6.629366269634e-01 
+ 3.228000000000e-10 -7.212894794449e-01 
+ 3.328000000000e-10 -7.220878341254e-01 
+ 3.428000000000e-10 -6.576651735802e-01 
+ 3.528000000000e-10 -5.257535323793e-01 
+ 3.628000000000e-10 -3.273054874384e-01 
+ 3.728000000000e-10 -8.759901468452e-02 
+ 3.828000000000e-10  1.605580394287e-01 
+ 3.928000000000e-10  3.869863823107e-01 
+ 4.028000000000e-10  5.547303069787e-01 
+ 4.128000000000e-10  6.628461833305e-01 
+ 4.228000000000e-10  7.211466820779e-01 
+ 4.328000000000e-10  7.221995653822e-01 
+ 4.428000000000e-10  6.577128147927e-01 
+ 4.528000000000e-10  5.259884868760e-01 
+ 4.628000000000e-10  3.274163471898e-01 
+ 4.728000000000e-10  8.784541550780e-02 
+ 4.828000000000e-10 -1.604682108624e-01 
+ 4.928000000000e-10 -3.867888973241e-01 
+ 5.028000000000e-10 -5.547066546217e-01 
+ 5.128000000000e-10 -6.627253094524e-01 
+ 5.228000000000e-10 -7.211826888209e-01 
+ 5.328000000000e-10 -7.221369141817e-01 
+ 5.428000000000e-10 -6.577994031943e-01 
+ 5.528000000000e-10 -5.259620192587e-01 
+ 5.628000000000e-10 -3.275201865204e-01 
+ 5.728000000000e-10 -8.782404636233e-02 
+ 5.828000000000e-10  1.603689538405e-01 
+ 5.928000000000e-10  3.868153343854e-01 
+ 6.028000000000e-10  5.546284247412e-01 
+ 6.128000000000e-10  6.627691182366e-01 
+ 6.228000000000e-10  7.211205707397e-01 
+ 6.328000000000e-10  7.221945096033e-01 
+ 6.428000000000e-10  6.577508134366e-01 
+ 6.528000000000e-10  5.260261908485e-01 
+ 6.628000000000e-10  3.274760111912e-01 
+ 6.728000000000e-10  8.788851273294e-02 
+ 6.828000000000e-10 -1.604138329037e-01 
+ 6.928000000000e-10 -3.867579820075e-01 
+ 7.028000000000e-10 -5.546733587088e-01 
+ 7.128000000000e-10 -6.627166397254e-01 
+ 7.228000000000e-10 -7.211676696649e-01 
+ 7.328000000000e-10 -7.221448613305e-01 
+ 7.428000000000e-10 -6.577993970261e-01 
+ 7.528000000000e-10 -5.259796511606e-01 
+ 7.628000000000e-10 -3.275252420812e-01 
+ 7.728000000000e-10 -8.784270745333e-02 
+ 7.828000000000e-10  1.603648729372e-01 
+ 7.928000000000e-10  3.868003178892e-01 
+ 8.028000000000e-10  5.546284703905e-01 
+ 8.128000000000e-10  6.627594909397e-01 
+ 8.228000000000e-10  7.211247368625e-01 
+ 8.328000000000e-10  7.221884517678e-01 
+ 8.428000000000e-10  6.577581123739e-01 
+ 8.528000000000e-10  5.260226393584e-01 
+ 8.628000000000e-10  3.274844581735e-01 
+ 8.728000000000e-10  8.788515759553e-02 
+ 8.828000000000e-10 -1.604054537172e-01 
+ 8.928000000000e-10 -3.867616376768e-01 
+ 9.028000000000e-10 -5.546662826942e-01 
+ 9.128000000000e-10 -6.627215467888e-01 
+ 9.228000000000e-10 -7.211618152183e-01 
+ 9.328000000000e-10 -7.221504122635e-01 
+ 9.428000000000e-10 -6.577943183983e-01 
+ 9.528000000000e-10 -5.259856282734e-01 
+ 9.628000000000e-10 -3.275204867996e-01 
+ 9.728000000000e-10 -8.784851998896e-02 
+ 9.828000000000e-10  1.603694682536e-01 
+ 9.928000000000e-10  3.867951846118e-01 
+ 1.000000000000e-09  5.139507493642e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/conditions.yaml
new file mode 100644
index 00000000..e82cc1c3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 2
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_02
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb.sch
new file mode 100644
index 00000000..e892badb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb_3.data
new file mode 100644
index 00000000..fedc9e2a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_core_tb_3.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.752371518652e-01 
+ 1.728000000000e-10 -5.371376319543e-02 
+ 1.828000000000e-10  1.789877413053e-01 
+ 1.928000000000e-10  3.904548691103e-01 
+ 2.028000000000e-10  5.481842948229e-01 
+ 2.128000000000e-10  6.473880529986e-01 
+ 2.228000000000e-10  6.910106576952e-01 
+ 2.328000000000e-10  6.747515328639e-01 
+ 2.428000000000e-10  5.993982850131e-01 
+ 2.528000000000e-10  4.678235295331e-01 
+ 2.628000000000e-10  2.811940191144e-01 
+ 2.728000000000e-10  5.749892092429e-02 
+ 2.828000000000e-10 -1.768703468756e-01 
+ 2.928000000000e-10 -3.894327299011e-01 
+ 3.028000000000e-10 -5.481462871223e-01 
+ 3.128000000000e-10 -6.476233959034e-01 
+ 3.228000000000e-10 -6.918267741740e-01 
+ 3.328000000000e-10 -6.759891610513e-01 
+ 3.428000000000e-10 -6.011477081233e-01 
+ 3.528000000000e-10 -4.695436066174e-01 
+ 3.628000000000e-10 -2.830251877311e-01 
+ 3.728000000000e-10 -5.907673776650e-02 
+ 3.828000000000e-10  1.753349861707e-01 
+ 3.928000000000e-10  3.883274219019e-01 
+ 4.028000000000e-10  5.473035177189e-01 
+ 4.128000000000e-10  6.472356324664e-01 
+ 4.228000000000e-10  6.916308158427e-01 
+ 4.328000000000e-10  6.762268077787e-01 
+ 4.428000000000e-10  6.014684070962e-01 
+ 4.528000000000e-10  4.700895666681e-01 
+ 4.628000000000e-10  2.834862741746e-01 
+ 4.728000000000e-10  5.964855757082e-02 
+ 4.828000000000e-10 -1.749274761915e-01 
+ 4.928000000000e-10 -3.878897710558e-01 
+ 5.028000000000e-10 -5.470986037433e-01 
+ 5.128000000000e-10 -6.470272164409e-01 
+ 5.228000000000e-10 -6.916322065746e-01 
+ 5.328000000000e-10 -6.762158687864e-01 
+ 5.428000000000e-10 -6.016311330158e-01 
+ 5.528000000000e-10 -4.701782346337e-01 
+ 5.628000000000e-10 -2.836941639082e-01 
+ 5.728000000000e-10 -5.974768838543e-02 
+ 5.828000000000e-10  1.747352099095e-01 
+ 5.928000000000e-10  3.878245260251e-01 
+ 6.028000000000e-10  5.469715931678e-01 
+ 6.128000000000e-10  6.470284806517e-01 
+ 6.228000000000e-10  6.915679621080e-01 
+ 6.328000000000e-10  6.762768333485e-01 
+ 6.428000000000e-10  6.016163496453e-01 
+ 6.528000000000e-10  4.702674812943e-01 
+ 6.628000000000e-10  2.836938506434e-01 
+ 6.728000000000e-10  5.983990401354e-02 
+ 6.828000000000e-10 -1.747391664584e-01 
+ 6.928000000000e-10 -3.877472828580e-01 
+ 7.028000000000e-10 -5.469903889528e-01 
+ 7.128000000000e-10 -6.469730360721e-01 
+ 7.228000000000e-10 -6.916047287716e-01 
+ 7.328000000000e-10 -6.762386026180e-01 
+ 7.428000000000e-10 -6.016669907083e-01 
+ 7.528000000000e-10 -4.702390118128e-01 
+ 7.628000000000e-10 -2.837481181728e-01 
+ 7.728000000000e-10 -5.981248689037e-02 
+ 7.828000000000e-10  1.746867337354e-01 
+ 7.928000000000e-10  3.877749638679e-01 
+ 8.028000000000e-10  5.469462314077e-01 
+ 8.128000000000e-10  6.470055622974e-01 
+ 8.228000000000e-10  6.915665740520e-01 
+ 8.328000000000e-10  6.762766371031e-01 
+ 8.428000000000e-10  6.016337946720e-01 
+ 8.528000000000e-10  4.702787360349e-01 
+ 8.628000000000e-10  2.837166478209e-01 
+ 8.728000000000e-10  5.985233152722e-02 
+ 8.828000000000e-10 -1.747180248353e-01 
+ 8.928000000000e-10 -3.877389392165e-01 
+ 9.028000000000e-10 -5.469764940938e-01 
+ 9.128000000000e-10 -6.469724949526e-01 
+ 9.228000000000e-10 -6.915980610397e-01 
+ 9.328000000000e-10 -6.762447762615e-01 
+ 9.428000000000e-10 -6.016660865709e-01 
+ 9.528000000000e-10 -4.702484057793e-01 
+ 9.628000000000e-10 -2.837489236123e-01 
+ 9.728000000000e-10 -5.982216431619e-02 
+ 9.828000000000e-10  1.746862818107e-01 
+ 9.928000000000e-10  3.877670239311e-01 
+ 1.000000000000e-09  5.084292112944e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/conditions.yaml
new file mode 100644
index 00000000..ecdc3782
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 3
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_03
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb.sch
new file mode 100644
index 00000000..0bbf7b60
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb_4.data
new file mode 100644
index 00000000..4898dcc8
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_core_tb_4.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.482257947455e-01 
+ 1.728000000000e-10 -3.259266550036e-02 
+ 1.828000000000e-10  1.930322087844e-01 
+ 1.928000000000e-10  3.960886599474e-01 
+ 2.028000000000e-10  5.450058997505e-01 
+ 2.128000000000e-10  6.360387116800e-01 
+ 2.228000000000e-10  6.712975422190e-01 
+ 2.328000000000e-10  6.474938983982e-01 
+ 2.428000000000e-10  5.679706274704e-01 
+ 2.528000000000e-10  4.364781736218e-01 
+ 2.628000000000e-10  2.536409133725e-01 
+ 2.728000000000e-10  3.555786929817e-02 
+ 2.828000000000e-10 -1.919150168478e-01 
+ 2.928000000000e-10 -3.960490843585e-01 
+ 3.028000000000e-10 -5.456465197220e-01 
+ 3.128000000000e-10 -6.367232933250e-01 
+ 3.228000000000e-10 -6.725166925877e-01 
+ 3.328000000000e-10 -6.491812984547e-01 
+ 3.428000000000e-10 -5.701612342484e-01 
+ 3.528000000000e-10 -4.386195239579e-01 
+ 3.628000000000e-10 -2.558666299298e-01 
+ 3.728000000000e-10 -3.750940439386e-02 
+ 3.828000000000e-10  1.900731677010e-01 
+ 3.928000000000e-10  3.947279065049e-01 
+ 4.028000000000e-10  5.446879536498e-01 
+ 4.128000000000e-10  6.362937598492e-01 
+ 4.228000000000e-10  6.723764816130e-01 
+ 4.328000000000e-10  6.495551727740e-01 
+ 4.428000000000e-10  5.706690754638e-01 
+ 4.528000000000e-10  4.393690386282e-01 
+ 4.628000000000e-10  2.565445890136e-01 
+ 4.728000000000e-10  3.828939038749e-02 
+ 4.828000000000e-10 -1.894747026650e-01 
+ 4.928000000000e-10 -3.941469427019e-01 
+ 5.028000000000e-10 -5.443881652157e-01 
+ 5.128000000000e-10 -6.360424686566e-01 
+ 5.228000000000e-10 -6.723795425302e-01 
+ 5.328000000000e-10 -6.495951074105e-01 
+ 5.428000000000e-10 -5.709049111674e-01 
+ 5.528000000000e-10 -4.395480856778e-01 
+ 5.628000000000e-10 -2.568451405700e-01 
+ 5.728000000000e-10 -3.848386295175e-02 
+ 5.828000000000e-10  1.891998017504e-01 
+ 5.928000000000e-10  3.940128253458e-01 
+ 6.028000000000e-10  5.442195759360e-01 
+ 6.128000000000e-10  6.360190076123e-01 
+ 6.228000000000e-10  6.723154692419e-01 
+ 6.328000000000e-10  6.496722035130e-01 
+ 6.428000000000e-10  5.709215560836e-01 
+ 6.528000000000e-10  4.396716365902e-01 
+ 6.628000000000e-10  2.568848555761e-01 
+ 6.728000000000e-10  3.861258812938e-02 
+ 6.828000000000e-10 -1.891673406027e-01 
+ 6.928000000000e-10 -3.939096487469e-01 
+ 7.028000000000e-10 -5.442185154541e-01 
+ 7.128000000000e-10 -6.359555029215e-01 
+ 7.228000000000e-10 -6.723494769467e-01 
+ 7.328000000000e-10 -6.496420384079e-01 
+ 7.428000000000e-10 -5.709822816025e-01 
+ 7.528000000000e-10 -4.396582995671e-01 
+ 7.628000000000e-10 -2.569529185106e-01 
+ 7.728000000000e-10 -3.860128053098e-02 
+ 7.828000000000e-10  1.891028165048e-01 
+ 7.928000000000e-10  3.939252197739e-01 
+ 8.028000000000e-10  5.441685861906e-01 
+ 8.128000000000e-10  6.359828023137e-01 
+ 8.228000000000e-10  6.723118712615e-01 
+ 8.328000000000e-10  6.496812709937e-01 
+ 8.428000000000e-10  5.709544657577e-01 
+ 8.528000000000e-10  4.397022527784e-01 
+ 8.628000000000e-10  2.569280980597e-01 
+ 8.728000000000e-10  3.864565597287e-02 
+ 8.828000000000e-10 -1.891278298806e-01 
+ 8.928000000000e-10 -3.938862165142e-01 
+ 9.028000000000e-10 -5.441949734698e-01 
+ 9.128000000000e-10 -6.359493781265e-01 
+ 9.228000000000e-10 -6.723420888760e-01 
+ 9.328000000000e-10 -6.496512561522e-01 
+ 9.428000000000e-10 -5.709874488604e-01 
+ 9.528000000000e-10 -4.396746422576e-01 
+ 9.628000000000e-10 -2.569616958772e-01 
+ 9.728000000000e-10 -3.861839939192e-02 
+ 9.828000000000e-10  1.890951489097e-01 
+ 9.928000000000e-10  3.939119089870e-01 
+ 1.000000000000e-09  5.081084039478e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/conditions.yaml
new file mode 100644
index 00000000..d49c902e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 4
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_04
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb.sch
new file mode 100644
index 00000000..54957d0f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb_5.data
new file mode 100644
index 00000000..97a3ab1f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_core_tb_5.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -3.026592886865e-01 
+ 1.728000000000e-10 -8.046058591213e-02 
+ 1.828000000000e-10  1.560684489845e-01 
+ 1.928000000000e-10  3.758215815324e-01 
+ 2.028000000000e-10  5.441825187720e-01 
+ 2.128000000000e-10  6.527787402061e-01 
+ 2.228000000000e-10  7.054162779080e-01 
+ 2.328000000000e-10  6.966940307878e-01 
+ 2.428000000000e-10  6.251719997267e-01 
+ 2.528000000000e-10  4.948986245243e-01 
+ 2.628000000000e-10  3.088338841037e-01 
+ 2.728000000000e-10  8.463582249819e-02 
+ 2.828000000000e-10 -1.534379373390e-01 
+ 2.928000000000e-10 -3.742382678981e-01 
+ 3.028000000000e-10 -5.437587344983e-01 
+ 3.128000000000e-10 -6.527795869025e-01 
+ 3.228000000000e-10 -7.060578401775e-01 
+ 3.328000000000e-10 -6.977288800308e-01 
+ 3.428000000000e-10 -6.267241220561e-01 
+ 3.528000000000e-10 -4.964034573067e-01 
+ 3.628000000000e-10 -3.104523257846e-01 
+ 3.728000000000e-10 -8.599843693100e-02 
+ 3.828000000000e-10  1.520614001089e-01 
+ 3.928000000000e-10  3.732327292359e-01 
+ 4.028000000000e-10  5.429530946109e-01 
+ 4.128000000000e-10  6.523997728799e-01 
+ 4.228000000000e-10  7.058202145507e-01 
+ 4.328000000000e-10  6.979022558405e-01 
+ 4.428000000000e-10  6.269588593419e-01 
+ 4.528000000000e-10  4.968624227466e-01 
+ 4.628000000000e-10  3.108132149603e-01 
+ 4.728000000000e-10  8.648038785746e-02 
+ 4.828000000000e-10 -1.517384677919e-01 
+ 4.928000000000e-10 -3.728474794484e-01 
+ 5.028000000000e-10 -5.427866011842e-01 
+ 5.128000000000e-10 -6.522022614009e-01 
+ 5.228000000000e-10 -7.058208822479e-01 
+ 5.328000000000e-10 -6.978651082200e-01 
+ 5.428000000000e-10 -6.270935668997e-01 
+ 5.528000000000e-10 -4.969096569281e-01 
+ 5.628000000000e-10 -3.109835748750e-01 
+ 5.728000000000e-10 -8.653572716924e-02 
+ 5.828000000000e-10  1.515778681972e-01 
+ 5.928000000000e-10  3.728127447205e-01 
+ 6.028000000000e-10  5.426739415091e-01 
+ 6.128000000000e-10  6.522162007318e-01 
+ 6.228000000000e-10  7.057544179932e-01 
+ 6.328000000000e-10  6.979224304337e-01 
+ 6.428000000000e-10  6.270641898671e-01 
+ 6.528000000000e-10  4.969874144680e-01 
+ 6.628000000000e-10  3.109648292365e-01 
+ 6.728000000000e-10  8.661535651254e-02 
+ 6.828000000000e-10 -1.515990397030e-01 
+ 6.928000000000e-10 -3.727433125293e-01 
+ 7.028000000000e-10 -5.427028559119e-01 
+ 7.128000000000e-10 -6.521615488134e-01 
+ 7.228000000000e-10 -7.057946841560e-01 
+ 7.328000000000e-10 -6.978790263426e-01 
+ 7.428000000000e-10 -6.271133848792e-01 
+ 7.528000000000e-10 -4.969513861012e-01 
+ 7.628000000000e-10 -3.110159233563e-01 
+ 7.728000000000e-10 -8.658006676819e-02 
+ 7.828000000000e-10  1.515487071721e-01 
+ 7.928000000000e-10  3.727772980737e-01 
+ 8.028000000000e-10  5.426589701450e-01 
+ 8.128000000000e-10  6.521979789832e-01 
+ 8.228000000000e-10  7.057547305503e-01 
+ 8.328000000000e-10  6.979187185021e-01 
+ 8.428000000000e-10  6.270767072939e-01 
+ 8.528000000000e-10  4.969913946096e-01 
+ 8.628000000000e-10  3.109805885283e-01 
+ 8.728000000000e-10  8.662004567697e-02 
+ 8.828000000000e-10 -1.515841004471e-01 
+ 8.928000000000e-10 -3.727405314049e-01 
+ 9.028000000000e-10 -5.426922302859e-01 
+ 9.128000000000e-10 -6.521632231968e-01 
+ 9.228000000000e-10 -7.057882763540e-01 
+ 9.328000000000e-10 -6.978845659833e-01 
+ 9.428000000000e-10 -6.271103709374e-01 
+ 9.528000000000e-10 -4.969587868574e-01 
+ 9.628000000000e-10 -3.110138943909e-01 
+ 9.728000000000e-10 -8.658760475647e-02 
+ 9.828000000000e-10  1.515508999036e-01 
+ 9.928000000000e-10  3.727707590510e-01 
+ 1.000000000000e-09  5.012730784879e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/conditions.yaml
new file mode 100644
index 00000000..856c6ace
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 5
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_05
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb.sch
new file mode 100644
index 00000000..344a9459
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb_6.data
new file mode 100644
index 00000000..68f452a6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_core_tb_6.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.658991355482e-01 
+ 1.728000000000e-10 -5.658971746101e-02 
+ 1.828000000000e-10  1.665652322471e-01 
+ 1.928000000000e-10  3.726189743475e-01 
+ 2.028000000000e-10  5.303705116758e-01 
+ 2.128000000000e-10  6.287796796090e-01 
+ 2.228000000000e-10  6.685380236864e-01 
+ 2.328000000000e-10  6.490234756137e-01 
+ 2.428000000000e-10  5.737092070140e-01 
+ 2.528000000000e-10  4.474825535463e-01 
+ 2.628000000000e-10  2.725242795062e-01 
+ 2.728000000000e-10  6.117177433706e-02 
+ 2.828000000000e-10 -1.637031734924e-01 
+ 2.928000000000e-10 -3.708935568748e-01 
+ 3.028000000000e-10 -5.297756369707e-01 
+ 3.128000000000e-10 -6.287017384995e-01 
+ 3.228000000000e-10 -6.693265533929e-01 
+ 3.328000000000e-10 -6.504570398323e-01 
+ 3.428000000000e-10 -5.758168078022e-01 
+ 3.528000000000e-10 -4.496242973413e-01 
+ 3.628000000000e-10 -2.747981275605e-01 
+ 3.728000000000e-10 -6.319393908832e-02 
+ 3.828000000000e-10  1.617439470913e-01 
+ 3.928000000000e-10  3.694169588634e-01 
+ 4.028000000000e-10  5.286499307585e-01 
+ 4.128000000000e-10  6.281722098808e-01 
+ 4.228000000000e-10  6.691184385543e-01 
+ 4.328000000000e-10  6.507901751638e-01 
+ 4.428000000000e-10  5.762974118946e-01 
+ 4.528000000000e-10  4.503608294115e-01 
+ 4.628000000000e-10  2.754522690623e-01 
+ 4.728000000000e-10  6.396306731360e-02 
+ 4.828000000000e-10 -1.611542650007e-01 
+ 4.928000000000e-10 -3.688169747432e-01 
+ 5.028000000000e-10 -5.283292872594e-01 
+ 5.128000000000e-10 -6.279003852563e-01 
+ 5.228000000000e-10 -6.691136918962e-01 
+ 5.328000000000e-10 -6.508124831570e-01 
+ 5.428000000000e-10 -5.765249280825e-01 
+ 5.528000000000e-10 -4.505225248069e-01 
+ 5.628000000000e-10 -2.757393848954e-01 
+ 5.728000000000e-10 -6.413835118523e-02 
+ 5.828000000000e-10  1.608879015274e-01 
+ 5.928000000000e-10  3.686909867212e-01 
+ 6.028000000000e-10  5.281558224884e-01 
+ 6.128000000000e-10  6.278785795680e-01 
+ 6.228000000000e-10  6.690442760911e-01 
+ 6.328000000000e-10  6.508870303825e-01 
+ 6.428000000000e-10  5.765321271449e-01 
+ 6.528000000000e-10  4.506407637839e-01 
+ 6.628000000000e-10  2.757670228304e-01 
+ 6.728000000000e-10  6.426080532693e-02 
+ 6.828000000000e-10 -1.608659404084e-01 
+ 6.928000000000e-10 -3.685888330346e-01 
+ 7.028000000000e-10 -5.281591419234e-01 
+ 7.128000000000e-10 -6.278127091451e-01 
+ 7.228000000000e-10 -6.690805910819e-01 
+ 7.328000000000e-10 -6.508520944992e-01 
+ 7.428000000000e-10 -5.765925476371e-01 
+ 7.528000000000e-10 -4.506215704207e-01 
+ 7.628000000000e-10 -2.758332595929e-01 
+ 7.728000000000e-10 -6.424327491402e-02 
+ 7.828000000000e-10  1.608024320318e-01 
+ 7.928000000000e-10  3.686091606456e-01 
+ 8.028000000000e-10  5.281080947303e-01 
+ 8.128000000000e-10  6.278426474070e-01 
+ 8.228000000000e-10  6.690409470235e-01 
+ 8.328000000000e-10  6.508923982303e-01 
+ 8.428000000000e-10  5.765614162070e-01 
+ 8.528000000000e-10  4.506656063053e-01 
+ 8.628000000000e-10  2.758047260180e-01 
+ 8.728000000000e-10  6.428762429921e-02 
+ 8.828000000000e-10 -1.608310872580e-01 
+ 8.928000000000e-10 -3.685690211775e-01 
+ 9.028000000000e-10 -5.281370864241e-01 
+ 9.128000000000e-10 -6.278075066251e-01 
+ 9.228000000000e-10 -6.690730291835e-01 
+ 9.328000000000e-10 -6.508603444096e-01 
+ 9.428000000000e-10 -5.765956636588e-01 
+ 9.528000000000e-10 -4.506359555730e-01 
+ 9.628000000000e-10 -2.758391852586e-01 
+ 9.728000000000e-10 -6.425829353037e-02 
+ 9.828000000000e-10  1.607973448132e-01 
+ 9.928000000000e-10  3.685968285070e-01 
+ 1.000000000000e-09  4.894958047088e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/conditions.yaml
new file mode 100644
index 00000000..6c2f28e1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 6
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_06
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb.sch
new file mode 100644
index 00000000..ba10f5a7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb_7.data
new file mode 100644
index 00000000..0dc3c32a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_core_tb_7.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.411371086013e-01 
+ 1.728000000000e-10 -3.745255924117e-02 
+ 1.828000000000e-10  1.789428987452e-01 
+ 1.928000000000e-10  3.769558934840e-01 
+ 2.028000000000e-10  5.255858783541e-01 
+ 2.128000000000e-10  6.150086513683e-01 
+ 2.228000000000e-10  6.463506095909e-01 
+ 2.328000000000e-10  6.202014565113e-01 
+ 2.428000000000e-10  5.417075102450e-01 
+ 2.528000000000e-10  4.161519970610e-01 
+ 2.628000000000e-10  2.448960905686e-01 
+ 2.728000000000e-10  3.892968213965e-02 
+ 2.828000000000e-10 -1.791505445505e-01 
+ 2.928000000000e-10 -3.778686664383e-01 
+ 3.028000000000e-10 -5.268093330033e-01 
+ 3.128000000000e-10 -6.159877416348e-01 
+ 3.228000000000e-10 -6.476195951568e-01 
+ 3.328000000000e-10 -6.216667221790e-01 
+ 3.428000000000e-10 -5.435382878554e-01 
+ 3.528000000000e-10 -4.178448923887e-01 
+ 3.628000000000e-10 -2.466531390426e-01 
+ 3.728000000000e-10 -4.041876256606e-02 
+ 3.828000000000e-10  1.777092594525e-01 
+ 3.928000000000e-10  3.768542192180e-01 
+ 4.028000000000e-10  5.260351926041e-01 
+ 4.128000000000e-10  6.156923491854e-01 
+ 4.228000000000e-10  6.475364165656e-01 
+ 4.328000000000e-10  6.220253224816e-01 
+ 4.428000000000e-10  5.439681165412e-01 
+ 4.528000000000e-10  4.184919515643e-01 
+ 4.628000000000e-10  2.472032785778e-01 
+ 4.728000000000e-10  4.108392377197e-02 
+ 4.828000000000e-10 -1.772209974541e-01 
+ 4.928000000000e-10 -3.763464849454e-01 
+ 5.028000000000e-10 -5.257893585276e-01 
+ 5.128000000000e-10 -6.154751208437e-01 
+ 5.228000000000e-10 -6.475677164184e-01 
+ 5.328000000000e-10 -6.220637777790e-01 
+ 5.428000000000e-10 -5.441970040997e-01 
+ 5.528000000000e-10 -4.186454653208e-01 
+ 5.628000000000e-10 -2.474812841152e-01 
+ 5.728000000000e-10 -4.124875776275e-02 
+ 5.828000000000e-10  1.769646369358e-01 
+ 5.928000000000e-10  3.762321495571e-01 
+ 6.028000000000e-10  5.256270530622e-01 
+ 6.128000000000e-10  6.154644314175e-01 
+ 6.228000000000e-10  6.475079392204e-01 
+ 6.328000000000e-10  6.221477255403e-01 
+ 6.428000000000e-10  5.442104878297e-01 
+ 6.528000000000e-10  4.187701859554e-01 
+ 6.628000000000e-10  2.475138621783e-01 
+ 6.728000000000e-10  4.137738638918e-02 
+ 6.828000000000e-10 -1.769383615791e-01 
+ 6.928000000000e-10 -3.761265802968e-01 
+ 7.028000000000e-10 -5.256298366366e-01 
+ 7.128000000000e-10 -6.153992750277e-01 
+ 7.228000000000e-10 -6.475476374408e-01 
+ 7.328000000000e-10 -6.221164421539e-01 
+ 7.428000000000e-10 -5.442762390873e-01 
+ 7.528000000000e-10 -4.187551150856e-01 
+ 7.628000000000e-10 -2.475858208222e-01 
+ 7.728000000000e-10 -4.136415856981e-02 
+ 7.828000000000e-10  1.768699557901e-01 
+ 7.928000000000e-10  3.761440347995e-01 
+ 8.028000000000e-10  5.255765528630e-01 
+ 8.128000000000e-10  6.154291154928e-01 
+ 8.228000000000e-10  6.475082015932e-01 
+ 8.328000000000e-10  6.221591874055e-01 
+ 8.428000000000e-10  5.442468649409e-01 
+ 8.528000000000e-10  4.188025713318e-01 
+ 8.628000000000e-10  2.475593730203e-01 
+ 8.728000000000e-10  4.141194467582e-02 
+ 8.828000000000e-10 -1.768965906206e-01 
+ 8.928000000000e-10 -3.761014263264e-01 
+ 9.028000000000e-10 -5.256047249426e-01 
+ 9.128000000000e-10 -6.153930400648e-01 
+ 9.228000000000e-10 -6.475410523019e-01 
+ 9.328000000000e-10 -6.221273229309e-01 
+ 9.428000000000e-10 -5.442828742824e-01 
+ 9.528000000000e-10 -4.187734552047e-01 
+ 9.628000000000e-10 -2.475958588134e-01 
+ 9.728000000000e-10 -4.138326223976e-02 
+ 9.828000000000e-10  1.768611473522e-01 
+ 9.928000000000e-10  3.761288017358e-01 
+ 1.000000000000e-09  4.898465656484e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/conditions.yaml
new file mode 100644
index 00000000..d33b7488
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 7
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_07
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb.sch
new file mode 100644
index 00000000..7c2e7249
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb_8.data
new file mode 100644
index 00000000..f9704d61
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_core_tb_8.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -2.915574653990e-01 
+ 1.728000000000e-10 -8.207206468644e-02 
+ 1.828000000000e-10  1.443140454917e-01 
+ 1.928000000000e-10  3.578501059917e-01 
+ 2.028000000000e-10  5.264102614641e-01 
+ 2.128000000000e-10  6.356033847750e-01 
+ 2.228000000000e-10  6.852124516173e-01 
+ 2.328000000000e-10  6.731697751231e-01 
+ 2.428000000000e-10  6.014680860110e-01 
+ 2.528000000000e-10  4.762934940598e-01 
+ 2.628000000000e-10  3.019743151843e-01 
+ 2.728000000000e-10  9.052768843264e-02 
+ 2.828000000000e-10 -1.376882496508e-01 
+ 2.928000000000e-10 -3.528073773591e-01 
+ 3.028000000000e-10 -5.234244166185e-01 
+ 3.128000000000e-10 -6.340851318675e-01 
+ 3.228000000000e-10 -6.854084589569e-01 
+ 3.328000000000e-10 -6.747695956588e-01 
+ 3.428000000000e-10 -6.042844418494e-01 
+ 3.528000000000e-10 -4.793995649692e-01 
+ 3.628000000000e-10 -3.052822644166e-01 
+ 3.728000000000e-10 -9.358407685981e-02 
+ 3.828000000000e-10  1.347194202511e-01 
+ 3.928000000000e-10  3.504174847188e-01 
+ 4.028000000000e-10  5.215924623562e-01 
+ 4.128000000000e-10  6.330900225454e-01 
+ 4.228000000000e-10  6.849701135730e-01 
+ 4.328000000000e-10  6.751037342439e-01 
+ 4.428000000000e-10  6.049384750133e-01 
+ 4.528000000000e-10  4.803914109079e-01 
+ 4.628000000000e-10  3.062148923158e-01 
+ 4.728000000000e-10  9.463220881739e-02 
+ 4.828000000000e-10 -1.338572933423e-01 
+ 4.928000000000e-10 -3.495689260045e-01 
+ 5.028000000000e-10 -5.210792449240e-01 
+ 5.128000000000e-10 -6.326887195405e-01 
+ 5.228000000000e-10 -6.848983576670e-01 
+ 5.328000000000e-10 -6.751198274713e-01 
+ 5.428000000000e-10 -6.052060952211e-01 
+ 5.528000000000e-10 -4.806148207689e-01 
+ 5.628000000000e-10 -3.065686575138e-01 
+ 5.728000000000e-10 -9.487468231529e-02 
+ 5.828000000000e-10  1.335246601606e-01 
+ 5.928000000000e-10  3.493821792388e-01 
+ 6.028000000000e-10  5.208575371198e-01 
+ 6.128000000000e-10  6.326338805716e-01 
+ 6.228000000000e-10  6.848108600046e-01 
+ 6.328000000000e-10  6.751907109187e-01 
+ 6.428000000000e-10  6.052214841565e-01 
+ 6.528000000000e-10  4.807458450129e-01 
+ 6.628000000000e-10  3.066111422989e-01 
+ 6.728000000000e-10  9.501122064621e-02 
+ 6.828000000000e-10 -1.334882175614e-01 
+ 6.928000000000e-10 -3.492660352924e-01 
+ 7.028000000000e-10 -5.208495294585e-01 
+ 7.128000000000e-10 -6.325598499367e-01 
+ 7.228000000000e-10 -6.848421004986e-01 
+ 7.328000000000e-10 -6.751543080912e-01 
+ 7.428000000000e-10 -6.052828258645e-01 
+ 7.528000000000e-10 -4.807293659120e-01 
+ 7.628000000000e-10 -3.066794924108e-01 
+ 7.728000000000e-10 -9.499664108150e-02 
+ 7.828000000000e-10  1.334220275121e-01 
+ 7.928000000000e-10  3.492835018463e-01 
+ 8.028000000000e-10  5.207961769649e-01 
+ 8.128000000000e-10  6.325876998525e-01 
+ 8.228000000000e-10  6.848014468222e-01 
+ 8.328000000000e-10  6.751935994962e-01 
+ 8.428000000000e-10  6.052518981308e-01 
+ 8.528000000000e-10  4.807729857688e-01 
+ 8.628000000000e-10  3.066516205185e-01 
+ 8.728000000000e-10  9.504068447266e-02 
+ 8.828000000000e-10 -1.334502935734e-01 
+ 8.928000000000e-10 -3.492430994753e-01 
+ 9.028000000000e-10 -5.208246106410e-01 
+ 9.128000000000e-10 -6.325523513325e-01 
+ 9.228000000000e-10 -6.848328984481e-01 
+ 9.328000000000e-10 -6.751615848536e-01 
+ 9.428000000000e-10 -6.052856721640e-01 
+ 9.528000000000e-10 -4.807436971446e-01 
+ 9.628000000000e-10 -3.066854569150e-01 
+ 9.728000000000e-10 -9.501170247958e-02 
+ 9.828000000000e-10  1.334168358063e-01 
+ 9.928000000000e-10  3.492707284922e-01 
+ 1.000000000000e-09  4.787459694615e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/conditions.yaml
new file mode 100644
index 00000000..ef25974c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 8
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_08
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb.sch
new file mode 100644
index 00000000..640885d9
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb_9.data
new file mode 100644
index 00000000..bce5cca7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_core_tb_9.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.397443385003e-01 
+ 1.728000000000e-10 -2.045536352810e-01 
+ 1.828000000000e-10  1.313863393294e-01 
+ 1.928000000000e-10  3.838209275603e-01 
+ 2.028000000000e-10  5.347375940933e-01 
+ 2.128000000000e-10  6.276591932156e-01 
+ 2.228000000000e-10  7.115621702194e-01 
+ 2.328000000000e-10  7.798611559065e-01 
+ 2.428000000000e-10  8.066497785728e-01 
+ 2.528000000000e-10  7.447444131165e-01 
+ 2.628000000000e-10  5.331798214247e-01 
+ 2.728000000000e-10  1.991243487460e-01 
+ 2.828000000000e-10 -1.352153251063e-01 
+ 2.928000000000e-10 -3.864762984079e-01 
+ 3.028000000000e-10 -5.369168929595e-01 
+ 3.128000000000e-10 -6.290603792866e-01 
+ 3.228000000000e-10 -7.126196515736e-01 
+ 3.328000000000e-10 -7.804415576126e-01 
+ 3.428000000000e-10 -8.071911048716e-01 
+ 3.528000000000e-10 -7.450481751688e-01 
+ 3.628000000000e-10 -5.336055963763e-01 
+ 3.728000000000e-10 -1.993198332358e-01 
+ 3.828000000000e-10  1.349559401886e-01 
+ 3.928000000000e-10  3.864112742700e-01 
+ 4.028000000000e-10  5.367351878370e-01 
+ 4.128000000000e-10  6.290489992071e-01 
+ 4.228000000000e-10  7.124864782962e-01 
+ 4.328000000000e-10  7.804750739895e-01 
+ 4.428000000000e-10  8.070933947437e-01 
+ 4.528000000000e-10  7.451033689318e-01 
+ 4.628000000000e-10  5.335168975820e-01 
+ 4.728000000000e-10  1.993807368925e-01 
+ 4.828000000000e-10 -1.350304895400e-01 
+ 4.928000000000e-10 -3.863532554681e-01 
+ 5.028000000000e-10 -5.368040585560e-01 
+ 5.128000000000e-10 -6.289909078772e-01 
+ 5.228000000000e-10 -7.125533448218e-01 
+ 5.328000000000e-10 -7.804160897110e-01 
+ 5.428000000000e-10 -8.071554863663e-01 
+ 5.528000000000e-10 -7.450422465689e-01 
+ 5.628000000000e-10 -5.335838460974e-01 
+ 5.728000000000e-10 -1.993167730115e-01 
+ 5.828000000000e-10  1.349726890254e-01 
+ 5.928000000000e-10  3.864109858256e-01 
+ 6.028000000000e-10  5.367479691018e-01 
+ 6.128000000000e-10  6.290476980129e-01 
+ 6.228000000000e-10  7.124950121919e-01 
+ 6.328000000000e-10  7.804717191606e-01 
+ 6.428000000000e-10  8.070994779138e-01 
+ 6.528000000000e-10  7.450975613250e-01 
+ 6.628000000000e-10  5.335259065522e-01 
+ 6.728000000000e-10  1.993734548210e-01 
+ 6.828000000000e-10 -1.350242777574e-01 
+ 6.928000000000e-10 -3.863605033303e-01 
+ 7.028000000000e-10 -5.367975294074e-01 
+ 7.128000000000e-10 -6.289982763959e-01 
+ 7.228000000000e-10 -7.125455111440e-01 
+ 7.328000000000e-10 -7.804238043085e-01 
+ 7.428000000000e-10 -8.071473680780e-01 
+ 7.528000000000e-10 -7.450494772754e-01 
+ 7.628000000000e-10 -5.335773499054e-01 
+ 7.728000000000e-10 -1.993230348361e-01 
+ 7.828000000000e-10  1.349793746975e-01 
+ 7.928000000000e-10  3.864055722387e-01 
+ 8.028000000000e-10  5.367539279153e-01 
+ 8.128000000000e-10  6.290427569853e-01 
+ 8.228000000000e-10  7.125002063044e-01 
+ 8.328000000000e-10  7.804668926767e-01 
+ 8.428000000000e-10  8.071042297758e-01 
+ 8.528000000000e-10  7.450922570276e-01 
+ 8.628000000000e-10  5.335323457616e-01 
+ 8.728000000000e-10  1.993673584870e-01 
+ 8.828000000000e-10 -1.350193573750e-01 
+ 8.928000000000e-10 -3.863660901230e-01 
+ 9.028000000000e-10 -5.367925035482e-01 
+ 9.128000000000e-10 -6.290039875175e-01 
+ 9.228000000000e-10 -7.125398122704e-01 
+ 9.328000000000e-10 -7.804294363608e-01 
+ 9.428000000000e-10 -8.071416857778e-01 
+ 9.528000000000e-10 -7.450548065452e-01 
+ 9.628000000000e-10 -5.335722743766e-01 
+ 9.728000000000e-10 -1.993280329539e-01 
+ 9.828000000000e-10  1.349843549639e-01 
+ 9.928000000000e-10  3.864011317450e-01 
+ 1.000000000000e-09  5.028020863733e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/conditions.yaml
new file mode 100644
index 00000000..e334a68d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 9
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_09
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb.sch
new file mode 100644
index 00000000..d3fa88ed
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb_10.data
new file mode 100644
index 00000000..b27b6db0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_core_tb_10.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.293189432094e-01 
+ 1.728000000000e-10 -2.034299929592e-01 
+ 1.828000000000e-10  1.254532736892e-01 
+ 1.928000000000e-10  3.744603520131e-01 
+ 2.028000000000e-10  5.220595086358e-01 
+ 2.128000000000e-10  6.139346231694e-01 
+ 2.228000000000e-10  6.977077768020e-01 
+ 2.328000000000e-10  7.638951530454e-01 
+ 2.428000000000e-10  7.881008470503e-01 
+ 2.528000000000e-10  7.271434956617e-01 
+ 2.628000000000e-10  5.227259392947e-01 
+ 2.728000000000e-10  1.977807095317e-01 
+ 2.828000000000e-10 -1.296557480667e-01 
+ 2.928000000000e-10 -3.774966254092e-01 
+ 3.028000000000e-10 -5.245506032311e-01 
+ 3.128000000000e-10 -6.155925798862e-01 
+ 3.228000000000e-10 -6.989490114600e-01 
+ 3.328000000000e-10 -7.646204924296e-01 
+ 3.428000000000e-10 -7.887093478172e-01 
+ 3.528000000000e-10 -7.274783648153e-01 
+ 3.628000000000e-10 -5.231513423786e-01 
+ 3.728000000000e-10 -1.979863018154e-01 
+ 3.828000000000e-10  1.294013660930e-01 
+ 3.928000000000e-10  3.774276121382e-01 
+ 4.028000000000e-10  5.243833105689e-01 
+ 4.128000000000e-10  6.155813660155e-01 
+ 4.228000000000e-10  6.988272077165e-01 
+ 4.328000000000e-10  7.646509984988e-01 
+ 4.428000000000e-10  7.886185007607e-01 
+ 4.528000000000e-10  7.275266613790e-01 
+ 4.628000000000e-10  5.230676681296e-01 
+ 4.728000000000e-10  1.980405747385e-01 
+ 4.828000000000e-10 -1.294713662253e-01 
+ 4.928000000000e-10 -3.773761496757e-01 
+ 5.028000000000e-10 -5.244469821379e-01 
+ 5.128000000000e-10 -6.155294307936e-01 
+ 5.228000000000e-10 -6.988887956355e-01 
+ 5.328000000000e-10 -7.645972449904e-01 
+ 5.428000000000e-10 -7.886754254295e-01 
+ 5.528000000000e-10 -7.274706677122e-01 
+ 5.628000000000e-10 -5.231295350854e-01 
+ 5.728000000000e-10 -1.979806299381e-01 
+ 5.828000000000e-10  1.294187696545e-01 
+ 5.928000000000e-10  3.774292707563e-01 
+ 6.028000000000e-10  5.243961595933e-01 
+ 6.128000000000e-10  6.155814701559e-01 
+ 6.228000000000e-10  6.988355515168e-01 
+ 6.328000000000e-10  7.646484599731e-01 
+ 6.428000000000e-10  7.886243100181e-01 
+ 6.528000000000e-10  7.275215569265e-01 
+ 6.628000000000e-10  5.230764840752e-01 
+ 6.728000000000e-10  1.980332799823e-01 
+ 6.828000000000e-10 -1.294660192513e-01 
+ 6.928000000000e-10 -3.773827405650e-01 
+ 7.028000000000e-10 -5.244413520748e-01 
+ 7.128000000000e-10 -6.155361997798e-01 
+ 7.228000000000e-10 -6.988817029216e-01 
+ 7.328000000000e-10 -7.646043204444e-01 
+ 7.428000000000e-10 -7.886680576572e-01 
+ 7.528000000000e-10 -7.274772120684e-01 
+ 7.628000000000e-10 -5.231238849653e-01 
+ 7.728000000000e-10 -1.979860775160e-01 
+ 7.828000000000e-10  1.294249237809e-01 
+ 7.928000000000e-10  3.774244918330e-01 
+ 8.028000000000e-10  5.244015690321e-01 
+ 8.128000000000e-10  6.155771739166e-01 
+ 8.228000000000e-10  6.988402156207e-01 
+ 8.328000000000e-10  7.646441380646e-01 
+ 8.428000000000e-10  7.886285892332e-01 
+ 8.528000000000e-10  7.275167248781e-01 
+ 8.628000000000e-10  5.230825202638e-01 
+ 8.728000000000e-10  1.980273627479e-01 
+ 8.828000000000e-10 -1.294617038455e-01 
+ 8.928000000000e-10 -3.773878907235e-01 
+ 9.028000000000e-10 -5.244369215984e-01 
+ 9.128000000000e-10 -6.155414802599e-01 
+ 9.228000000000e-10 -6.988765421320e-01 
+ 9.328000000000e-10 -7.646094975483e-01 
+ 9.428000000000e-10 -7.886629049186e-01 
+ 9.528000000000e-10 -7.274820443091e-01 
+ 9.628000000000e-10 -5.231193961018e-01 
+ 9.728000000000e-10 -1.979905037884e-01 
+ 9.828000000000e-10  1.294294922144e-01 
+ 9.928000000000e-10  3.774205018001e-01 
+ 1.000000000000e-09  4.912603506308e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/conditions.yaml
new file mode 100644
index 00000000..9563737f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 10
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_10
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb.sch
new file mode 100644
index 00000000..ea990b32
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb_11.data
new file mode 100644
index 00000000..799f8459
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_core_tb_11.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.473675478550e-01 
+ 1.728000000000e-10 -2.087893101739e-01 
+ 1.828000000000e-10  1.310494751476e-01 
+ 1.928000000000e-10  3.871555645678e-01 
+ 2.028000000000e-10  5.437689230363e-01 
+ 2.128000000000e-10  6.391330299748e-01 
+ 2.228000000000e-10  7.213082317981e-01 
+ 2.328000000000e-10  7.903248370025e-01 
+ 2.428000000000e-10  8.187618792919e-01 
+ 2.528000000000e-10  7.555729663838e-01 
+ 2.628000000000e-10  5.409345054541e-01 
+ 2.728000000000e-10  2.036912835862e-01 
+ 2.828000000000e-10 -1.345140506878e-01 
+ 2.928000000000e-10 -3.895370892644e-01 
+ 3.028000000000e-10 -5.457400052530e-01 
+ 3.128000000000e-10 -6.403498057265e-01 
+ 3.228000000000e-10 -7.222286336937e-01 
+ 3.328000000000e-10 -7.907911780827e-01 
+ 3.428000000000e-10 -8.192361080664e-01 
+ 3.528000000000e-10 -7.558198978931e-01 
+ 3.628000000000e-10 -5.413206307136e-01 
+ 3.728000000000e-10 -2.038438399825e-01 
+ 3.828000000000e-10  1.342763346632e-01 
+ 3.928000000000e-10  3.894921044587e-01 
+ 4.028000000000e-10  5.455616788274e-01 
+ 4.128000000000e-10  6.403489734683e-01 
+ 4.228000000000e-10  7.220944352324e-01 
+ 4.328000000000e-10  7.908322596821e-01 
+ 4.428000000000e-10  8.191363162855e-01 
+ 4.528000000000e-10  7.558824803046e-01 
+ 4.628000000000e-10  5.412307821184e-01 
+ 4.728000000000e-10  2.039121351986e-01 
+ 4.828000000000e-10 -1.343528713892e-01 
+ 4.928000000000e-10 -3.894290190191e-01 
+ 5.028000000000e-10 -5.456335562174e-01 
+ 5.128000000000e-10 -6.402860869065e-01 
+ 5.228000000000e-10 -7.221652152444e-01 
+ 5.328000000000e-10 -7.907686614943e-01 
+ 5.428000000000e-10 -8.192023796026e-01 
+ 5.528000000000e-10 -7.558173441778e-01 
+ 5.628000000000e-10 -5.413004970284e-01 
+ 5.728000000000e-10 -2.038447386050e-01 
+ 5.828000000000e-10  1.342913524064e-01 
+ 5.928000000000e-10  3.894897157728e-01 
+ 6.028000000000e-10  5.455737058766e-01 
+ 6.128000000000e-10  6.403462778603e-01 
+ 6.228000000000e-10  7.221032530671e-01 
+ 6.328000000000e-10  7.908278354740e-01 
+ 6.428000000000e-10  8.191430293573e-01 
+ 6.528000000000e-10  7.558759446864e-01 
+ 6.628000000000e-10  5.412396296665e-01 
+ 6.728000000000e-10  2.039046702204e-01 
+ 6.828000000000e-10 -1.343459163903e-01 
+ 6.928000000000e-10 -3.894366779769e-01 
+ 7.028000000000e-10 -5.456262483653e-01 
+ 7.128000000000e-10 -6.402940065215e-01 
+ 7.228000000000e-10 -7.221570137640e-01 
+ 7.328000000000e-10 -7.907769448806e-01 
+ 7.428000000000e-10 -8.191938542033e-01 
+ 7.528000000000e-10 -7.558251320231e-01 
+ 7.628000000000e-10 -5.412933191298e-01 
+ 7.728000000000e-10 -2.038518419443e-01 
+ 7.828000000000e-10  1.342982918430e-01 
+ 7.928000000000e-10  3.894837914532e-01 
+ 8.028000000000e-10  5.455799247329e-01 
+ 8.128000000000e-10  6.403408689327e-01 
+ 8.228000000000e-10  7.221089932485e-01 
+ 8.328000000000e-10  7.908225333386e-01 
+ 8.428000000000e-10  8.191482615363e-01 
+ 8.528000000000e-10  7.558702665648e-01 
+ 8.628000000000e-10  5.412462517638e-01 
+ 8.728000000000e-10  2.038984202104e-01 
+ 8.828000000000e-10 -1.343404705774e-01 
+ 8.928000000000e-10 -3.894425333092e-01 
+ 9.028000000000e-10 -5.456206778041e-01 
+ 9.128000000000e-10 -6.403000729433e-01 
+ 9.228000000000e-10 -7.221509667404e-01 
+ 9.328000000000e-10 -7.907829740936e-01 
+ 9.428000000000e-10 -8.191877974471e-01 
+ 9.528000000000e-10 -7.558308764830e-01 
+ 9.628000000000e-10 -5.412878201925e-01 
+ 9.728000000000e-10 -2.038573569097e-01 
+ 9.828000000000e-10  1.343035264203e-01 
+ 9.928000000000e-10  3.894790170617e-01 
+ 1.000000000000e-09  5.100069898815e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/conditions.yaml
new file mode 100644
index 00000000..0d4e1f0c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 11
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_11
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb.sch
new file mode 100644
index 00000000..dac359f6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb_12.data
new file mode 100644
index 00000000..db4e4cce
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_core_tb_12.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.049557277618e-01 
+ 1.728000000000e-10 -1.958466480437e-01 
+ 1.828000000000e-10  1.196319367700e-01 
+ 1.928000000000e-10  3.700244189406e-01 
+ 2.028000000000e-10  5.308067637731e-01 
+ 2.128000000000e-10  6.311299202315e-01 
+ 2.228000000000e-10  7.086540860403e-01 
+ 2.328000000000e-10  7.625529356493e-01 
+ 2.428000000000e-10  7.708473475114e-01 
+ 2.528000000000e-10  6.980446990655e-01 
+ 2.628000000000e-10  4.981026307256e-01 
+ 2.728000000000e-10  1.904449044265e-01 
+ 2.828000000000e-10 -1.236510258628e-01 
+ 2.928000000000e-10 -3.730975798774e-01 
+ 3.028000000000e-10 -5.333436235403e-01 
+ 3.128000000000e-10 -6.328422885796e-01 
+ 3.228000000000e-10 -7.099622515515e-01 
+ 3.328000000000e-10 -7.633093670089e-01 
+ 3.428000000000e-10 -7.714462858000e-01 
+ 3.528000000000e-10 -6.983543456334e-01 
+ 3.628000000000e-10 -4.984830350414e-01 
+ 3.728000000000e-10 -1.906133898346e-01 
+ 3.828000000000e-10  1.234140438752e-01 
+ 3.928000000000e-10  3.730258572177e-01 
+ 4.028000000000e-10  5.331667972487e-01 
+ 4.128000000000e-10  6.328214645319e-01 
+ 4.228000000000e-10  7.098336990067e-01 
+ 4.328000000000e-10  7.633335528675e-01 
+ 4.428000000000e-10  7.713603033543e-01 
+ 4.528000000000e-10  6.984040906368e-01 
+ 4.628000000000e-10  4.984087981115e-01 
+ 4.728000000000e-10  1.906698925098e-01 
+ 4.828000000000e-10 -1.234792426423e-01 
+ 4.928000000000e-10 -3.729733539485e-01 
+ 5.028000000000e-10 -5.332277682129e-01 
+ 5.128000000000e-10 -6.327690017914e-01 
+ 5.228000000000e-10 -7.098933602520e-01 
+ 5.328000000000e-10 -7.632805035294e-01 
+ 5.428000000000e-10 -7.714147767047e-01 
+ 5.528000000000e-10 -6.983493927960e-01 
+ 5.628000000000e-10 -4.984657326360e-01 
+ 5.728000000000e-10 -1.906133403657e-01 
+ 5.828000000000e-10  1.234275058651e-01 
+ 5.928000000000e-10  3.730246636548e-01 
+ 6.028000000000e-10  5.331775888699e-01 
+ 6.128000000000e-10  6.328197652536e-01 
+ 6.228000000000e-10  7.098419058182e-01 
+ 6.328000000000e-10  7.633301342197e-01 
+ 6.428000000000e-10  7.713661487972e-01 
+ 6.528000000000e-10  6.983986251010e-01 
+ 6.628000000000e-10  4.984160910452e-01 
+ 6.728000000000e-10  1.906635868460e-01 
+ 6.828000000000e-10 -1.234734747225e-01 
+ 6.928000000000e-10 -3.729797013887e-01 
+ 7.028000000000e-10 -5.332215969565e-01 
+ 7.128000000000e-10 -6.327757131741e-01 
+ 7.228000000000e-10 -7.098865351622e-01 
+ 7.328000000000e-10 -7.632871392149e-01 
+ 7.428000000000e-10 -7.714081948986e-01 
+ 7.528000000000e-10 -6.983555969606e-01 
+ 7.628000000000e-10 -4.984601688237e-01 
+ 7.728000000000e-10 -1.906192454806e-01 
+ 7.828000000000e-10  1.234332321656e-01 
+ 7.928000000000e-10  3.730195983111e-01 
+ 8.028000000000e-10  5.331826746949e-01 
+ 8.128000000000e-10  6.328151783475e-01 
+ 8.228000000000e-10  7.098466992587e-01 
+ 8.328000000000e-10  7.633256332241e-01 
+ 8.428000000000e-10  7.713705417094e-01 
+ 8.528000000000e-10  6.983937777920e-01 
+ 8.628000000000e-10  4.984215072239e-01 
+ 8.728000000000e-10  1.906583322627e-01 
+ 8.828000000000e-10 -1.234689419945e-01 
+ 8.928000000000e-10 -3.729845695752e-01 
+ 9.028000000000e-10 -5.332169477613e-01 
+ 9.128000000000e-10 -6.327807857544e-01 
+ 9.228000000000e-10 -7.098815617208e-01 
+ 9.328000000000e-10 -7.632920474235e-01 
+ 9.428000000000e-10 -7.714033753149e-01 
+ 9.528000000000e-10 -6.983602366678e-01 
+ 9.628000000000e-10 -4.984557776243e-01 
+ 9.728000000000e-10 -1.906237729891e-01 
+ 9.828000000000e-10  1.234375916302e-01 
+ 9.928000000000e-10  3.730155682884e-01 
+ 1.000000000000e-09  4.959193237551e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/conditions.yaml
new file mode 100644
index 00000000..b0f21e40
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 12
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_12
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb.sch
new file mode 100644
index 00000000..2dec963c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb_13.data
new file mode 100644
index 00000000..539ab7b7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_core_tb_13.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.935497259980e-01 
+ 1.728000000000e-10 -1.928633983658e-01 
+ 1.828000000000e-10  1.160949240371e-01 
+ 1.928000000000e-10  3.619360857197e-01 
+ 2.028000000000e-10  5.185143131218e-01 
+ 2.128000000000e-10  6.170086772416e-01 
+ 2.228000000000e-10  6.939063598865e-01 
+ 2.328000000000e-10  7.457993341265e-01 
+ 2.428000000000e-10  7.520509596304e-01 
+ 2.528000000000e-10  6.804739824857e-01 
+ 2.628000000000e-10  4.870426149481e-01 
+ 2.728000000000e-10  1.875308246798e-01 
+ 2.828000000000e-10 -1.202389208092e-01 
+ 2.928000000000e-10 -3.651754434827e-01 
+ 3.028000000000e-10 -5.211918880427e-01 
+ 3.128000000000e-10 -6.188469707889e-01 
+ 3.228000000000e-10 -6.953072467312e-01 
+ 3.328000000000e-10 -7.466129151979e-01 
+ 3.428000000000e-10 -7.526565311823e-01 
+ 3.528000000000e-10 -6.807675409917e-01 
+ 3.628000000000e-10 -4.873945801883e-01 
+ 3.728000000000e-10 -1.876809763872e-01 
+ 3.828000000000e-10  1.200199744899e-01 
+ 3.928000000000e-10  3.651151173578e-01 
+ 4.028000000000e-10  5.210322421793e-01 
+ 4.128000000000e-10  6.188330192958e-01 
+ 4.228000000000e-10  6.951893716680e-01 
+ 4.328000000000e-10  7.466394998986e-01 
+ 4.428000000000e-10  7.525773069027e-01 
+ 4.528000000000e-10  6.808165070916e-01 
+ 4.628000000000e-10  4.873248087716e-01 
+ 4.728000000000e-10  1.877358679741e-01 
+ 4.828000000000e-10 -1.200819840902e-01 
+ 4.928000000000e-10 -3.650646413699e-01 
+ 5.028000000000e-10 -5.210903047408e-01 
+ 5.128000000000e-10 -6.187830156405e-01 
+ 5.228000000000e-10 -6.952462050643e-01 
+ 5.328000000000e-10 -7.465883056073e-01 
+ 5.428000000000e-10 -7.526293067125e-01 
+ 5.528000000000e-10 -6.807638103361e-01 
+ 5.628000000000e-10 -4.873795115624e-01 
+ 5.728000000000e-10 -1.876807689254e-01 
+ 5.828000000000e-10  1.200326256254e-01 
+ 5.928000000000e-10  3.651139754788e-01 
+ 6.028000000000e-10  5.210426454606e-01 
+ 6.128000000000e-10  6.188315227579e-01 
+ 6.228000000000e-10  6.951972695911e-01 
+ 6.328000000000e-10  7.466359762402e-01 
+ 6.428000000000e-10  7.525829976005e-01 
+ 6.528000000000e-10  6.808110143898e-01 
+ 6.628000000000e-10  4.873318873720e-01 
+ 6.728000000000e-10  1.877292356433e-01 
+ 6.828000000000e-10 -1.200767202072e-01 
+ 6.928000000000e-10 -3.650706499628e-01 
+ 7.028000000000e-10 -5.210847183857e-01 
+ 7.128000000000e-10 -6.187893543189e-01 
+ 7.228000000000e-10 -6.952399017798e-01 
+ 7.328000000000e-10 -7.465944604664e-01 
+ 7.428000000000e-10 -7.526232942576e-01 
+ 7.528000000000e-10 -6.807695137827e-01 
+ 7.628000000000e-10 -4.873744121182e-01 
+ 7.728000000000e-10 -1.876860880622e-01 
+ 7.828000000000e-10  1.200380835632e-01 
+ 7.928000000000e-10  3.651091778387e-01 
+ 8.028000000000e-10  5.210475167171e-01 
+ 8.128000000000e-10  6.188272213187e-01 
+ 8.228000000000e-10  6.952018279574e-01 
+ 8.328000000000e-10  7.466316140292e-01 
+ 8.428000000000e-10  7.525872528114e-01 
+ 8.528000000000e-10  6.808063071094e-01 
+ 8.628000000000e-10  4.873371355126e-01 
+ 8.728000000000e-10  1.877239857571e-01 
+ 8.828000000000e-10 -1.200724809112e-01 
+ 8.928000000000e-10 -3.650752679165e-01 
+ 9.028000000000e-10 -5.210804068397e-01 
+ 9.128000000000e-10 -6.187941569931e-01 
+ 9.228000000000e-10 -6.952352466105e-01 
+ 9.328000000000e-10 -7.465990720366e-01 
+ 9.428000000000e-10 -7.526188226163e-01 
+ 9.528000000000e-10 -6.807738360998e-01 
+ 9.628000000000e-10 -4.873703126609e-01 
+ 9.728000000000e-10 -1.876902725775e-01 
+ 9.828000000000e-10  1.200422409457e-01 
+ 9.928000000000e-10  3.651053453859e-01 
+ 1.000000000000e-09  4.847952698035e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/conditions.yaml
new file mode 100644
index 00000000..4bf35c87
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 13
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_13
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb.sch
new file mode 100644
index 00000000..c5a0f74e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb_14.data
new file mode 100644
index 00000000..3796cea3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_core_tb_14.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.133282675634e-01 
+ 1.728000000000e-10 -2.031582081928e-01 
+ 1.828000000000e-10  1.144804838339e-01 
+ 1.928000000000e-10  3.698591588516e-01 
+ 2.028000000000e-10  5.380258146680e-01 
+ 2.128000000000e-10  6.422542980920e-01 
+ 2.228000000000e-10  7.191574927620e-01 
+ 2.328000000000e-10  7.734390216007e-01 
+ 2.428000000000e-10  7.823512104827e-01 
+ 2.528000000000e-10  7.081342613122e-01 
+ 2.628000000000e-10  5.065809773945e-01 
+ 2.728000000000e-10  1.980707374060e-01 
+ 2.828000000000e-10 -1.181831896095e-01 
+ 2.928000000000e-10 -3.727163876319e-01 
+ 3.028000000000e-10 -5.404428949084e-01 
+ 3.128000000000e-10 -6.438704305572e-01 
+ 3.228000000000e-10 -7.204145434420e-01 
+ 3.328000000000e-10 -7.741471374370e-01 
+ 3.428000000000e-10 -7.829309638154e-01 
+ 3.528000000000e-10 -7.084110972821e-01 
+ 3.628000000000e-10 -5.069426471107e-01 
+ 3.728000000000e-10 -1.982066720174e-01 
+ 3.828000000000e-10  1.179564926067e-01 
+ 3.928000000000e-10  3.726621714283e-01 
+ 4.028000000000e-10  5.402630628674e-01 
+ 4.128000000000e-10  6.438601752956e-01 
+ 4.228000000000e-10  7.202791375194e-01 
+ 4.328000000000e-10  7.741793827377e-01 
+ 4.428000000000e-10  7.828380754967e-01 
+ 4.528000000000e-10  7.084693803333e-01 
+ 4.628000000000e-10  5.068627667504e-01 
+ 4.728000000000e-10  1.982719515445e-01 
+ 4.828000000000e-10 -1.180275895897e-01 
+ 4.928000000000e-10 -3.726028735362e-01 
+ 5.028000000000e-10 -5.403301024789e-01 
+ 5.128000000000e-10 -6.438008084190e-01 
+ 5.228000000000e-10 -7.203455420725e-01 
+ 5.328000000000e-10 -7.741198297783e-01 
+ 5.428000000000e-10 -7.828987326701e-01 
+ 5.528000000000e-10 -7.084084859242e-01 
+ 5.628000000000e-10 -5.069251044876e-01 
+ 5.728000000000e-10 -1.982094732584e-01 
+ 5.828000000000e-10  1.179697981212e-01 
+ 5.928000000000e-10  3.726595322461e-01 
+ 6.028000000000e-10  5.402739437431e-01 
+ 6.128000000000e-10  6.438573026479e-01 
+ 6.228000000000e-10  7.202880216174e-01 
+ 6.328000000000e-10  7.741750830136e-01 
+ 6.428000000000e-10  7.828445699494e-01 
+ 6.528000000000e-10  7.084631989914e-01 
+ 6.628000000000e-10  5.068703543607e-01 
+ 6.728000000000e-10  1.982651160797e-01 
+ 6.828000000000e-10 -1.180209524418e-01 
+ 6.928000000000e-10 -3.726100259571e-01 
+ 7.028000000000e-10 -5.403229404029e-01 
+ 7.128000000000e-10 -6.438083895554e-01 
+ 7.228000000000e-10 -7.203378638829e-01 
+ 7.328000000000e-10 -7.741273273776e-01 
+ 7.428000000000e-10 -7.828912312659e-01 
+ 7.528000000000e-10 -7.084155733246e-01 
+ 7.628000000000e-10 -5.069185371484e-01 
+ 7.728000000000e-10 -1.982163796445e-01 
+ 7.828000000000e-10  1.179761824049e-01 
+ 7.928000000000e-10  3.726538824343e-01 
+ 8.028000000000e-10  5.402795684719e-01 
+ 8.128000000000e-10  6.438520994328e-01 
+ 8.228000000000e-10  7.202935093188e-01 
+ 8.328000000000e-10  7.741699689895e-01 
+ 8.428000000000e-10  7.828494756723e-01 
+ 8.528000000000e-10  7.084578188073e-01 
+ 8.628000000000e-10  5.068761410729e-01 
+ 8.728000000000e-10  1.982594122387e-01 
+ 8.828000000000e-10 -1.180157633845e-01 
+ 8.928000000000e-10 -3.726154653834e-01 
+ 9.028000000000e-10 -5.403175771302e-01 
+ 9.128000000000e-10 -6.438140825829e-01 
+ 9.228000000000e-10 -7.203322576361e-01 
+ 9.328000000000e-10 -7.741328388949e-01 
+ 9.428000000000e-10 -7.828857350121e-01 
+ 9.528000000000e-10 -7.084208512479e-01 
+ 9.628000000000e-10 -5.069134738545e-01 
+ 9.728000000000e-10 -1.982215797151e-01 
+ 9.828000000000e-10  1.179810466336e-01 
+ 9.928000000000e-10  3.726493985613e-01 
+ 1.000000000000e-09  5.010433738758e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/conditions.yaml
new file mode 100644
index 00000000..63e5d64f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 14
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_14
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb.sch
new file mode 100644
index 00000000..bb1e1970
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb_15.data
new file mode 100644
index 00000000..14866dfa
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_core_tb_15.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.764925698370e-01 
+ 1.728000000000e-10 -1.934019301871e-01 
+ 1.828000000000e-10  1.027850457497e-01 
+ 1.928000000000e-10  3.499528968595e-01 
+ 2.028000000000e-10  5.186059326129e-01 
+ 2.128000000000e-10  6.254912177700e-01 
+ 2.228000000000e-10  6.994356057335e-01 
+ 2.328000000000e-10  7.419604616039e-01 
+ 2.428000000000e-10  7.366001230120e-01 
+ 2.528000000000e-10  6.575586826882e-01 
+ 2.628000000000e-10  4.703480039804e-01 
+ 2.728000000000e-10  1.887311437228e-01 
+ 2.828000000000e-10 -1.064955609068e-01 
+ 2.928000000000e-10 -3.530674432656e-01 
+ 3.028000000000e-10 -5.214103928852e-01 
+ 3.128000000000e-10 -6.276329249236e-01 
+ 3.228000000000e-10 -7.010919569869e-01 
+ 3.328000000000e-10 -7.428528846984e-01 
+ 3.428000000000e-10 -7.371070425945e-01 
+ 3.528000000000e-10 -6.576931102984e-01 
+ 3.628000000000e-10 -4.705213908487e-01 
+ 3.728000000000e-10 -1.887451417089e-01 
+ 3.828000000000e-10  1.063771169054e-01 
+ 3.928000000000e-10  3.530644558224e-01 
+ 4.028000000000e-10  5.212882945537e-01 
+ 4.128000000000e-10  6.276273956697e-01 
+ 4.228000000000e-10  7.009872983885e-01 
+ 4.328000000000e-10  7.428850006835e-01 
+ 4.428000000000e-10  7.370483197885e-01 
+ 4.528000000000e-10  6.577532995019e-01 
+ 4.628000000000e-10  4.704734311564e-01 
+ 4.728000000000e-10  1.888066765623e-01 
+ 4.828000000000e-10 -1.064251900033e-01 
+ 4.928000000000e-10 -3.530110058012e-01 
+ 5.028000000000e-10 -5.213363794122e-01 
+ 5.128000000000e-10 -6.275779961821e-01 
+ 5.228000000000e-10 -7.010367362436e-01 
+ 5.328000000000e-10 -7.428359180793e-01 
+ 5.428000000000e-10 -7.370946234404e-01 
+ 5.528000000000e-10 -6.577041924294e-01 
+ 5.628000000000e-10 -4.705211118057e-01 
+ 5.728000000000e-10 -1.887571402743e-01 
+ 5.828000000000e-10  1.063798390696e-01 
+ 5.928000000000e-10  3.530562876751e-01 
+ 6.028000000000e-10  5.212929538773e-01 
+ 6.128000000000e-10  6.276223718978e-01 
+ 6.228000000000e-10  7.009927681762e-01 
+ 6.328000000000e-10  7.428797293753e-01 
+ 6.428000000000e-10  7.370526578677e-01 
+ 6.528000000000e-10  6.577470674825e-01 
+ 6.628000000000e-10  4.704784998901e-01 
+ 6.728000000000e-10  1.888003575241e-01 
+ 6.828000000000e-10 -1.064204487643e-01 
+ 6.928000000000e-10 -3.530168946500e-01 
+ 7.028000000000e-10 -5.213312567329e-01 
+ 7.128000000000e-10 -6.275838929681e-01 
+ 7.228000000000e-10 -7.010312441909e-01 
+ 7.328000000000e-10 -7.428415937954e-01 
+ 7.428000000000e-10 -7.370893810626e-01 
+ 7.528000000000e-10 -6.577094889087e-01 
+ 7.628000000000e-10 -4.705162397262e-01 
+ 7.728000000000e-10 -1.887623115300e-01 
+ 7.828000000000e-10  1.063847513579e-01 
+ 7.928000000000e-10  3.530516705381e-01 
+ 8.028000000000e-10  5.212973590939e-01 
+ 8.128000000000e-10  6.276181223045e-01 
+ 8.228000000000e-10  7.009970786286e-01 
+ 8.328000000000e-10  7.428754735512e-01 
+ 8.428000000000e-10  7.370567570344e-01 
+ 8.528000000000e-10  6.577427030952e-01 
+ 8.628000000000e-10  4.704830497474e-01 
+ 8.728000000000e-10  1.887958404937e-01 
+ 8.828000000000e-10 -1.064163174914e-01 
+ 8.928000000000e-10 -3.530210908451e-01 
+ 9.028000000000e-10 -5.213271590930e-01 
+ 9.128000000000e-10 -6.275881896870e-01 
+ 9.228000000000e-10 -7.010270518598e-01 
+ 9.328000000000e-10 -7.428457852801e-01 
+ 9.428000000000e-10 -7.370853633469e-01 
+ 9.528000000000e-10 -6.577134719194e-01 
+ 9.628000000000e-10 -4.705123783357e-01 
+ 9.728000000000e-10 -1.887662540331e-01 
+ 9.828000000000e-10  1.063885555413e-01 
+ 9.928000000000e-10  3.530480784075e-01 
+ 1.000000000000e-09  4.814572085440e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/conditions.yaml
new file mode 100644
index 00000000..caf50bc7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 15
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_15
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb.sch
new file mode 100644
index 00000000..1715f9ce
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb_16.data
new file mode 100644
index 00000000..0b2ed0e8
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_core_tb_16.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.643042367579e-01 
+ 1.728000000000e-10 -1.889536448800e-01 
+ 1.828000000000e-10  1.011027156160e-01 
+ 1.928000000000e-10  3.431119917378e-01 
+ 2.028000000000e-10  5.070519088353e-01 
+ 2.128000000000e-10  6.112991757094e-01 
+ 2.228000000000e-10  6.838020209744e-01 
+ 2.328000000000e-10  7.242864479517e-01 
+ 2.428000000000e-10  7.174167448313e-01 
+ 2.528000000000e-10  6.398083866093e-01 
+ 2.628000000000e-10  4.585166519927e-01 
+ 2.728000000000e-10  1.844271573483e-01 
+ 2.828000000000e-10 -1.048019054065e-01 
+ 2.928000000000e-10 -3.462317584687e-01 
+ 3.028000000000e-10 -5.098344721858e-01 
+ 3.128000000000e-10 -6.133899227371e-01 
+ 3.228000000000e-10 -6.853968517792e-01 
+ 3.328000000000e-10 -7.251059393871e-01 
+ 3.428000000000e-10 -7.178642533065e-01 
+ 3.528000000000e-10 -6.398898931720e-01 
+ 3.628000000000e-10 -4.586473976402e-01 
+ 3.728000000000e-10 -1.843989570584e-01 
+ 3.828000000000e-10  1.047140758745e-01 
+ 3.928000000000e-10  3.462576483703e-01 
+ 4.028000000000e-10  5.097333770466e-01 
+ 4.128000000000e-10  6.134023110554e-01 
+ 4.228000000000e-10  6.853047053340e-01 
+ 4.328000000000e-10  7.251501511308e-01 
+ 4.428000000000e-10  7.178117501486e-01 
+ 4.528000000000e-10  6.399568281317e-01 
+ 4.628000000000e-10  4.586017943502e-01 
+ 4.728000000000e-10  1.844658494373e-01 
+ 4.828000000000e-10 -1.047609876408e-01 
+ 4.928000000000e-10 -3.462003104379e-01 
+ 5.028000000000e-10 -5.097813732572e-01 
+ 5.128000000000e-10 -6.133504189098e-01 
+ 5.228000000000e-10 -6.853547602223e-01 
+ 5.328000000000e-10 -7.250985458364e-01 
+ 5.428000000000e-10 -7.178593251267e-01 
+ 5.528000000000e-10 -6.399055102013e-01 
+ 5.628000000000e-10 -4.586511534755e-01 
+ 5.728000000000e-10 -1.844138975484e-01 
+ 5.828000000000e-10  1.047143295024e-01 
+ 5.928000000000e-10  3.462472486482e-01 
+ 6.028000000000e-10  5.097369504642e-01 
+ 6.128000000000e-10  6.133959963639e-01 
+ 6.228000000000e-10  6.853096740322e-01 
+ 6.328000000000e-10  7.251438129543e-01 
+ 6.428000000000e-10  7.178160816468e-01 
+ 6.528000000000e-10  6.399498616471e-01 
+ 6.628000000000e-10  4.586069220749e-01 
+ 6.728000000000e-10  1.844588245643e-01 
+ 6.828000000000e-10 -1.047563687876e-01 
+ 6.928000000000e-10 -3.462063328010e-01 
+ 7.028000000000e-10 -5.097765086741e-01 
+ 7.128000000000e-10 -6.133562893232e-01 
+ 7.228000000000e-10 -6.853494321266e-01 
+ 7.328000000000e-10 -7.251041291885e-01 
+ 7.428000000000e-10 -7.178542203751e-01 
+ 7.528000000000e-10 -6.399107355976e-01 
+ 7.628000000000e-10 -4.586462738291e-01 
+ 7.728000000000e-10 -1.844190131957e-01 
+ 7.828000000000e-10  1.047193339603e-01 
+ 7.928000000000e-10  3.462424630766e-01 
+ 8.028000000000e-10  5.097415276109e-01 
+ 8.128000000000e-10  6.133915881396e-01 
+ 8.228000000000e-10  6.853141467162e-01 
+ 8.328000000000e-10  7.251393167662e-01 
+ 8.428000000000e-10  7.178204152808e-01 
+ 8.528000000000e-10  6.399452651751e-01 
+ 8.628000000000e-10  4.586116651576e-01 
+ 8.728000000000e-10  1.844540563551e-01 
+ 8.828000000000e-10 -1.047521530128e-01 
+ 8.928000000000e-10 -3.462105768541e-01 
+ 9.028000000000e-10 -5.097724238353e-01 
+ 9.128000000000e-10 -6.133605792288e-01 
+ 9.228000000000e-10 -6.853452315529e-01 
+ 9.328000000000e-10 -7.251083207568e-01 
+ 9.428000000000e-10 -7.178502144615e-01 
+ 9.528000000000e-10 -6.399147306347e-01 
+ 9.628000000000e-10 -4.586423495280e-01 
+ 9.728000000000e-10 -1.844229988419e-01 
+ 9.828000000000e-10  1.047232268776e-01 
+ 9.928000000000e-10  3.462387497741e-01 
+ 1.000000000000e-09  4.710752262880e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/conditions.yaml
new file mode 100644
index 00000000..eb92c022
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 16
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_16
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb.sch
new file mode 100644
index 00000000..284b2d92
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb_17.data
new file mode 100644
index 00000000..a6cc3a7a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_core_tb_17.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.852886719505e-01 
+ 1.728000000000e-10 -2.023606658915e-01 
+ 1.828000000000e-10  9.500407548716e-02 
+ 1.928000000000e-10  3.473018630854e-01 
+ 2.028000000000e-10  5.238539974445e-01 
+ 2.128000000000e-10  6.356942626004e-01 
+ 2.228000000000e-10  7.106560719901e-01 
+ 2.328000000000e-10  7.539243132234e-01 
+ 2.428000000000e-10  7.486736309564e-01 
+ 2.528000000000e-10  6.681985082542e-01 
+ 2.628000000000e-10  4.800908099257e-01 
+ 2.728000000000e-10  1.985903293754e-01 
+ 2.828000000000e-10 -9.801965724846e-02 
+ 2.928000000000e-10 -3.499456539083e-01 
+ 3.028000000000e-10 -5.264166063204e-01 
+ 3.128000000000e-10 -6.377599985577e-01 
+ 3.228000000000e-10 -7.123258227204e-01 
+ 3.328000000000e-10 -7.548386637736e-01 
+ 3.428000000000e-10 -7.491646196322e-01 
+ 3.528000000000e-10 -6.682802381819e-01 
+ 3.628000000000e-10 -4.802044877583e-01 
+ 3.728000000000e-10 -1.985554586747e-01 
+ 3.828000000000e-10  9.793570714349e-02 
+ 3.928000000000e-10  3.499705083814e-01 
+ 4.028000000000e-10  5.263126851869e-01 
+ 4.128000000000e-10  6.377668221774e-01 
+ 4.228000000000e-10  7.122256281615e-01 
+ 4.328000000000e-10  7.548735616237e-01 
+ 4.428000000000e-10  7.491068615558e-01 
+ 4.528000000000e-10  6.683430307676e-01 
+ 4.628000000000e-10  4.801581700098e-01 
+ 4.728000000000e-10  1.986186025664e-01 
+ 4.828000000000e-10 -9.798359332438e-02 
+ 4.928000000000e-10 -3.499159407959e-01 
+ 5.028000000000e-10 -5.263605524234e-01 
+ 5.128000000000e-10 -6.377159898188e-01 
+ 5.228000000000e-10 -7.122753084256e-01 
+ 5.328000000000e-10 -7.548237332543e-01 
+ 5.428000000000e-10 -7.491535548765e-01 
+ 5.528000000000e-10 -6.682936663178e-01 
+ 5.628000000000e-10 -4.802057994081e-01 
+ 5.728000000000e-10 -1.985692377738e-01 
+ 5.828000000000e-10  9.793754425939e-02 
+ 5.928000000000e-10  3.499612594703e-01 
+ 6.028000000000e-10  5.263165540334e-01 
+ 6.128000000000e-10  6.377608692392e-01 
+ 6.228000000000e-10  7.122309292959e-01 
+ 6.328000000000e-10  7.548679483739e-01 
+ 6.428000000000e-10  7.491113260135e-01 
+ 6.528000000000e-10  6.683367510584e-01 
+ 6.628000000000e-10  4.801631540398e-01 
+ 6.728000000000e-10  1.986123746205e-01 
+ 6.828000000000e-10 -9.797860547700e-02 
+ 6.928000000000e-10 -3.499219086015e-01 
+ 7.028000000000e-10 -5.263552271330e-01 
+ 7.128000000000e-10 -6.377219921840e-01 
+ 7.228000000000e-10 -7.122696952774e-01 
+ 7.328000000000e-10 -7.548295298651e-01 
+ 7.428000000000e-10 -7.491481908175e-01 
+ 7.528000000000e-10 -6.682991221138e-01 
+ 7.628000000000e-10 -4.802006967346e-01 
+ 7.728000000000e-10 -1.985745887274e-01 
+ 7.828000000000e-10  9.794256695295e-02 
+ 7.928000000000e-10  3.499565849765e-01 
+ 8.028000000000e-10  5.263210489698e-01 
+ 8.128000000000e-10  6.377564579322e-01 
+ 8.228000000000e-10  7.122353719246e-01 
+ 8.328000000000e-10  7.548635649926e-01 
+ 8.428000000000e-10  7.491155123701e-01 
+ 8.528000000000e-10  6.683323549155e-01 
+ 8.628000000000e-10  4.801676539865e-01 
+ 8.728000000000e-10  1.986078923136e-01 
+ 8.828000000000e-10 -9.797434132867e-02 
+ 8.928000000000e-10 -3.499261582655e-01 
+ 9.028000000000e-10 -5.263510069851e-01 
+ 9.128000000000e-10 -6.377263524571e-01 
+ 9.228000000000e-10 -7.122654282965e-01 
+ 9.328000000000e-10 -7.548337908470e-01 
+ 9.428000000000e-10 -7.491440991364e-01 
+ 9.528000000000e-10 -6.683032069827e-01 
+ 9.628000000000e-10 -4.801967157057e-01 
+ 9.728000000000e-10 -1.985786291727e-01 
+ 9.828000000000e-10  9.794644208879e-02 
+ 9.928000000000e-10  3.499529545785e-01 
+ 1.000000000000e-09  4.843355885316e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/conditions.yaml
new file mode 100644
index 00000000..c082f4cc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 17
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_17
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb.sch
new file mode 100644
index 00000000..aeaacc11
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb_18.data
new file mode 100644
index 00000000..a490208f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_core_tb_18.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.747244840755e-01 
+ 1.728000000000e-10  2.031348680811e-01 
+ 1.828000000000e-10 -1.640358346053e-01 
+ 1.928000000000e-10 -4.121983890365e-01 
+ 2.028000000000e-10 -5.403960481430e-01 
+ 2.128000000000e-10 -6.175267008304e-01 
+ 2.228000000000e-10 -7.185181164841e-01 
+ 2.328000000000e-10 -8.111835866476e-01 
+ 2.428000000000e-10 -8.505757111821e-01 
+ 2.528000000000e-10 -7.941523888433e-01 
+ 2.628000000000e-10 -5.697557803605e-01 
+ 2.728000000000e-10 -1.993901761575e-01 
+ 2.828000000000e-10  1.667454340744e-01 
+ 2.928000000000e-10  4.143424459307e-01 
+ 3.028000000000e-10  5.421310172268e-01 
+ 3.128000000000e-10  6.189024162340e-01 
+ 3.228000000000e-10  7.194369498053e-01 
+ 3.328000000000e-10  8.117600127730e-01 
+ 3.428000000000e-10  8.508336653308e-01 
+ 3.528000000000e-10  7.942656656210e-01 
+ 3.628000000000e-10  5.697751550033e-01 
+ 3.728000000000e-10  1.994135726672e-01 
+ 3.828000000000e-10 -1.667386419247e-01 
+ 3.928000000000e-10 -4.143148464313e-01 
+ 4.028000000000e-10 -5.421262038320e-01 
+ 4.128000000000e-10 -6.188832903749e-01 
+ 4.228000000000e-10 -7.194346712496e-01 
+ 4.328000000000e-10 -8.117442314974e-01 
+ 4.428000000000e-10 -8.508381039982e-01 
+ 4.528000000000e-10 -7.942559196005e-01 
+ 4.628000000000e-10 -5.697859373045e-01 
+ 4.728000000000e-10 -1.993975895742e-01 
+ 4.828000000000e-10  1.667322235508e-01 
+ 4.928000000000e-10  4.143280512458e-01 
+ 5.028000000000e-10  5.421195877560e-01 
+ 5.128000000000e-10  6.188968586913e-01 
+ 5.228000000000e-10  7.194236426239e-01 
+ 5.328000000000e-10  8.117540342679e-01 
+ 5.428000000000e-10  8.508266757829e-01 
+ 5.528000000000e-10  7.942652287581e-01 
+ 5.628000000000e-10  5.697754142960e-01 
+ 5.728000000000e-10  1.994033695962e-01 
+ 5.828000000000e-10 -1.667424669503e-01 
+ 5.928000000000e-10 -4.143216611718e-01 
+ 6.028000000000e-10 -5.421291067647e-01 
+ 6.128000000000e-10 -6.188909595847e-01 
+ 6.228000000000e-10 -7.194310352535e-01 
+ 6.328000000000e-10 -8.117467342350e-01 
+ 6.428000000000e-10 -8.508333273630e-01 
+ 6.528000000000e-10 -7.942577903765e-01 
+ 6.628000000000e-10 -5.697836419865e-01 
+ 6.728000000000e-10 -1.993929431350e-01 
+ 6.828000000000e-10  1.667361734044e-01 
+ 6.928000000000e-10  4.143307053824e-01 
+ 7.028000000000e-10  5.421226813799e-01 
+ 7.128000000000e-10  6.189001833416e-01 
+ 7.228000000000e-10  7.194227358993e-01 
+ 7.328000000000e-10  8.117542266055e-01 
+ 7.428000000000e-10  8.508251070290e-01 
+ 7.528000000000e-10  7.942649966766e-01 
+ 7.628000000000e-10  5.697756363247e-01 
+ 7.728000000000e-10  1.993989977467e-01 
+ 7.828000000000e-10 -1.667434615441e-01 
+ 7.928000000000e-10 -4.143248161746e-01 
+ 8.028000000000e-10 -5.421295610790e-01 
+ 8.128000000000e-10 -6.188945163710e-01 
+ 8.228000000000e-10 -7.194289229798e-01 
+ 8.328000000000e-10 -8.117483413843e-01 
+ 8.428000000000e-10 -8.508308647988e-01 
+ 8.528000000000e-10 -7.942590780393e-01 
+ 8.628000000000e-10 -5.697822347435e-01 
+ 8.728000000000e-10 -1.993917000580e-01 
+ 8.828000000000e-10  1.667380255271e-01 
+ 8.928000000000e-10  4.143314131245e-01 
+ 9.028000000000e-10  5.421241182927e-01 
+ 9.128000000000e-10  6.189011822630e-01 
+ 9.228000000000e-10  7.194226089303e-01 
+ 9.328000000000e-10  8.117540798381e-01 
+ 9.428000000000e-10  8.508247577722e-01 
+ 9.528000000000e-10  7.942646412255e-01 
+ 9.628000000000e-10  5.697760282588e-01 
+ 9.728000000000e-10  1.993969946892e-01 
+ 9.828000000000e-10 -1.667434796269e-01 
+ 9.928000000000e-10 -4.143264352220e-01 
+ 1.000000000000e-09 -5.150731751424e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/conditions.yaml
new file mode 100644
index 00000000..4f9367fd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 18
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_18
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb.sch
new file mode 100644
index 00000000..88f38d6f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb_19.data
new file mode 100644
index 00000000..c81efdd4
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_core_tb_19.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.707988120441e-01 
+ 1.728000000000e-10  2.050562196689e-01 
+ 1.828000000000e-10 -1.568083182045e-01 
+ 1.928000000000e-10 -4.020696229917e-01 
+ 2.028000000000e-10 -5.270997867267e-01 
+ 2.128000000000e-10 -6.030122328411e-01 
+ 2.228000000000e-10 -7.060404303518e-01 
+ 2.328000000000e-10 -7.977729548420e-01 
+ 2.428000000000e-10 -8.357087979117e-01 
+ 2.528000000000e-10 -7.823438332914e-01 
+ 2.628000000000e-10 -5.641015035384e-01 
+ 2.728000000000e-10 -1.996979729386e-01 
+ 2.828000000000e-10  1.605395493176e-01 
+ 2.928000000000e-10  4.049019788065e-01 
+ 3.028000000000e-10  5.293349858313e-01 
+ 3.128000000000e-10  6.047755538782e-01 
+ 3.228000000000e-10  7.072083327509e-01 
+ 3.328000000000e-10  7.985177439850e-01 
+ 3.428000000000e-10  8.360745897587e-01 
+ 3.528000000000e-10  7.825643018760e-01 
+ 3.628000000000e-10  5.642043953033e-01 
+ 3.728000000000e-10  1.998026918934e-01 
+ 3.828000000000e-10 -1.604858693758e-01 
+ 3.928000000000e-10 -4.048299316522e-01 
+ 4.028000000000e-10 -5.293048172022e-01 
+ 4.128000000000e-10 -6.047267733392e-01 
+ 4.228000000000e-10 -7.071932602489e-01 
+ 4.328000000000e-10 -7.984844304352e-01 
+ 4.428000000000e-10 -8.360789616419e-01 
+ 4.528000000000e-10 -7.825446968704e-01 
+ 4.628000000000e-10 -5.642205462461e-01 
+ 4.728000000000e-10 -1.997755595675e-01 
+ 4.828000000000e-10  1.604765943145e-01 
+ 4.928000000000e-10  4.048512691297e-01 
+ 5.028000000000e-10  5.292953655278e-01 
+ 5.128000000000e-10  6.047472585148e-01 
+ 5.228000000000e-10  7.071773753770e-01 
+ 5.328000000000e-10  7.985008103891e-01 
+ 5.428000000000e-10  8.360621173440e-01 
+ 5.528000000000e-10  7.825604957102e-01 
+ 5.628000000000e-10  5.642042607215e-01 
+ 5.728000000000e-10  1.997857962408e-01 
+ 5.828000000000e-10 -1.604926267251e-01 
+ 5.928000000000e-10 -4.048407079574e-01 
+ 6.028000000000e-10 -5.293103597207e-01 
+ 6.128000000000e-10 -6.047374718328e-01 
+ 6.228000000000e-10 -7.071895246392e-01 
+ 6.328000000000e-10 -7.984887922220e-01 
+ 6.428000000000e-10 -8.360735876941e-01 
+ 6.528000000000e-10 -7.825482507809e-01 
+ 6.628000000000e-10 -5.642183473935e-01 
+ 6.728000000000e-10 -1.997692084041e-01 
+ 6.828000000000e-10  1.604823178167e-01 
+ 6.928000000000e-10  4.048548923991e-01 
+ 7.028000000000e-10  5.293001528657e-01 
+ 7.128000000000e-10  6.047514904939e-01 
+ 7.228000000000e-10  7.071767775245e-01 
+ 7.328000000000e-10  7.985010886851e-01 
+ 7.428000000000e-10  8.360609061049e-01 
+ 7.528000000000e-10  7.825602391468e-01 
+ 7.628000000000e-10  5.642057995328e-01 
+ 7.728000000000e-10  1.997793833692e-01 
+ 7.828000000000e-10 -1.604939026989e-01 
+ 7.928000000000e-10 -4.048452814924e-01 
+ 8.028000000000e-10 -5.293110935611e-01 
+ 8.128000000000e-10 -6.047422910037e-01 
+ 8.228000000000e-10 -7.071868576548e-01 
+ 8.328000000000e-10 -7.984914661054e-01 
+ 8.428000000000e-10 -8.360704549701e-01 
+ 8.528000000000e-10 -7.825505283213e-01 
+ 8.628000000000e-10 -5.642168951425e-01 
+ 8.728000000000e-10 -1.997675829904e-01 
+ 8.828000000000e-10  1.604850893678e-01 
+ 8.928000000000e-10  4.048557791622e-01 
+ 9.028000000000e-10  5.293024006551e-01 
+ 9.128000000000e-10  6.047526676189e-01 
+ 9.228000000000e-10  7.071769813422e-01 
+ 9.328000000000e-10  7.985009240492e-01 
+ 9.428000000000e-10  8.360608174754e-01 
+ 9.528000000000e-10  7.825597625659e-01 
+ 9.628000000000e-10  5.642070937767e-01 
+ 9.728000000000e-10  1.997763618165e-01 
+ 9.828000000000e-10 -1.604938267743e-01 
+ 9.928000000000e-10 -4.048476936234e-01 
+ 1.000000000000e-09 -5.033604123532e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/conditions.yaml
new file mode 100644
index 00000000..ccf6e277
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 19
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_19
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb.sch
new file mode 100644
index 00000000..ac357f76
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb_20.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb_20.data
new file mode 100644
index 00000000..1c245490
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_core_tb_20.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.787258342535e-01 
+ 1.728000000000e-10  2.078017915173e-01 
+ 1.828000000000e-10 -1.622649468476e-01 
+ 1.928000000000e-10 -4.154784848215e-01 
+ 2.028000000000e-10 -5.503628241592e-01 
+ 2.128000000000e-10 -6.299323770996e-01 
+ 2.228000000000e-10 -7.254942323191e-01 
+ 2.328000000000e-10 -8.176578932008e-01 
+ 2.428000000000e-10 -8.600222409410e-01 
+ 2.528000000000e-10 -8.019093712422e-01 
+ 2.628000000000e-10 -5.756893793886e-01 
+ 2.728000000000e-10 -2.057606209176e-01 
+ 2.828000000000e-10  1.639197157563e-01 
+ 2.928000000000e-10  4.168841038800e-01 
+ 3.028000000000e-10  5.515424627408e-01 
+ 3.128000000000e-10  6.308336221978e-01 
+ 3.228000000000e-10  7.261208861559e-01 
+ 3.328000000000e-10  8.180354096547e-01 
+ 3.428000000000e-10  8.601969327831e-01 
+ 3.528000000000e-10  8.019450515145e-01 
+ 3.628000000000e-10  5.756806762770e-01 
+ 3.728000000000e-10  2.057351595047e-01 
+ 3.828000000000e-10 -1.639234125928e-01 
+ 3.928000000000e-10 -4.168916689126e-01 
+ 4.028000000000e-10 -5.515399403849e-01 
+ 4.128000000000e-10 -6.308421950132e-01 
+ 4.228000000000e-10 -7.261151591955e-01 
+ 4.328000000000e-10 -8.180409257235e-01 
+ 4.428000000000e-10 -8.601903753395e-01 
+ 4.528000000000e-10 -8.019506024478e-01 
+ 4.628000000000e-10 -5.756757498169e-01 
+ 4.728000000000e-10 -2.057370812604e-01 
+ 4.828000000000e-10  1.639284669376e-01 
+ 4.928000000000e-10  4.168895758092e-01 
+ 5.028000000000e-10  5.515444733402e-01 
+ 5.128000000000e-10  6.308408648378e-01 
+ 5.228000000000e-10  7.261175778597e-01 
+ 5.328000000000e-10  8.180376908128e-01 
+ 5.428000000000e-10  8.601923700088e-01 
+ 5.528000000000e-10  8.019470527506e-01 
+ 5.628000000000e-10  5.756789455973e-01 
+ 5.728000000000e-10  2.057316537746e-01 
+ 5.828000000000e-10 -1.639258645561e-01 
+ 5.928000000000e-10 -4.168940343704e-01 
+ 6.028000000000e-10 -5.515416140289e-01 
+ 6.128000000000e-10 -6.308456056710e-01 
+ 6.228000000000e-10 -7.261132930683e-01 
+ 6.328000000000e-10 -8.180415890619e-01 
+ 6.428000000000e-10 -8.601877913845e-01 
+ 6.528000000000e-10 -8.019507055326e-01 
+ 6.628000000000e-10 -5.756748223597e-01 
+ 6.728000000000e-10 -2.057339330851e-01 
+ 6.828000000000e-10  1.639294327626e-01 
+ 6.928000000000e-10  4.168918933453e-01 
+ 7.028000000000e-10  5.515448110547e-01 
+ 7.128000000000e-10  6.308438013344e-01 
+ 7.228000000000e-10  7.261156471026e-01 
+ 7.328000000000e-10  8.180389426729e-01 
+ 7.428000000000e-10  8.601899882644e-01 
+ 7.528000000000e-10  8.019478991926e-01 
+ 7.628000000000e-10  5.756775488816e-01 
+ 7.728000000000e-10  2.057303912126e-01 
+ 7.828000000000e-10 -1.639270777727e-01 
+ 7.928000000000e-10 -4.168949361223e-01 
+ 8.028000000000e-10 -5.515423789761e-01 
+ 8.128000000000e-10 -6.308469511551e-01 
+ 8.228000000000e-10 -7.261125857103e-01 
+ 8.328000000000e-10 -8.180418172660e-01 
+ 8.428000000000e-10 -8.601868536640e-01 
+ 8.528000000000e-10 -8.019506539776e-01 
+ 8.628000000000e-10 -5.756745040863e-01 
+ 8.728000000000e-10 -2.057325997968e-01 
+ 8.828000000000e-10  1.639296206310e-01 
+ 8.928000000000e-10  4.168929982528e-01 
+ 9.028000000000e-10  5.515447184418e-01 
+ 9.128000000000e-10  6.308451859194e-01 
+ 9.228000000000e-10  7.261146020976e-01 
+ 9.328000000000e-10  8.180396416883e-01 
+ 9.428000000000e-10  8.601888436252e-01 
+ 9.528000000000e-10  8.019484098509e-01 
+ 9.628000000000e-10  5.756767177581e-01 
+ 9.728000000000e-10  2.057300830000e-01 
+ 9.828000000000e-10 -1.639276725752e-01 
+ 9.928000000000e-10 -4.168951851932e-01 
+ 1.000000000000e-09 -5.223291820834e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/conditions.yaml
new file mode 100644
index 00000000..35ee6f6e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 20
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_20
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb.sch
new file mode 100644
index 00000000..2466a20b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb_21.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb_21.data
new file mode 100644
index 00000000..18e4ab76
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_core_tb_21.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.573501255338e-01 
+ 1.728000000000e-10  2.075317226020e-01 
+ 1.828000000000e-10 -1.459750710281e-01 
+ 1.928000000000e-10 -3.981214724862e-01 
+ 2.028000000000e-10 -5.378144391949e-01 
+ 2.128000000000e-10 -6.222071778117e-01 
+ 2.228000000000e-10 -7.144656924256e-01 
+ 2.328000000000e-10 -7.957588475985e-01 
+ 2.428000000000e-10 -8.259944634024e-01 
+ 2.528000000000e-10 -7.639419051023e-01 
+ 2.628000000000e-10 -5.499582313836e-01 
+ 2.728000000000e-10 -2.015822705639e-01 
+ 2.828000000000e-10  1.503547149045e-01 
+ 2.928000000000e-10  4.016725871885e-01 
+ 3.028000000000e-10  5.406529598204e-01 
+ 3.128000000000e-10  6.244429748136e-01 
+ 3.228000000000e-10  7.159703736038e-01 
+ 3.328000000000e-10  7.967442303644e-01 
+ 3.428000000000e-10  8.264465978318e-01 
+ 3.528000000000e-10  7.642028659706e-01 
+ 3.628000000000e-10  5.500598536778e-01 
+ 3.728000000000e-10  2.017167809837e-01 
+ 3.828000000000e-10 -1.502994036069e-01 
+ 3.928000000000e-10 -4.015772846450e-01 
+ 4.028000000000e-10 -5.406194194588e-01 
+ 4.128000000000e-10 -6.243734224937e-01 
+ 4.228000000000e-10 -7.159615996115e-01 
+ 4.328000000000e-10 -7.966982014285e-01 
+ 4.428000000000e-10 -8.264613960108e-01 
+ 4.528000000000e-10 -7.641725666632e-01 
+ 4.628000000000e-10 -5.500862997678e-01 
+ 4.728000000000e-10 -2.016863380222e-01 
+ 4.828000000000e-10  1.502773228882e-01 
+ 4.928000000000e-10  4.016041852700e-01 
+ 5.028000000000e-10  5.405973091915e-01 
+ 5.128000000000e-10  6.243995261147e-01 
+ 5.228000000000e-10  7.159367954986e-01 
+ 5.328000000000e-10  7.967237369409e-01 
+ 5.428000000000e-10  8.264362767952e-01 
+ 5.528000000000e-10  7.641972989051e-01 
+ 5.628000000000e-10  5.500612169320e-01 
+ 5.728000000000e-10  2.017098008556e-01 
+ 5.828000000000e-10 -1.502994747055e-01 
+ 5.928000000000e-10 -4.015836624598e-01 
+ 6.028000000000e-10 -5.406181129288e-01 
+ 6.128000000000e-10 -6.243799299897e-01 
+ 6.228000000000e-10 -7.159574419629e-01 
+ 6.328000000000e-10 -7.967036557443e-01 
+ 6.428000000000e-10 -8.264562124237e-01 
+ 6.528000000000e-10 -7.641768324224e-01 
+ 6.628000000000e-10 -5.500832409355e-01 
+ 6.728000000000e-10 -2.016878835950e-01 
+ 6.828000000000e-10  1.502805147690e-01 
+ 6.928000000000e-10  4.016033959904e-01 
+ 7.028000000000e-10  5.405993862387e-01 
+ 7.128000000000e-10  6.243994053085e-01 
+ 7.228000000000e-10  7.159375001908e-01 
+ 7.328000000000e-10  7.967227911979e-01 
+ 7.428000000000e-10  8.264369695557e-01 
+ 7.528000000000e-10  7.641957504676e-01 
+ 7.628000000000e-10  5.500638388088e-01 
+ 7.728000000000e-10  2.017065810230e-01 
+ 7.828000000000e-10 -1.502977706940e-01 
+ 7.928000000000e-10 -4.015868518817e-01 
+ 8.028000000000e-10 -5.406159021220e-01 
+ 8.128000000000e-10 -6.243834226598e-01 
+ 8.228000000000e-10 -7.159542700032e-01 
+ 8.328000000000e-10 -7.967069113699e-01 
+ 8.428000000000e-10 -8.264528986398e-01 
+ 8.528000000000e-10 -7.641796598358e-01 
+ 8.628000000000e-10 -5.500810114131e-01 
+ 8.728000000000e-10 -2.016895461018e-01 
+ 8.828000000000e-10  1.502827695530e-01 
+ 8.928000000000e-10  4.016022282365e-01 
+ 9.028000000000e-10  5.406011687872e-01 
+ 9.128000000000e-10  6.243986267121e-01 
+ 9.228000000000e-10  7.159387803359e-01 
+ 9.328000000000e-10  7.967217157361e-01 
+ 9.428000000000e-10  8.264380732408e-01 
+ 9.528000000000e-10  7.641943142595e-01 
+ 9.628000000000e-10  5.500658668163e-01 
+ 9.728000000000e-10  2.017043552905e-01 
+ 9.828000000000e-10 -1.502962363926e-01 
+ 9.928000000000e-10 -4.015890294030e-01 
+ 1.000000000000e-09 -5.098048460363e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/conditions.yaml
new file mode 100644
index 00000000..f6ff0f82
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 21
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_21
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb.sch
new file mode 100644
index 00000000..69f686b2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb_22.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb_22.data
new file mode 100644
index 00000000..1d781434
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_core_tb_22.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.539342660958e-01 
+ 1.728000000000e-10  2.092356958505e-01 
+ 1.828000000000e-10 -1.399589402437e-01 
+ 1.928000000000e-10 -3.887664135754e-01 
+ 2.028000000000e-10 -5.242925922458e-01 
+ 2.128000000000e-10 -6.069418933180e-01 
+ 2.228000000000e-10 -7.009344183633e-01 
+ 2.328000000000e-10 -7.819154973681e-01 
+ 2.428000000000e-10 -8.115011787752e-01 
+ 2.528000000000e-10 -7.528782125237e-01 
+ 2.628000000000e-10 -5.449881732974e-01 
+ 2.728000000000e-10 -2.018085669996e-01 
+ 2.828000000000e-10  1.453371294429e-01 
+ 2.928000000000e-10  3.930046196046e-01 
+ 3.028000000000e-10  5.275952350978e-01 
+ 3.128000000000e-10  6.094983923497e-01 
+ 3.228000000000e-10  7.026430994561e-01 
+ 3.328000000000e-10  7.830459101342e-01 
+ 3.428000000000e-10  8.120643124066e-01 
+ 3.528000000000e-10  7.532542388222e-01 
+ 3.628000000000e-10  5.451889146656e-01 
+ 3.728000000000e-10  2.020380161925e-01 
+ 3.828000000000e-10 -1.452202245966e-01 
+ 3.928000000000e-10 -3.928550396378e-01 
+ 4.028000000000e-10 -5.275272038156e-01 
+ 4.128000000000e-10 -6.093963788491e-01 
+ 4.228000000000e-10 -7.026185076638e-01 
+ 4.328000000000e-10 -7.829822343256e-01 
+ 4.428000000000e-10 -8.120760322925e-01 
+ 4.528000000000e-10 -7.532137307257e-01 
+ 4.628000000000e-10 -5.452168897181e-01 
+ 4.728000000000e-10 -2.019975663161e-01 
+ 4.828000000000e-10  1.451970774770e-01 
+ 4.928000000000e-10  3.928886426712e-01 
+ 5.028000000000e-10  5.275035947470e-01 
+ 5.128000000000e-10  6.094279224341e-01 
+ 5.228000000000e-10  7.025906785817e-01 
+ 5.328000000000e-10  7.830125874729e-01 
+ 5.428000000000e-10  8.120474298427e-01 
+ 5.528000000000e-10  7.532431353399e-01 
+ 5.628000000000e-10  5.451877569897e-01 
+ 5.728000000000e-10  2.020249691554e-01 
+ 5.828000000000e-10 -1.452230860448e-01 
+ 5.928000000000e-10 -3.928644448798e-01 
+ 6.028000000000e-10 -5.275279936983e-01 
+ 6.128000000000e-10 -6.094050782075e-01 
+ 6.228000000000e-10 -7.026148963104e-01 
+ 6.328000000000e-10 -7.829886841749e-01 
+ 6.428000000000e-10 -8.120708569069e-01 
+ 6.528000000000e-10 -7.532187757848e-01 
+ 6.628000000000e-10 -5.452139572157e-01 
+ 6.728000000000e-10 -2.019983459359e-01 
+ 6.828000000000e-10  1.452010057661e-01 
+ 6.928000000000e-10  3.928879698340e-01 
+ 7.028000000000e-10  5.275064479083e-01 
+ 7.128000000000e-10  6.094280990005e-01 
+ 7.228000000000e-10  7.025917879356e-01 
+ 7.328000000000e-10  7.830113821989e-01 
+ 7.428000000000e-10  8.120485256383e-01 
+ 7.528000000000e-10  7.532412367972e-01 
+ 7.628000000000e-10  5.451912171970e-01 
+ 7.728000000000e-10  2.020204953427e-01 
+ 7.828000000000e-10 -1.452213117731e-01 
+ 7.928000000000e-10 -3.928683087954e-01 
+ 8.028000000000e-10 -5.275257546899e-01 
+ 8.128000000000e-10 -6.094092443435e-01 
+ 8.228000000000e-10 -7.026114152643e-01 
+ 8.328000000000e-10 -7.829924127838e-01 
+ 8.428000000000e-10 -8.120671951794e-01 
+ 8.528000000000e-10 -7.532220607865e-01 
+ 8.628000000000e-10 -5.452116115033e-01 
+ 8.728000000000e-10 -2.019999026100e-01 
+ 8.828000000000e-10  1.452037268076e-01 
+ 8.928000000000e-10  3.928866787285e-01 
+ 9.028000000000e-10  5.275085793907e-01 
+ 9.128000000000e-10  6.094272189130e-01 
+ 9.228000000000e-10  7.025932924679e-01 
+ 9.328000000000e-10  7.830100596429e-01 
+ 9.428000000000e-10  8.120498613680e-01 
+ 9.528000000000e-10  7.532395420815e-01 
+ 9.628000000000e-10  5.451937902396e-01 
+ 9.728000000000e-10  2.020175827840e-01 
+ 9.828000000000e-10 -1.452196157349e-01 
+ 9.928000000000e-10 -3.928709378362e-01 
+ 1.000000000000e-09 -4.979849828547e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/conditions.yaml
new file mode 100644
index 00000000..97923d2c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 22
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_22
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb.sch
new file mode 100644
index 00000000..2c076fbe
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb_23.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb_23.data
new file mode 100644
index 00000000..90cde859
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_core_tb_23.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.609932954578e-01 
+ 1.728000000000e-10  2.135803595156e-01 
+ 1.828000000000e-10 -1.406795105233e-01 
+ 1.928000000000e-10 -3.985242549940e-01 
+ 2.028000000000e-10 -5.467902250199e-01 
+ 2.128000000000e-10 -6.349197102047e-01 
+ 2.228000000000e-10 -7.225601155251e-01 
+ 2.328000000000e-10 -8.022847270862e-01 
+ 2.428000000000e-10 -8.341174139963e-01 
+ 2.528000000000e-10 -7.703472968512e-01 
+ 2.628000000000e-10 -5.554753546701e-01 
+ 2.728000000000e-10 -2.092959847468e-01 
+ 2.828000000000e-10  1.439827087572e-01 
+ 2.928000000000e-10  4.013409764958e-01 
+ 3.028000000000e-10  5.491103575815e-01 
+ 3.128000000000e-10  6.367736171292e-01 
+ 3.228000000000e-10  7.238327114492e-01 
+ 3.328000000000e-10  8.031250424519e-01 
+ 3.428000000000e-10  8.344898451807e-01 
+ 3.528000000000e-10  7.705288945959e-01 
+ 3.628000000000e-10  5.555161552443e-01 
+ 3.728000000000e-10  2.093659332353e-01 
+ 3.828000000000e-10 -1.439645708780e-01 
+ 3.928000000000e-10 -4.012864243472e-01 
+ 4.028000000000e-10 -5.490981432908e-01 
+ 4.128000000000e-10 -6.367310776976e-01 
+ 4.228000000000e-10 -7.238327358891e-01 
+ 4.328000000000e-10 -8.030945225544e-01 
+ 4.428000000000e-10 -8.345032641498e-01 
+ 4.528000000000e-10 -7.705076814073e-01 
+ 4.628000000000e-10 -5.555368200040e-01 
+ 4.728000000000e-10 -2.093450233605e-01 
+ 4.828000000000e-10  1.439466188317e-01 
+ 4.928000000000e-10  4.013057839415e-01 
+ 5.028000000000e-10  5.490801810840e-01 
+ 5.128000000000e-10  6.367502973173e-01 
+ 5.228000000000e-10  7.238134370273e-01 
+ 5.328000000000e-10  8.031142213064e-01 
+ 5.428000000000e-10  8.344836920712e-01 
+ 5.528000000000e-10  7.705267055681e-01 
+ 5.628000000000e-10  5.555176728822e-01 
+ 5.728000000000e-10  2.093634169255e-01 
+ 5.828000000000e-10 -1.439633135714e-01 
+ 5.928000000000e-10 -4.012903718012e-01 
+ 6.028000000000e-10 -5.490957661747e-01 
+ 6.128000000000e-10 -6.367354259501e-01 
+ 6.228000000000e-10 -7.238289911799e-01 
+ 6.328000000000e-10 -8.030991093312e-01 
+ 6.428000000000e-10 -8.344987261970e-01 
+ 6.528000000000e-10 -7.705113506628e-01 
+ 6.628000000000e-10 -5.555339922038e-01 
+ 6.728000000000e-10 -2.093472747698e-01 
+ 6.828000000000e-10  1.439488143392e-01 
+ 6.928000000000e-10  4.013051006454e-01 
+ 7.028000000000e-10  5.490813620131e-01 
+ 7.128000000000e-10  6.367501696447e-01 
+ 7.228000000000e-10  7.238138408460e-01 
+ 7.328000000000e-10  8.031138234310e-01 
+ 7.428000000000e-10  8.344840024625e-01 
+ 7.528000000000e-10  7.705257750612e-01 
+ 7.628000000000e-10  5.555193682491e-01 
+ 7.728000000000e-10  2.093616154732e-01 
+ 7.828000000000e-10 -1.439618235384e-01 
+ 7.928000000000e-10 -4.012927107128e-01 
+ 8.028000000000e-10 -5.490937463184e-01 
+ 8.128000000000e-10 -6.367380404539e-01 
+ 8.228000000000e-10 -7.238264478501e-01 
+ 8.328000000000e-10 -8.031018435980e-01 
+ 8.428000000000e-10 -8.344959687989e-01 
+ 8.528000000000e-10 -7.705137100306e-01 
+ 8.628000000000e-10 -5.555321098787e-01 
+ 8.728000000000e-10 -2.093489927492e-01 
+ 8.828000000000e-10  1.439504269532e-01 
+ 8.928000000000e-10  4.013041525432e-01 
+ 9.028000000000e-10  5.490824887692e-01 
+ 9.128000000000e-10  6.367494882502e-01 
+ 9.228000000000e-10  7.238146944607e-01 
+ 9.328000000000e-10  8.031131051507e-01 
+ 9.428000000000e-10  8.344847147049e-01 
+ 9.528000000000e-10  7.705248067970e-01 
+ 9.628000000000e-10  5.555207970002e-01 
+ 9.728000000000e-10  2.093601819839e-01 
+ 9.828000000000e-10 -1.439605753448e-01 
+ 9.928000000000e-10 -4.012943342775e-01 
+ 1.000000000000e-09 -5.158218772706e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/conditions.yaml
new file mode 100644
index 00000000..7cb02bec
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 23
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_23
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb.sch
new file mode 100644
index 00000000..537eb2a6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb_24.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb_24.data
new file mode 100644
index 00000000..d8c2e7bc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_core_tb_24.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.405028365217e-01 
+ 1.728000000000e-10  2.142897527484e-01 
+ 1.828000000000e-10 -1.231353412434e-01 
+ 1.928000000000e-10 -3.782847553257e-01 
+ 2.028000000000e-10 -5.290944707244e-01 
+ 2.128000000000e-10 -6.207435846591e-01 
+ 2.228000000000e-10 -7.069850917784e-01 
+ 2.328000000000e-10 -7.774395392863e-01 
+ 2.428000000000e-10 -7.982183108700e-01 
+ 2.528000000000e-10 -7.327456021571e-01 
+ 2.628000000000e-10 -5.310063164445e-01 
+ 2.728000000000e-10 -2.063297175293e-01 
+ 2.828000000000e-10  1.293176468138e-01 
+ 2.928000000000e-10  3.835270490977e-01 
+ 3.028000000000e-10  5.333180257023e-01 
+ 3.128000000000e-10  6.240938619865e-01 
+ 3.228000000000e-10  7.092802493907e-01 
+ 3.328000000000e-10  7.789607942300e-01 
+ 3.428000000000e-10  7.989234313230e-01 
+ 3.528000000000e-10  7.331763415294e-01 
+ 3.628000000000e-10  5.312045040772e-01 
+ 3.728000000000e-10  2.065847902134e-01 
+ 3.828000000000e-10 -1.291958906021e-01 
+ 3.928000000000e-10 -3.833411283085e-01 
+ 4.028000000000e-10 -5.332389173297e-01 
+ 4.128000000000e-10 -6.239588708494e-01 
+ 4.228000000000e-10 -7.092541595355e-01 
+ 4.328000000000e-10 -7.788766619073e-01 
+ 4.428000000000e-10 -7.989439817890e-01 
+ 4.528000000000e-10 -7.331237184970e-01 
+ 4.628000000000e-10 -5.312431858800e-01 
+ 4.728000000000e-10 -2.065354720445e-01 
+ 4.828000000000e-10  1.291604530900e-01 
+ 4.928000000000e-10  3.833851407049e-01 
+ 5.028000000000e-10  5.332033925163e-01 
+ 5.128000000000e-10  6.240009303805e-01 
+ 5.228000000000e-10  7.092156296740e-01 
+ 5.328000000000e-10  7.789178950697e-01 
+ 5.428000000000e-10  7.989050835748e-01 
+ 5.528000000000e-10  7.331635644704e-01 
+ 5.628000000000e-10  5.312038508238e-01 
+ 5.728000000000e-10  2.065745538625e-01 
+ 5.828000000000e-10 -1.291960705945e-01 
+ 5.928000000000e-10 -3.833509278886e-01 
+ 6.028000000000e-10 -5.332368573592e-01 
+ 6.128000000000e-10 -6.239679712691e-01 
+ 6.228000000000e-10 -7.092497084655e-01 
+ 6.328000000000e-10 -7.788845366535e-01 
+ 6.428000000000e-10 -7.989377629672e-01 
+ 6.528000000000e-10 -7.331298791234e-01 
+ 6.628000000000e-10 -5.312385744549e-01 
+ 6.728000000000e-10 -2.065399094583e-01 
+ 6.828000000000e-10  1.291646812353e-01 
+ 6.928000000000e-10  3.833822988637e-01 
+ 7.028000000000e-10  5.332062833028e-01 
+ 7.128000000000e-10  6.239988652624e-01 
+ 7.228000000000e-10  7.092181343784e-01 
+ 7.328000000000e-10  7.789155267181e-01 
+ 7.428000000000e-10  7.989074545455e-01 
+ 7.528000000000e-10  7.331605295450e-01 
+ 7.628000000000e-10  5.312080087648e-01 
+ 7.728000000000e-10  2.065705039315e-01 
+ 7.828000000000e-10 -1.291926212165e-01 
+ 7.928000000000e-10 -3.833551733065e-01 
+ 8.028000000000e-10 -5.332328436976e-01 
+ 8.128000000000e-10 -6.239725200032e-01 
+ 8.228000000000e-10 -7.092452956008e-01 
+ 8.328000000000e-10 -7.788891439389e-01 
+ 8.428000000000e-10 -7.989331916474e-01 
+ 8.528000000000e-10 -7.331340451631e-01 
+ 8.628000000000e-10 -5.312350772815e-01 
+ 8.728000000000e-10 -2.065433053799e-01 
+ 8.828000000000e-10  1.291679984852e-01 
+ 8.928000000000e-10  3.833797175156e-01 
+ 9.028000000000e-10  5.332088978420e-01 
+ 9.128000000000e-10  6.239966795455e-01 
+ 9.228000000000e-10  7.092206518532e-01 
+ 9.328000000000e-10  7.789132522577e-01 
+ 9.428000000000e-10  7.989096829456e-01 
+ 9.528000000000e-10  7.331579091452e-01 
+ 9.628000000000e-10  5.312112407565e-01 
+ 9.728000000000e-10  2.065672983353e-01 
+ 9.828000000000e-10 -1.291898675297e-01 
+ 9.928000000000e-10 -3.833583124064e-01 
+ 1.000000000000e-09 -4.991705375338e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/conditions.yaml
new file mode 100644
index 00000000..d6c8c2d6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 24
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_24
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb.sch
new file mode 100644
index 00000000..d5f3541b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb_25.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb_25.data
new file mode 100644
index 00000000..10c03df1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_core_tb_25.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.368449571565e-01 
+ 1.728000000000e-10  2.154696494615e-01 
+ 1.828000000000e-10 -1.180750667507e-01 
+ 1.928000000000e-10 -3.694801437498e-01 
+ 2.028000000000e-10 -5.157339685643e-01 
+ 2.128000000000e-10 -6.051803608378e-01 
+ 2.228000000000e-10 -6.923688047900e-01 
+ 2.328000000000e-10 -7.627278516708e-01 
+ 2.428000000000e-10 -7.836324050269e-01 
+ 2.528000000000e-10 -7.217390774868e-01 
+ 2.628000000000e-10 -5.258344598842e-01 
+ 2.728000000000e-10 -2.060622799160e-01 
+ 2.828000000000e-10  1.253068918672e-01 
+ 2.928000000000e-10  3.754763463876e-01 
+ 3.028000000000e-10  5.204513706872e-01 
+ 3.128000000000e-10  6.088547126517e-01 
+ 3.228000000000e-10  6.948747427610e-01 
+ 3.328000000000e-10  7.643967320598e-01 
+ 3.428000000000e-10  7.844541546789e-01 
+ 3.528000000000e-10  7.222905371020e-01 
+ 3.628000000000e-10  5.261436989659e-01 
+ 3.728000000000e-10  2.064244494061e-01 
+ 3.828000000000e-10 -1.251087630483e-01 
+ 3.928000000000e-10 -3.752230316775e-01 
+ 4.028000000000e-10 -5.203274407129e-01 
+ 4.128000000000e-10 -6.086807930540e-01 
+ 4.228000000000e-10 -6.948278459755e-01 
+ 4.328000000000e-10 -7.642927444658e-01 
+ 4.428000000000e-10 -7.844689558048e-01 
+ 4.528000000000e-10 -7.222270537973e-01 
+ 4.628000000000e-10 -5.261810188038e-01 
+ 4.728000000000e-10 -2.063649367923e-01 
+ 4.828000000000e-10  1.250740150254e-01 
+ 4.928000000000e-10  3.752740624702e-01 
+ 5.028000000000e-10  5.202917067072e-01 
+ 5.128000000000e-10  6.087280474834e-01 
+ 5.228000000000e-10  6.947875493975e-01 
+ 5.328000000000e-10  7.643381446772e-01 
+ 5.428000000000e-10  7.844278436925e-01 
+ 5.528000000000e-10  7.222707134126e-01 
+ 5.628000000000e-10  5.261386731045e-01 
+ 5.728000000000e-10  2.064078101390e-01 
+ 5.828000000000e-10 -1.251125509614e-01 
+ 5.928000000000e-10 -3.752362786491e-01 
+ 6.028000000000e-10 -5.203279553884e-01 
+ 6.128000000000e-10 -6.086920089480e-01 
+ 6.228000000000e-10 -6.948246280643e-01 
+ 6.328000000000e-10 -7.643013046090e-01 
+ 6.428000000000e-10 -7.844633201903e-01 
+ 6.528000000000e-10 -7.222336042293e-01 
+ 6.628000000000e-10 -5.261766512068e-01 
+ 6.728000000000e-10 -2.063691829929e-01 
+ 6.828000000000e-10  1.250784814444e-01 
+ 6.928000000000e-10  3.752708432251e-01 
+ 7.028000000000e-10  5.202949527958e-01 
+ 7.128000000000e-10  6.087256874770e-01 
+ 7.228000000000e-10  6.947904319095e-01 
+ 7.328000000000e-10  7.643352365607e-01 
+ 7.428000000000e-10  7.844306677783e-01 
+ 7.528000000000e-10  7.222672114429e-01 
+ 7.628000000000e-10  5.261433781551e-01 
+ 7.728000000000e-10  2.064029029490e-01 
+ 7.828000000000e-10 -1.251089390610e-01 
+ 7.928000000000e-10 -3.752408867518e-01 
+ 8.028000000000e-10 -5.203238706374e-01 
+ 8.128000000000e-10 -6.086968714397e-01 
+ 8.228000000000e-10 -6.948200705245e-01 
+ 8.328000000000e-10 -7.643060605343e-01 
+ 8.428000000000e-10 -7.844586734539e-01 
+ 8.528000000000e-10 -7.222379683754e-01 
+ 8.628000000000e-10 -5.261730442965e-01 
+ 8.728000000000e-10 -2.063725681788e-01 
+ 8.828000000000e-10  1.250820910423e-01 
+ 8.928000000000e-10  3.752680406761e-01 
+ 9.028000000000e-10  5.202978581562e-01 
+ 9.128000000000e-10  6.087233210610e-01 
+ 9.228000000000e-10  6.947932359489e-01 
+ 9.328000000000e-10  7.643326365950e-01 
+ 9.428000000000e-10  7.844331791786e-01 
+ 9.528000000000e-10  7.222642751837e-01 
+ 9.628000000000e-10  5.261469613157e-01 
+ 9.728000000000e-10  2.063991803079e-01 
+ 9.828000000000e-10 -1.251060220915e-01 
+ 9.928000000000e-10 -3.752443155305e-01 
+ 1.000000000000e-09 -4.875704709340e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/conditions.yaml
new file mode 100644
index 00000000..43e5069a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 25
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_25
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb.sch
new file mode 100644
index 00000000..e9ecf884
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0.3
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb_26.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb_26.data
new file mode 100644
index 00000000..0eed4736
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_core_tb_26.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.436948212736e-01 
+ 1.728000000000e-10  2.205877879634e-01 
+ 1.828000000000e-10 -1.163348151974e-01 
+ 1.928000000000e-10 -3.771420921807e-01 
+ 2.028000000000e-10 -5.370108455130e-01 
+ 2.128000000000e-10 -6.331888427572e-01 
+ 2.228000000000e-10 -7.164762236683e-01 
+ 2.328000000000e-10 -7.851286946760e-01 
+ 2.428000000000e-10 -8.059531868761e-01 
+ 2.528000000000e-10 -7.384564800459e-01 
+ 2.628000000000e-10 -5.363144999221e-01 
+ 2.728000000000e-10 -2.144637665285e-01 
+ 2.828000000000e-10  1.212929793685e-01 
+ 2.928000000000e-10  3.815418180812e-01 
+ 3.028000000000e-10  5.406606883043e-01 
+ 3.128000000000e-10  6.361475176918e-01 
+ 3.228000000000e-10  7.185360719894e-01 
+ 3.328000000000e-10  7.865091736067e-01 
+ 3.428000000000e-10  8.065713749450e-01 
+ 3.528000000000e-10  7.387921596039e-01 
+ 3.628000000000e-10  5.364259512539e-01 
+ 3.728000000000e-10  2.146317863835e-01 
+ 3.828000000000e-10 -1.212295238309e-01 
+ 3.928000000000e-10 -3.814110096077e-01 
+ 4.028000000000e-10 -5.406166203788e-01 
+ 4.128000000000e-10 -6.360467438854e-01 
+ 4.228000000000e-10 -7.185257686739e-01 
+ 4.328000000000e-10 -7.864422304189e-01 
+ 4.428000000000e-10 -8.065937411295e-01 
+ 4.528000000000e-10 -7.387487319623e-01 
+ 4.628000000000e-10 -5.364619855530e-01 
+ 4.728000000000e-10 -2.145913861363e-01 
+ 4.828000000000e-10  1.211959412322e-01 
+ 4.928000000000e-10  3.814481551476e-01 
+ 5.028000000000e-10  5.405833390120e-01 
+ 5.128000000000e-10  6.360831449777e-01 
+ 5.228000000000e-10  7.184907253890e-01 
+ 5.328000000000e-10  7.864786648334e-01 
+ 5.428000000000e-10  8.065585198321e-01 
+ 5.528000000000e-10  7.387840006966e-01 
+ 5.628000000000e-10  5.364270346085e-01 
+ 5.728000000000e-10  2.146260338485e-01 
+ 5.828000000000e-10 -1.212277001076e-01 
+ 5.928000000000e-10 -3.814182410321e-01 
+ 6.028000000000e-10 -5.406130595607e-01 
+ 6.128000000000e-10 -6.360540210765e-01 
+ 6.228000000000e-10 -7.185209180994e-01 
+ 6.328000000000e-10 -7.864492678158e-01 
+ 6.428000000000e-10 -8.065874846616e-01 
+ 6.528000000000e-10 -7.387544794760e-01 
+ 6.628000000000e-10 -5.364572547805e-01 
+ 6.728000000000e-10 -2.145959871001e-01 
+ 6.828000000000e-10  1.211997934696e-01 
+ 6.928000000000e-10  3.814456726213e-01 
+ 7.028000000000e-10  5.405857946323e-01 
+ 7.128000000000e-10  6.360813265814e-01 
+ 7.228000000000e-10  7.184929266665e-01 
+ 7.328000000000e-10  7.864767243186e-01 
+ 7.428000000000e-10  8.065604357181e-01 
+ 7.528000000000e-10  7.387815158779e-01 
+ 7.628000000000e-10  5.364303644926e-01 
+ 7.728000000000e-10  2.146228844142e-01 
+ 7.828000000000e-10 -1.212245339809e-01 
+ 7.928000000000e-10 -3.814220075435e-01 
+ 8.028000000000e-10 -5.406092538148e-01 
+ 8.128000000000e-10 -6.360581238583e-01 
+ 8.228000000000e-10 -7.185168954112e-01 
+ 8.328000000000e-10 -7.864535273883e-01 
+ 8.428000000000e-10 -8.065831328643e-01 
+ 8.528000000000e-10 -7.387583532284e-01 
+ 8.628000000000e-10 -5.364538735708e-01 
+ 8.728000000000e-10 -2.145992968151e-01 
+ 8.828000000000e-10  1.212027591883e-01 
+ 8.928000000000e-10  3.814433789143e-01 
+ 9.028000000000e-10  5.405880431190e-01 
+ 9.128000000000e-10  6.360793794817e-01 
+ 9.228000000000e-10  7.184951630330e-01 
+ 9.328000000000e-10  7.864747526663e-01 
+ 9.428000000000e-10  8.065622905723e-01 
+ 9.528000000000e-10  7.387792872630e-01 
+ 9.628000000000e-10  5.364330391099e-01 
+ 9.728000000000e-10  2.146202349236e-01 
+ 9.828000000000e-10 -1.212220310216e-01 
+ 9.928000000000e-10 -3.814247853449e-01 
+ 1.000000000000e-09 -5.040490090913e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/conditions.yaml
new file mode 100644
index 00000000..0bd90bf0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 26
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/run_26
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/simulation_summary.csv
new file mode 100644
index 00000000..2f5f947b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/simulation_summary.csv
@@ -0,0 +1,28 @@
+run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing
+run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.952e-01, -6.044e-02, 0.182, …]",4.722e+09,0.709,1.418
+run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.648e-01, -3.672e-02, 0.198, …]",4.722e+09,0.693,1.386
+run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.227e-01, -8.540e-02, 0.161, …]",4.722e+09,0.722,1.444
+run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.752e-01, -5.371e-02, 0.179, …]",4.722e+09,0.692,1.383
+run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.482e-01, -3.259e-02, 0.193, …]",4.722e+09,0.672,1.345
+run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-3.027e-01, -8.046e-02, 0.156, …]",4.722e+09,0.706,1.412
+run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.659e-01, -5.659e-02, 0.167, …]",4.722e+09,0.669,1.338
+run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.411e-01, -3.745e-02, 0.179, …]",4.722e+09,0.648,1.295
+run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-2.916e-01, -8.207e-02, 0.144, …]",4.722e+09,0.685,1.371
+run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.397e-01, -2.046e-01, 0.131, …]",4.722e+09,0.807,1.614
+run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.293e-01, -2.034e-01, 0.125, …]",4.722e+09,0.789,1.577
+run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.474e-01, -2.088e-01, 0.131, …]",4.722e+09,0.819,1.638
+run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.050e-01, -1.958e-01, 0.120, …]",4.722e+09,0.771,1.543
+run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.935e-01, -1.929e-01, 0.116, …]",4.722e+09,0.753,1.505
+run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.133e-01, -2.032e-01, 0.114, …]",4.722e+09,0.783,1.566
+run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.765e-01, -1.934e-01, 0.103, …]",4.722e+09,0.743,1.486
+run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.643e-01, -1.890e-01, 0.101, …]",4.722e+09,0.725,1.450
+run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.853e-01, -2.024e-01, 9.500e-02, …]",4.722e+09,0.755,1.510
+run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.575, 0.203, -1.640e-01, …]",4.722e+09,0.851,1.702
+run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.571, 0.205, -1.568e-01, …]",4.722e+09,0.836,1.672
+run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.579, 0.208, -1.623e-01, …]",4.722e+09,0.860,1.720
+run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.557, 0.208, -1.460e-01, …]",4.722e+09,0.826,1.653
+run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.554, 0.209, -1.400e-01, …]",4.722e+09,0.812,1.624
+run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.561, 0.214, -1.407e-01, …]",4.722e+09,0.834,1.669
+run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.541, 0.214, -1.231e-01, …]",4.722e+09,0.799,1.598
+run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.537, 0.215, -1.181e-01, …]",4.722e+09,0.784,1.569
+run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.544, 0.221, -1.163e-01, …]",4.722e+09,0.807,1.613
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/simulation_summary.md
new file mode 100644
index 00000000..6401031e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/simulation_summary.md
@@ -0,0 +1,31 @@
+# Simulation Summary for CML divider frequency response
+
+| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing |
+| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: |
+| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.952e-01, -6.044e-02, 0.182, …] | 4.722e+09 | 0.709 | 1.418 |
+| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.648e-01, -3.672e-02, 0.198, …] | 4.722e+09 | 0.693 | 1.386 |
+| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.227e-01, -8.540e-02, 0.161, …] | 4.722e+09 | 0.722 | 1.444 |
+| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.752e-01, -5.371e-02, 0.179, …] | 4.722e+09 | 0.692 | 1.383 |
+| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.482e-01, -3.259e-02, 0.193, …] | 4.722e+09 | 0.672 | 1.345 |
+| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-3.027e-01, -8.046e-02, 0.156, …] | 4.722e+09 | 0.706 | 1.412 |
+| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.659e-01, -5.659e-02, 0.167, …] | 4.722e+09 | 0.669 | 1.338 |
+| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.411e-01, -3.745e-02, 0.179, …] | 4.722e+09 | 0.648 | 1.295 |
+| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-2.916e-01, -8.207e-02, 0.144, …] | 4.722e+09 | 0.685 | 1.371 |
+| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.397e-01, -2.046e-01, 0.131, …] | 4.722e+09 | 0.807 | 1.614 |
+| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.293e-01, -2.034e-01, 0.125, …] | 4.722e+09 | 0.789 | 1.577 |
+| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.474e-01, -2.088e-01, 0.131, …] | 4.722e+09 | 0.819 | 1.638 |
+| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.050e-01, -1.958e-01, 0.120, …] | 4.722e+09 | 0.771 | 1.543 |
+| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.935e-01, -1.929e-01, 0.116, …] | 4.722e+09 | 0.753 | 1.505 |
+| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.133e-01, -2.032e-01, 0.114, …] | 4.722e+09 | 0.783 | 1.566 |
+| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.765e-01, -1.934e-01, 0.103, …] | 4.722e+09 | 0.743 | 1.486 |
+| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.643e-01, -1.890e-01, 0.101, …] | 4.722e+09 | 0.725 | 1.450 |
+| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.853e-01, -2.024e-01, 9.500e-02, …] | 4.722e+09 | 0.755 | 1.510 |
+| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.575, 0.203, -1.640e-01, …] | 4.722e+09 | 0.851 | 1.702 |
+| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.571, 0.205, -1.568e-01, …] | 4.722e+09 | 0.836 | 1.672 |
+| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.579, 0.208, -1.623e-01, …] | 4.722e+09 | 0.860 | 1.720 |
+| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.557, 0.208, -1.460e-01, …] | 4.722e+09 | 0.826 | 1.653 |
+| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.554, 0.209, -1.400e-01, …] | 4.722e+09 | 0.812 | 1.624 |
+| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.561, 0.214, -1.407e-01, …] | 4.722e+09 | 0.834 | 1.669 |
+| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.541, 0.214, -1.231e-01, …] | 4.722e+09 | 0.799 | 1.598 |
+| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.537, 0.215, -1.181e-01, …] | 4.722e+09 | 0.784 | 1.569 |
+| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.544, 0.221, -1.163e-01, …] | 4.722e+09 | 0.807 | 1.613 |
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/vo_diff_vs_time.png
new file mode 100644
index 00000000..64d1b808
Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/parameters/ac_params/vo_diff_vs_time.png differ
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/summary.md
new file mode 100644
index 00000000..a11c2c65
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-42-46/summary.md
@@ -0,0 +1,11 @@
+
+# CACE Summary for CML_divider
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |  4.722 GHz |      5.0 GHz |  4.722 GHz |      5.2 GHz |  4.722 GHz |   Pass ✅    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |    0.648 V |        0.4 V |    0.771 V |        0.6 V |    0.860 V |   Fail ❌    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |    1.295 V |        0.8 V |    1.543 V |        1.2 V |    1.720 V |   Fail ❌    |
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/CML_core_tb.sch
new file mode 100644
index 00000000..0f707234
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb.sch
new file mode 100644
index 00000000..5a875307
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb_0.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb_0.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb_0.data
new file mode 100644
index 00000000..66b58199
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_core_tb_0.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  4.172295258702e-01 
+ 1.728000000000e-10  5.660306289841e-01 
+ 1.828000000000e-10  6.427714835619e-01 
+ 1.928000000000e-10  6.309902240882e-01 
+ 2.028000000000e-10  5.294294766946e-01 
+ 2.128000000000e-10  3.620240344858e-01 
+ 2.228000000000e-10  1.640234450884e-01 
+ 2.328000000000e-10 -4.612275905861e-02 
+ 2.428000000000e-10 -2.579117429775e-01 
+ 2.528000000000e-10 -4.481189355521e-01 
+ 2.628000000000e-10 -5.863632401034e-01 
+ 2.728000000000e-10 -6.500797909801e-01 
+ 2.828000000000e-10 -6.244800987133e-01 
+ 2.928000000000e-10 -5.114796948453e-01 
+ 3.028000000000e-10 -3.375169508656e-01 
+ 3.128000000000e-10 -1.371992811787e-01 
+ 3.228000000000e-10  7.406969194951e-02 
+ 3.328000000000e-10  2.845715128812e-01 
+ 3.428000000000e-10  4.697496179395e-01 
+ 3.528000000000e-10  5.992920985552e-01 
+ 3.628000000000e-10  6.520148385162e-01 
+ 3.728000000000e-10  6.144241739579e-01 
+ 3.828000000000e-10  4.915878717611e-01 
+ 3.928000000000e-10  3.124248149666e-01 
+ 4.028000000000e-10  1.102877163723e-01 
+ 4.128000000000e-10 -1.018116542879e-01 
+ 4.228000000000e-10 -3.106348763410e-01 
+ 4.328000000000e-10 -4.902750974502e-01 
+ 4.428000000000e-10 -6.108946985102e-01 
+ 4.528000000000e-10 -6.523720773639e-01 
+ 4.628000000000e-10 -6.029054191106e-01 
+ 4.728000000000e-10 -4.707230721172e-01 
+ 4.828000000000e-10 -2.870097642856e-01 
+ 4.928000000000e-10 -8.317192159450e-02 
+ 5.028000000000e-10  1.295203952971e-01 
+ 5.128000000000e-10  3.362518112840e-01 
+ 5.228000000000e-10  5.097742084312e-01 
+ 5.328000000000e-10  6.211919546772e-01 
+ 5.428000000000e-10  6.511756762383e-01 
+ 5.528000000000e-10  5.899749487975e-01 
+ 5.628000000000e-10  4.489748742278e-01 
+ 5.728000000000e-10  2.613211253429e-01 
+ 5.828000000000e-10  5.587544382072e-02 
+ 5.928000000000e-10 -1.571477580061e-01 
+ 6.028000000000e-10 -3.613437817138e-01 
+ 6.128000000000e-10 -5.281831591597e-01 
+ 6.228000000000e-10 -6.301006152887e-01 
+ 6.328000000000e-10 -6.483960457705e-01 
+ 6.428000000000e-10 -5.756654257371e-01 
+ 6.528000000000e-10 -4.264399047824e-01 
+ 6.628000000000e-10 -2.354004817627e-01 
+ 6.728000000000e-10 -2.842675634560e-02 
+ 6.828000000000e-10  1.846345692911e-01 
+ 6.928000000000e-10  3.858281396610e-01 
+ 7.028000000000e-10  5.454514092524e-01 
+ 7.128000000000e-10  6.375581744727e-01 
+ 7.228000000000e-10  6.440263958793e-01 
+ 7.328000000000e-10  5.600361282065e-01 
+ 7.428000000000e-10  4.031839179600e-01 
+ 7.528000000000e-10  2.092376914444e-01 
+ 7.628000000000e-10  8.502356190527e-04 
+ 7.728000000000e-10 -2.119337824727e-01 
+ 7.828000000000e-10 -4.096116454145e-01 
+ 7.928000000000e-10 -5.615497053806e-01 
+ 8.028000000000e-10 -6.435211973252e-01 
+ 8.128000000000e-10 -6.380709280118e-01 
+ 8.228000000000e-10 -5.431342908426e-01 
+ 8.328000000000e-10 -3.792993370635e-01 
+ 8.428000000000e-10 -1.828419681275e-01 
+ 8.528000000000e-10  2.683833801096e-02 
+ 8.628000000000e-10  2.390033411822e-01 
+ 8.728000000000e-10  4.326291356130e-01 
+ 8.828000000000e-10  5.764809726856e-01 
+ 8.928000000000e-10  6.479900106917e-01 
+ 9.028000000000e-10  6.305680198179e-01 
+ 9.128000000000e-10  5.250415256290e-01 
+ 9.228000000000e-10  3.548834257623e-01 
+ 9.328000000000e-10  1.562248890761e-01 
+ 9.428000000000e-10 -5.459580212146e-02 
+ 9.528000000000e-10 -2.657781449274e-01 
+ 9.628000000000e-10 -4.547945612946e-01 
+ 9.728000000000e-10 -5.902149502308e-01 
+ 9.828000000000e-10 -6.509292568482e-01 
+ 9.928000000000e-10 -6.215366113118e-01 
+ 1.000000000000e-09 -5.446631202469e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/conditions.yaml
new file mode 100644
index 00000000..5e0cf1a6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 0
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_00
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb.sch
new file mode 100644
index 00000000..d89df912
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb_1.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb_1.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb_1.data
new file mode 100644
index 00000000..09b2cf28
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_core_tb_1.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.883390876595e-01 
+ 1.728000000000e-10  5.408201711303e-01 
+ 1.828000000000e-10  6.237425658147e-01 
+ 1.928000000000e-10  6.212954997578e-01 
+ 2.028000000000e-10  5.309611858082e-01 
+ 2.128000000000e-10  3.727669362568e-01 
+ 2.228000000000e-10  1.799806712761e-01 
+ 2.328000000000e-10 -2.603148458398e-02 
+ 2.428000000000e-10 -2.346564323193e-01 
+ 2.528000000000e-10 -4.242479038446e-01 
+ 2.628000000000e-10 -5.649526956169e-01 
+ 2.728000000000e-10 -6.329728273322e-01 
+ 2.828000000000e-10 -6.146559746281e-01 
+ 2.928000000000e-10 -5.108371727377e-01 
+ 3.028000000000e-10 -3.442884446101e-01 
+ 3.128000000000e-10 -1.483824207161e-01 
+ 3.228000000000e-10  5.906028995990e-02 
+ 3.328000000000e-10  2.664145911003e-01 
+ 3.428000000000e-10  4.504551879416e-01 
+ 3.528000000000e-10  5.809008844736e-01 
+ 3.628000000000e-10  6.360567187756e-01 
+ 3.728000000000e-10  6.037436816278e-01 
+ 3.828000000000e-10  4.881225452421e-01 
+ 3.928000000000e-10  3.148407462953e-01 
+ 4.028000000000e-10  1.165218007575e-01 
+ 4.128000000000e-10 -9.193574793921e-02 
+ 4.228000000000e-10 -2.974342499544e-01 
+ 4.328000000000e-10 -4.751326768798e-01 
+ 4.428000000000e-10 -5.949346596006e-01 
+ 4.528000000000e-10 -6.369164704138e-01 
+ 4.628000000000e-10 -5.907458792091e-01 
+ 4.728000000000e-10 -4.639467590464e-01 
+ 4.828000000000e-10 -2.848562973336e-01 
+ 4.928000000000e-10 -8.437689253965e-02 
+ 5.028000000000e-10  1.247629474968e-01 
+ 5.128000000000e-10  3.278244343609e-01 
+ 5.228000000000e-10  4.983346669982e-01 
+ 5.328000000000e-10  6.070914453050e-01 
+ 5.428000000000e-10  6.355806464383e-01 
+ 5.528000000000e-10  5.757490218128e-01 
+ 5.628000000000e-10  4.384583523195e-01 
+ 5.728000000000e-10  2.544319838869e-01 
+ 5.828000000000e-10  5.198316416371e-02 
+ 5.928000000000e-10 -1.574660223817e-01 
+ 6.028000000000e-10 -3.574666910126e-01 
+ 6.128000000000e-10 -5.199664726946e-01 
+ 6.228000000000e-10 -6.172633670247e-01 
+ 6.328000000000e-10 -6.320252018899e-01 
+ 6.428000000000e-10 -5.588131771792e-01 
+ 6.528000000000e-10 -4.118134126240e-01 
+ 6.628000000000e-10 -2.236388151954e-01 
+ 6.728000000000e-10 -1.939350560218e-02 
+ 6.828000000000e-10  1.899440121342e-01 
+ 6.928000000000e-10  3.862188408687e-01 
+ 7.028000000000e-10  5.399416899491e-01 
+ 7.128000000000e-10  6.253721966482e-01 
+ 7.228000000000e-10  6.262505877611e-01 
+ 7.328000000000e-10  5.400360393825e-01 
+ 7.428000000000e-10  3.841445496134e-01 
+ 7.528000000000e-10  1.924821267214e-01 
+ 7.628000000000e-10 -1.335772409919e-02 
+ 7.728000000000e-10 -2.221234295217e-01 
+ 7.828000000000e-10 -4.139356901001e-01 
+ 7.928000000000e-10 -5.582208930433e-01 
+ 8.028000000000e-10 -6.313676734981e-01 
+ 8.128000000000e-10 -6.182838529344e-01 
+ 8.228000000000e-10 -5.195061658404e-01 
+ 8.328000000000e-10 -3.556114902208e-01 
+ 8.428000000000e-10 -1.609892428532e-01 
+ 8.528000000000e-10  4.622340719895e-02 
+ 8.628000000000e-10  2.539143850297e-01 
+ 8.728000000000e-10  4.404846384078e-01 
+ 8.828000000000e-10  5.747805062647e-01 
+ 8.928000000000e-10  6.352424586450e-01 
+ 9.028000000000e-10  6.081834380184e-01 
+ 9.128000000000e-10  4.973521296985e-01 
+ 9.228000000000e-10  3.263756894147e-01 
+ 9.328000000000e-10  1.291897894332e-01 
+ 9.428000000000e-10 -7.912913934513e-02 
+ 9.528000000000e-10 -2.852083523069e-01 
+ 9.628000000000e-10 -4.657099955095e-01 
+ 9.728000000000e-10 -5.895419772383e-01 
+ 9.828000000000e-10 -6.369389667120e-01 
+ 9.928000000000e-10 -5.959930992809e-01 
+ 1.000000000000e-09 -5.138392169398e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/conditions.yaml
new file mode 100644
index 00000000..53deb0f2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 1
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_01
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb.sch
new file mode 100644
index 00000000..3278780c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb_2.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb_2.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb_2.data
new file mode 100644
index 00000000..ef2eb41d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_core_tb_2.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  4.369784277324e-01 
+ 1.728000000000e-10  5.844303264451e-01 
+ 1.828000000000e-10  6.576704604404e-01 
+ 1.928000000000e-10  6.389429128039e-01 
+ 2.028000000000e-10  5.287476203431e-01 
+ 2.128000000000e-10  3.556487123432e-01 
+ 2.228000000000e-10  1.563418818172e-01 
+ 2.328000000000e-10 -5.502691143237e-02 
+ 2.428000000000e-10 -2.693404771282e-01 
+ 2.528000000000e-10 -4.618915081145e-01 
+ 2.628000000000e-10 -6.008858148447e-01 
+ 2.728000000000e-10 -6.639573195925e-01 
+ 2.828000000000e-10 -6.345947706320e-01 
+ 2.928000000000e-10 -5.159306555046e-01 
+ 3.028000000000e-10 -3.383759499466e-01 
+ 3.128000000000e-10 -1.375370817241e-01 
+ 3.228000000000e-10  7.475314631072e-02 
+ 3.328000000000e-10  2.882433328129e-01 
+ 3.428000000000e-10  4.772006954996e-01 
+ 3.528000000000e-10  6.100237090738e-01 
+ 3.628000000000e-10  6.652131671859e-01 
+ 3.728000000000e-10  6.272348898736e-01 
+ 3.828000000000e-10  5.017111005409e-01 
+ 3.928000000000e-10  3.208176059829e-01 
+ 4.028000000000e-10  1.188347173379e-01 
+ 4.128000000000e-10 -9.421906833550e-02 
+ 4.228000000000e-10 -3.067231995217e-01 
+ 4.328000000000e-10 -4.918821205637e-01 
+ 4.428000000000e-10 -6.185156844977e-01 
+ 4.528000000000e-10 -6.657095473383e-01 
+ 4.628000000000e-10 -6.191782362066e-01 
+ 4.728000000000e-10 -4.870441103398e-01 
+ 4.828000000000e-10 -3.031237925016e-01 
+ 4.928000000000e-10 -1.000018396065e-01 
+ 5.028000000000e-10  1.137158888499e-01 
+ 5.128000000000e-10  3.250317818347e-01 
+ 5.228000000000e-10  5.060979436969e-01 
+ 5.328000000000e-10  6.264062533570e-01 
+ 5.428000000000e-10  6.654548423706e-01 
+ 5.528000000000e-10  6.104263907841e-01 
+ 5.628000000000e-10  4.719575676260e-01 
+ 5.728000000000e-10  2.853143594971e-01 
+ 5.828000000000e-10  8.106414726920e-02 
+ 5.928000000000e-10 -1.332038364715e-01 
+ 6.028000000000e-10 -3.431129576746e-01 
+ 6.128000000000e-10 -5.197947732430e-01 
+ 6.228000000000e-10 -6.336444564921e-01 
+ 6.328000000000e-10 -6.644191517138e-01 
+ 6.428000000000e-10 -6.009859600646e-01 
+ 6.528000000000e-10 -4.564780986599e-01 
+ 6.628000000000e-10 -2.673977907968e-01 
+ 6.728000000000e-10 -6.202320930944e-02 
+ 6.828000000000e-10  1.526686803142e-01 
+ 6.928000000000e-10  3.609440280272e-01 
+ 7.028000000000e-10  5.329548030217e-01 
+ 7.128000000000e-10  6.401938938134e-01 
+ 7.228000000000e-10  6.625917482038e-01 
+ 7.328000000000e-10  5.908682152266e-01 
+ 7.428000000000e-10  4.406469457529e-01 
+ 7.528000000000e-10  2.493902766858e-01 
+ 7.628000000000e-10  4.288693618446e-02 
+ 7.728000000000e-10 -1.720955910448e-01 
+ 7.828000000000e-10 -3.785000668285e-01 
+ 7.928000000000e-10 -5.455631256377e-01 
+ 8.028000000000e-10 -6.460279628055e-01 
+ 8.128000000000e-10 -6.599666543450e-01 
+ 8.228000000000e-10 -5.800952421897e-01 
+ 8.328000000000e-10 -4.244724639235e-01 
+ 8.428000000000e-10 -2.312744332894e-01 
+ 8.528000000000e-10 -2.367347524184e-02 
+ 8.628000000000e-10  1.914518431597e-01 
+ 8.728000000000e-10  3.957278536471e-01 
+ 8.828000000000e-10  5.575922897374e-01 
+ 8.928000000000e-10  6.511097119424e-01 
+ 9.028000000000e-10  6.565314471724e-01 
+ 9.128000000000e-10  5.686744713173e-01 
+ 9.228000000000e-10  4.079868100625e-01 
+ 9.328000000000e-10  2.130521276703e-01 
+ 9.428000000000e-10  4.377478818861e-03 
+ 9.528000000000e-10 -2.107363569920e-01 
+ 9.628000000000e-10 -4.126164059868e-01 
+ 9.728000000000e-10 -5.690558179458e-01 
+ 9.828000000000e-10 -6.554409556493e-01 
+ 9.928000000000e-10 -6.522987163864e-01 
+ 1.000000000000e-09 -5.908571383549e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/conditions.yaml
new file mode 100644
index 00000000..6fc556db
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 2
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_02
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb.sch
new file mode 100644
index 00000000..5412b0ed
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb_3.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb_3.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb_3.data
new file mode 100644
index 00000000..01d3da70
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_core_tb_3.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.787312328274e-01 
+ 1.728000000000e-10  5.310718577798e-01 
+ 1.828000000000e-10  6.116694852515e-01 
+ 1.928000000000e-10  6.032465414624e-01 
+ 2.028000000000e-10  5.080931547620e-01 
+ 2.128000000000e-10  3.507201651223e-01 
+ 2.228000000000e-10  1.637728723673e-01 
+ 2.328000000000e-10 -3.591423441942e-02 
+ 2.428000000000e-10 -2.389715433325e-01 
+ 2.528000000000e-10 -4.246365337882e-01 
+ 2.628000000000e-10 -5.619274107991e-01 
+ 2.728000000000e-10 -6.217416227793e-01 
+ 2.828000000000e-10 -5.917990170747e-01 
+ 2.928000000000e-10 -4.793798636191e-01 
+ 3.028000000000e-10 -3.123775151550e-01 
+ 3.128000000000e-10 -1.216623790409e-01 
+ 3.228000000000e-10  7.991461458154e-02 
+ 3.328000000000e-10  2.813838782715e-01 
+ 3.428000000000e-10  4.595056728565e-01 
+ 3.528000000000e-10  5.820987735157e-01 
+ 3.628000000000e-10  6.230696206400e-01 
+ 3.728000000000e-10  5.740668117715e-01 
+ 3.828000000000e-10  4.470822134740e-01 
+ 3.928000000000e-10  2.728987140975e-01 
+ 4.028000000000e-10  7.924079481723e-02 
+ 4.128000000000e-10 -1.235982812782e-01 
+ 4.228000000000e-10 -3.224222279001e-01 
+ 4.328000000000e-10 -4.914711718710e-01 
+ 4.428000000000e-10 -5.982669959871e-01 
+ 4.528000000000e-10 -6.200561583520e-01 
+ 4.628000000000e-10 -5.526428354822e-01 
+ 4.728000000000e-10 -4.125771347856e-01 
+ 4.828000000000e-10 -2.326459140319e-01 
+ 4.928000000000e-10 -3.636345260799e-02 
+ 5.028000000000e-10  1.671292936419e-01 
+ 5.128000000000e-10  3.621740771165e-01 
+ 5.228000000000e-10  5.205351785740e-01 
+ 5.328000000000e-10  6.105069571881e-01 
+ 5.428000000000e-10  6.128628419209e-01 
+ 5.528000000000e-10  5.278288461165e-01 
+ 5.628000000000e-10  3.762585221796e-01 
+ 5.728000000000e-10  1.917227152577e-01 
+ 5.828000000000e-10 -6.904475690515e-03 
+ 5.928000000000e-10 -2.103220173831e-01 
+ 6.028000000000e-10 -4.003190871139e-01 
+ 6.128000000000e-10 -5.464444171748e-01 
+ 6.228000000000e-10 -6.187242472741e-01 
+ 6.328000000000e-10 -6.016161834184e-01 
+ 6.428000000000e-10 -4.999426915796e-01 
+ 6.528000000000e-10 -3.384986058457e-01 
+ 6.628000000000e-10 -1.501838709863e-01 
+ 6.728000000000e-10  5.043881560349e-02 
+ 6.828000000000e-10  2.529164351583e-01 
+ 6.928000000000e-10  4.364447819991e-01 
+ 7.028000000000e-10  5.688890883170e-01 
+ 7.128000000000e-10  6.227826879224e-01 
+ 7.228000000000e-10  5.864162100126e-01 
+ 7.328000000000e-10  4.692911957394e-01 
+ 7.428000000000e-10  2.996268945459e-01 
+ 7.528000000000e-10  1.080868898165e-01 
+ 7.628000000000e-10 -9.411819978895e-02 
+ 7.728000000000e-10 -2.946865001516e-01 
+ 7.828000000000e-10 -4.702089203683e-01 
+ 7.928000000000e-10 -5.876676138587e-01 
+ 8.028000000000e-10 -6.226257044083e-01 
+ 8.128000000000e-10 -5.674465695445e-01 
+ 8.228000000000e-10 -4.362183280713e-01 
+ 8.328000000000e-10 -2.598861301879e-01 
+ 8.428000000000e-10 -6.549233734919e-02 
+ 8.528000000000e-10  1.377780729322e-01 
+ 8.628000000000e-10  3.353665108903e-01 
+ 8.728000000000e-10  5.012715026474e-01 
+ 8.828000000000e-10  6.025971886412e-01 
+ 8.928000000000e-10  6.182514222450e-01 
+ 9.028000000000e-10  5.449093081378e-01 
+ 9.128000000000e-10  4.010874781253e-01 
+ 9.228000000000e-10  2.194242609006e-01 
+ 9.328000000000e-10  2.246875729083e-02 
+ 9.428000000000e-10 -1.812181861115e-01 
+ 9.528000000000e-10 -3.746515006742e-01 
+ 9.628000000000e-10 -5.293413040803e-01 
+ 9.728000000000e-10 -6.135587086509e-01 
+ 9.828000000000e-10 -6.097309440254e-01 
+ 9.928000000000e-10 -5.190796501788e-01 
+ 1.000000000000e-09 -4.110830567596e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/conditions.yaml
new file mode 100644
index 00000000..800e62da
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 3
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_03
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb.sch
new file mode 100644
index 00000000..a72a8f48
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb_4.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb_4.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb_4.data
new file mode 100644
index 00000000..9ae39401
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_core_tb_4.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.527739932023e-01 
+ 1.728000000000e-10  5.067296132741e-01 
+ 1.828000000000e-10  5.919306102367e-01 
+ 1.928000000000e-10  5.909637421707e-01 
+ 2.028000000000e-10  5.050843854174e-01 
+ 2.128000000000e-10  3.555305747672e-01 
+ 2.228000000000e-10  1.733318945705e-01 
+ 2.328000000000e-10 -2.246320083073e-02 
+ 2.428000000000e-10 -2.220625103466e-01 
+ 2.528000000000e-10 -4.056931517405e-01 
+ 2.628000000000e-10 -5.427471082900e-01 
+ 2.728000000000e-10 -6.042039445662e-01 
+ 2.828000000000e-10 -5.786741938972e-01 
+ 2.928000000000e-10 -4.726336370412e-01 
+ 3.028000000000e-10 -3.111272852435e-01 
+ 3.128000000000e-10 -1.240925914530e-01 
+ 3.228000000000e-10  7.395024567436e-02 
+ 3.328000000000e-10  2.718578294311e-01 
+ 3.428000000000e-10  4.467934011904e-01 
+ 3.528000000000e-10  5.665709106631e-01 
+ 3.628000000000e-10  6.061049714339e-01 
+ 3.728000000000e-10  5.585778357772e-01 
+ 3.828000000000e-10  4.353637877442e-01 
+ 3.928000000000e-10  2.649104770346e-01 
+ 4.028000000000e-10  7.422447535881e-02 
+ 4.128000000000e-10 -1.252066094696e-01 
+ 4.228000000000e-10 -3.199114008579e-01 
+ 4.328000000000e-10 -4.839123173062e-01 
+ 4.428000000000e-10 -5.848683081174e-01 
+ 4.528000000000e-10 -6.020960278290e-01 
+ 4.628000000000e-10 -5.334075032087e-01 
+ 4.728000000000e-10 -3.949565487431e-01 
+ 4.828000000000e-10 -2.175202194849e-01 
+ 4.928000000000e-10 -2.374137033440e-02 
+ 5.028000000000e-10  1.762067660298e-01 
+ 5.128000000000e-10  3.660614981710e-01 
+ 5.228000000000e-10  5.168353314960e-01 
+ 5.328000000000e-10  5.976520790730e-01 
+ 5.428000000000e-10  5.923721290712e-01 
+ 5.528000000000e-10  5.036135913931e-01 
+ 5.628000000000e-10  3.520147819229e-01 
+ 5.728000000000e-10  1.691411016634e-01 
+ 5.828000000000e-10 -2.720287389901e-02 
+ 5.928000000000e-10 -2.265902016718e-01 
+ 6.028000000000e-10 -4.097016868418e-01 
+ 6.128000000000e-10 -5.451012400507e-01 
+ 6.228000000000e-10 -6.047637320677e-01 
+ 6.328000000000e-10 -5.771127174561e-01 
+ 6.428000000000e-10 -4.696619234859e-01 
+ 6.528000000000e-10 -3.071376992250e-01 
+ 6.628000000000e-10 -1.199124463650e-01 
+ 6.728000000000e-10  7.843292596863e-02 
+ 6.828000000000e-10  2.759743419607e-01 
+ 6.928000000000e-10  4.502085789734e-01 
+ 7.028000000000e-10  5.682846910592e-01 
+ 7.128000000000e-10  6.060547534659e-01 
+ 7.228000000000e-10  5.565297283293e-01 
+ 7.328000000000e-10  4.320660125387e-01 
+ 7.428000000000e-10  2.608014341229e-01 
+ 7.528000000000e-10  6.996576024471e-02 
+ 7.628000000000e-10 -1.296831986240e-01 
+ 7.728000000000e-10 -3.239050411005e-01 
+ 7.828000000000e-10 -4.869831605413e-01 
+ 7.928000000000e-10 -5.861285383102e-01 
+ 8.028000000000e-10 -6.015423398526e-01 
+ 8.128000000000e-10 -5.309529844792e-01 
+ 8.228000000000e-10 -3.914078404525e-01 
+ 8.328000000000e-10 -2.133268983323e-01 
+ 8.428000000000e-10 -1.942817053603e-02 
+ 8.528000000000e-10  1.806385493964e-01 
+ 8.628000000000e-10  3.698710924499e-01 
+ 8.728000000000e-10  5.195165545946e-01 
+ 8.828000000000e-10  5.984340950058e-01 
+ 8.928000000000e-10  5.913281701523e-01 
+ 9.028000000000e-10  5.007881491315e-01 
+ 9.128000000000e-10  3.482705219974e-01 
+ 9.228000000000e-10  1.648762275078e-01 
+ 9.328000000000e-10 -3.155556636608e-02 
+ 9.428000000000e-10 -2.309443516678e-01 
+ 9.528000000000e-10 -4.132744730914e-01 
+ 9.628000000000e-10 -5.473543968075e-01 
+ 9.728000000000e-10 -6.050589011645e-01 
+ 9.828000000000e-10 -5.755953492732e-01 
+ 9.928000000000e-10 -4.665084057301e-01 
+ 1.000000000000e-09 -3.516472164760e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/conditions.yaml
new file mode 100644
index 00000000..193bbe4d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 4
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_04
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb.sch
new file mode 100644
index 00000000..336721e9
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb_5.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb_5.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb_5.data
new file mode 100644
index 00000000..10687699
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_core_tb_5.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.899805551492e-01 
+ 1.728000000000e-10  5.446618577616e-01 
+ 1.828000000000e-10  6.266096652190e-01 
+ 1.928000000000e-10  6.172504471116e-01 
+ 2.028000000000e-10  5.190610617635e-01 
+ 2.128000000000e-10  3.593956743245e-01 
+ 2.228000000000e-10  1.724426085975e-01 
+ 2.328000000000e-10 -2.745064663747e-02 
+ 2.428000000000e-10 -2.329616471951e-01 
+ 2.528000000000e-10 -4.234893258118e-01 
+ 2.628000000000e-10 -5.680967965453e-01 
+ 2.728000000000e-10 -6.358508809756e-01 
+ 2.828000000000e-10 -6.116847704035e-01 
+ 2.928000000000e-10 -5.017753699043e-01 
+ 3.028000000000e-10 -3.357622391395e-01 
+ 3.128000000000e-10 -1.463951301493e-01 
+ 3.228000000000e-10  5.501228565901e-02 
+ 3.328000000000e-10  2.599601873588e-01 
+ 3.428000000000e-10  4.463204041669e-01 
+ 3.528000000000e-10  5.821572067154e-01 
+ 3.628000000000e-10  6.381725221864e-01 
+ 3.728000000000e-10  6.017055446787e-01 
+ 3.828000000000e-10  4.823097743360e-01 
+ 3.928000000000e-10  3.116413511196e-01 
+ 4.028000000000e-10  1.204513464120e-01 
+ 4.128000000000e-10 -8.216746608457e-02 
+ 4.228000000000e-10 -2.861629008922e-01 
+ 4.328000000000e-10 -4.678572590668e-01 
+ 4.428000000000e-10 -5.945512494607e-01 
+ 4.528000000000e-10 -6.386993079281e-01 
+ 4.628000000000e-10 -5.902002735031e-01 
+ 4.728000000000e-10 -4.619269519683e-01 
+ 4.828000000000e-10 -2.872325672856e-01 
+ 4.928000000000e-10 -9.428805990276e-02 
+ 5.028000000000e-10  1.093767475837e-01 
+ 5.128000000000e-10  3.120263965424e-01 
+ 5.228000000000e-10  4.884339240257e-01 
+ 5.328000000000e-10  6.055096291837e-01 
+ 5.428000000000e-10  6.375795029609e-01 
+ 5.528000000000e-10  5.772859873177e-01 
+ 5.628000000000e-10  4.407300348513e-01 
+ 5.728000000000e-10  2.625705353928e-01 
+ 5.828000000000e-10  6.792556046796e-02 
+ 5.928000000000e-10 -1.365768524997e-01 
+ 6.028000000000e-10 -3.374542253471e-01 
+ 6.128000000000e-10 -5.079466715988e-01 
+ 6.228000000000e-10 -6.149592289389e-01 
+ 6.328000000000e-10 -6.347974900667e-01 
+ 6.428000000000e-10 -5.630051271319e-01 
+ 6.528000000000e-10 -4.188061832544e-01 
+ 6.628000000000e-10 -2.376603787830e-01 
+ 6.728000000000e-10 -4.134818844143e-02 
+ 6.828000000000e-10  1.637586206522e-01 
+ 6.928000000000e-10  3.624175492031e-01 
+ 7.028000000000e-10  5.263633140706e-01 
+ 7.128000000000e-10  6.228964156442e-01 
+ 7.228000000000e-10  6.303896300717e-01 
+ 7.328000000000e-10  5.474437216466e-01 
+ 7.428000000000e-10  3.962386662731e-01 
+ 7.528000000000e-10  2.125149883232e-01 
+ 7.628000000000e-10  1.461648003679e-02 
+ 7.728000000000e-10 -1.908138897843e-01 
+ 7.828000000000e-10 -3.867729399792e-01 
+ 7.928000000000e-10 -5.435669596211e-01 
+ 8.028000000000e-10 -6.292531394829e-01 
+ 8.128000000000e-10 -6.243668066490e-01 
+ 8.228000000000e-10 -5.306765426618e-01 
+ 8.328000000000e-10 -3.731361043849e-01 
+ 8.428000000000e-10 -1.871403151425e-01 
+ 8.528000000000e-10  1.226616272226e-02 
+ 8.628000000000e-10  2.177097156913e-01 
+ 8.728000000000e-10  4.104603685680e-01 
+ 8.828000000000e-10  5.595160805387e-01 
+ 8.928000000000e-10  6.340210539113e-01 
+ 9.028000000000e-10  6.167734167151e-01 
+ 9.128000000000e-10  5.127945975126e-01 
+ 9.228000000000e-10  3.495872919270e-01 
+ 9.328000000000e-10  1.615373139215e-01 
+ 9.428000000000e-10 -3.927853585867e-02 
+ 9.528000000000e-10 -2.443951865104e-01 
+ 9.628000000000e-10 -4.333865230537e-01 
+ 9.728000000000e-10 -5.741458706841e-01 
+ 9.828000000000e-10 -6.371615177319e-01 
+ 9.928000000000e-10 -6.076273838542e-01 
+ 1.000000000000e-09 -5.316204064609e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/conditions.yaml
new file mode 100644
index 00000000..5d00c883
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 5
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_05
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb.sch
new file mode 100644
index 00000000..a4275f71
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb_6.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb_6.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb_6.data
new file mode 100644
index 00000000..d41c6130
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_core_tb_6.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.272923197830e-01 
+ 1.728000000000e-10  4.819566763926e-01 
+ 1.828000000000e-10  5.726826350468e-01 
+ 1.928000000000e-10  5.788408046581e-01 
+ 2.028000000000e-10  5.015057929381e-01 
+ 2.128000000000e-10  3.614946791662e-01 
+ 2.228000000000e-10  1.878018883160e-01 
+ 2.328000000000e-10 -5.152928654438e-04 
+ 2.428000000000e-10 -1.939629764799e-01 
+ 2.528000000000e-10 -3.754137148459e-01 
+ 2.628000000000e-10 -5.169596677951e-01 
+ 2.728000000000e-10 -5.868852209445e-01 
+ 2.828000000000e-10 -5.708977912689e-01 
+ 2.928000000000e-10 -4.753083054539e-01 
+ 3.028000000000e-10 -3.241657178363e-01 
+ 3.128000000000e-10 -1.455948464079e-01 
+ 3.228000000000e-10  4.499341463190e-02 
+ 3.328000000000e-10  2.376719771956e-01 
+ 3.428000000000e-10  4.128180830206e-01 
+ 3.528000000000e-10  5.403996474700e-01 
+ 3.628000000000e-10  5.911000287822e-01 
+ 3.728000000000e-10  5.556682151963e-01 
+ 3.828000000000e-10  4.448214476974e-01 
+ 3.928000000000e-10  2.852566745587e-01 
+ 4.028000000000e-10  1.031028047915e-01 
+ 4.128000000000e-10 -8.903168621584e-02 
+ 4.228000000000e-10 -2.798685004857e-01 
+ 4.328000000000e-10 -4.471531492488e-01 
+ 4.428000000000e-10 -5.593245084023e-01 
+ 4.528000000000e-10 -5.905190912946e-01 
+ 4.628000000000e-10 -5.363759912566e-01 
+ 4.728000000000e-10 -4.117695851479e-01 
+ 4.828000000000e-10 -2.452792947403e-01 
+ 4.928000000000e-10 -6.009673014036e-02 
+ 5.028000000000e-10  1.330294549602e-01 
+ 5.128000000000e-10  3.209066489495e-01 
+ 5.228000000000e-10  4.786196617327e-01 
+ 5.328000000000e-10  5.739939994269e-01 
+ 5.428000000000e-10  5.854521386947e-01 
+ 5.528000000000e-10  5.133999770894e-01 
+ 5.628000000000e-10  3.765766215401e-01 
+ 5.728000000000e-10  2.044210251017e-01 
+ 5.828000000000e-10  1.663948978675e-02 
+ 5.928000000000e-10 -1.768225768789e-01 
+ 6.028000000000e-10 -3.604735185863e-01 
+ 6.128000000000e-10 -5.068517002383e-01 
+ 6.228000000000e-10 -5.842923519665e-01 
+ 6.328000000000e-10 -5.760243982484e-01 
+ 6.428000000000e-10 -4.870560863823e-01 
+ 6.528000000000e-10 -3.396140103858e-01 
+ 6.628000000000e-10 -1.628160907611e-01 
+ 6.728000000000e-10  2.713518106981e-02 
+ 6.828000000000e-10  2.201313700592e-01 
+ 6.928000000000e-10  3.981398672845e-01 
+ 7.028000000000e-10  5.314129585100e-01 
+ 7.128000000000e-10  5.900629559558e-01 
+ 7.228000000000e-10  5.623346075405e-01 
+ 7.328000000000e-10  4.576489899043e-01 
+ 7.428000000000e-10  3.012060707577e-01 
+ 7.528000000000e-10  1.205607029165e-01 
+ 7.628000000000e-10 -7.111902777530e-02 
+ 7.728000000000e-10 -2.627143394217e-01 
+ 7.828000000000e-10 -4.335192481659e-01 
+ 7.928000000000e-10 -5.520469297325e-01 
+ 8.028000000000e-10 -5.913465255736e-01 
+ 8.128000000000e-10 -5.446422750292e-01 
+ 8.228000000000e-10 -4.255777736303e-01 
+ 8.328000000000e-10 -2.616434466132e-01 
+ 8.428000000000e-10 -7.774328533570e-02 
+ 8.528000000000e-10  1.151601059047e-01 
+ 8.628000000000e-10  3.042846665874e-01 
+ 8.728000000000e-10  4.662132820490e-01 
+ 8.828000000000e-10  5.684913559476e-01 
+ 8.928000000000e-10  5.881064262615e-01 
+ 9.028000000000e-10  5.231504152161e-01 
+ 9.128000000000e-10  3.912170597589e-01 
+ 9.228000000000e-10  2.211379352235e-01 
+ 9.328000000000e-10  3.445328650701e-02 
+ 9.428000000000e-10 -1.590552113490e-01 
+ 9.528000000000e-10 -3.445018956927e-01 
+ 9.628000000000e-10 -4.958047876980e-01 
+ 9.728000000000e-10 -5.805916053244e-01 
+ 9.828000000000e-10 -5.804363168583e-01 
+ 9.928000000000e-10 -4.981483730617e-01 
+ 1.000000000000e-09 -3.984864554057e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/conditions.yaml
new file mode 100644
index 00000000..e9928240
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 6
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_06
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb.sch
new file mode 100644
index 00000000..b8634c09
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb_7.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb_7.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb_7.data
new file mode 100644
index 00000000..a10c27d2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_core_tb_7.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.046755204913e-01 
+ 1.728000000000e-10  4.588771864746e-01 
+ 1.828000000000e-10  5.518179717254e-01 
+ 1.928000000000e-10  5.630613181018e-01 
+ 2.028000000000e-10  4.930058654618e-01 
+ 2.128000000000e-10  3.600434340665e-01 
+ 2.228000000000e-10  1.913332065647e-01 
+ 2.328000000000e-10  7.030379563374e-03 
+ 2.428000000000e-10 -1.825845992720e-01 
+ 2.528000000000e-10 -3.607212321510e-01 
+ 2.628000000000e-10 -4.995152077763e-01 
+ 2.728000000000e-10 -5.681601776296e-01 
+ 2.828000000000e-10 -5.536475265944e-01 
+ 2.928000000000e-10 -4.620883849781e-01 
+ 3.028000000000e-10 -3.154948373540e-01 
+ 3.128000000000e-10 -1.405895328965e-01 
+ 3.228000000000e-10  4.643731481932e-02 
+ 3.328000000000e-10  2.350973253463e-01 
+ 3.428000000000e-10  4.054203097179e-01 
+ 3.528000000000e-10  5.270988155628e-01 
+ 3.628000000000e-10  5.727125157929e-01 
+ 3.728000000000e-10  5.352123535322e-01 
+ 3.828000000000e-10  4.254605305301e-01 
+ 3.928000000000e-10  2.685036737698e-01 
+ 4.028000000000e-10  8.911586636822e-02 
+ 4.128000000000e-10 -9.963398240146e-02 
+ 4.228000000000e-10 -2.857170287196e-01 
+ 4.328000000000e-10 -4.457726616042e-01 
+ 4.428000000000e-10 -5.482103366819e-01 
+ 4.528000000000e-10 -5.704216942123e-01 
+ 4.628000000000e-10 -5.109460128406e-01 
+ 4.728000000000e-10 -3.850868130838e-01 
+ 4.828000000000e-10 -2.198835933739e-01 
+ 4.928000000000e-10 -3.689980676769e-02 
+ 5.028000000000e-10  1.526833767467e-01 
+ 5.128000000000e-10  3.343900010501e-01 
+ 5.228000000000e-10  4.815572314350e-01 
+ 5.328000000000e-10  5.629454287650e-01 
+ 5.428000000000e-10  5.616466908200e-01 
+ 5.528000000000e-10  4.814338387350e-01 
+ 5.628000000000e-10  3.416630734205e-01 
+ 5.728000000000e-10  1.699699975451e-01 
+ 5.828000000000e-10 -1.585775886924e-02 
+ 5.928000000000e-10 -2.051574982768e-01 
+ 6.028000000000e-10 -3.803955463572e-01 
+ 6.128000000000e-10 -5.120569276360e-01 
+ 6.228000000000e-10 -5.710959641361e-01 
+ 6.328000000000e-10 -5.465908780276e-01 
+ 6.428000000000e-10 -4.471998258417e-01 
+ 6.528000000000e-10 -2.958148073664e-01 
+ 6.628000000000e-10 -1.190050287464e-01 
+ 6.728000000000e-10  6.896892282433e-02 
+ 6.828000000000e-10  2.566225290979e-01 
+ 6.928000000000e-10  4.230361487305e-01 
+ 7.028000000000e-10  5.367245944621e-01 
+ 7.128000000000e-10  5.726009405551e-01 
+ 7.228000000000e-10  5.255773298606e-01 
+ 7.328000000000e-10  4.088680395342e-01 
+ 7.428000000000e-10  2.480819861851e-01 
+ 7.528000000000e-10  6.719204479067e-02 
+ 7.628000000000e-10 -1.221352201548e-01 
+ 7.728000000000e-10 -3.064998235705e-01 
+ 7.828000000000e-10 -4.615352773482e-01 
+ 7.928000000000e-10 -5.551743835496e-01 
+ 8.028000000000e-10 -5.675398121722e-01 
+ 8.128000000000e-10 -4.990356074229e-01 
+ 8.228000000000e-10 -3.671187730269e-01 
+ 8.328000000000e-10 -1.988855738478e-01 
+ 8.428000000000e-10 -1.471402250170e-02 
+ 8.528000000000e-10  1.749906067695e-01 
+ 8.628000000000e-10  3.541421288266e-01 
+ 8.728000000000e-10  4.951614050915e-01 
+ 8.828000000000e-10  5.671473843583e-01 
+ 8.928000000000e-10  5.560712514825e-01 
+ 9.028000000000e-10  4.674591983192e-01 
+ 9.128000000000e-10  3.225884832919e-01 
+ 9.228000000000e-10  1.485020348748e-01 
+ 9.328000000000e-10 -3.823610122102e-02 
+ 9.428000000000e-10 -2.271067171072e-01 
+ 9.528000000000e-10 -3.988323544176e-01 
+ 9.628000000000e-10 -5.232527594701e-01 
+ 9.728000000000e-10 -5.724941479336e-01 
+ 9.828000000000e-10 -5.384465917756e-01 
+ 9.928000000000e-10 -4.314195039535e-01 
+ 1.000000000000e-09 -3.218668116164e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/conditions.yaml
new file mode 100644
index 00000000..bcee4a2e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 7
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_07
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb.sch
new file mode 100644
index 00000000..056de1a6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb_8.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb_8.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb_8.data
new file mode 100644
index 00000000..9bf52d4b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_core_tb_8.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  3.334512303141e-01 
+ 1.728000000000e-10  4.920310241072e-01 
+ 1.828000000000e-10  5.871516315218e-01 
+ 1.928000000000e-10  5.960766354992e-01 
+ 2.028000000000e-10  5.190911466521e-01 
+ 2.128000000000e-10  3.785207326900e-01 
+ 2.228000000000e-10  2.049302653238e-01 
+ 2.328000000000e-10  1.651767251554e-02 
+ 2.428000000000e-10 -1.790271764811e-01 
+ 2.528000000000e-10 -3.657879864898e-01 
+ 2.628000000000e-10 -5.171831909383e-01 
+ 2.728000000000e-10 -5.997088663149e-01 
+ 2.828000000000e-10 -5.948111801226e-01 
+ 2.928000000000e-10 -5.063654012101e-01 
+ 3.028000000000e-10 -3.587863037418e-01 
+ 3.128000000000e-10 -1.821379391557e-01 
+ 3.228000000000e-10  7.888972519530e-03 
+ 3.328000000000e-10  2.035088728667e-01 
+ 3.428000000000e-10  3.875409021465e-01 
+ 3.528000000000e-10  5.320644301491e-01 
+ 3.628000000000e-10  6.042388280374e-01 
+ 3.728000000000e-10  5.883403890472e-01 
+ 3.828000000000e-10  4.910042429366e-01 
+ 3.928000000000e-10  3.383713820269e-01 
+ 4.028000000000e-10  1.596304490075e-01 
+ 4.128000000000e-10 -3.157975881199e-02 
+ 4.228000000000e-10 -2.269158813736e-01 
+ 4.328000000000e-10 -4.078630979115e-01 
+ 4.428000000000e-10 -5.452238343377e-01 
+ 4.528000000000e-10 -6.070914209056e-01 
+ 4.628000000000e-10 -5.804825164118e-01 
+ 4.728000000000e-10 -4.747613668514e-01 
+ 4.828000000000e-10 -3.176002092310e-01 
+ 4.928000000000e-10 -1.369439978288e-01 
+ 5.028000000000e-10  5.534658721980e-02 
+ 5.128000000000e-10  2.501430489142e-01 
+ 5.228000000000e-10  4.275696337474e-01 
+ 5.328000000000e-10  5.572530695454e-01 
+ 5.428000000000e-10  6.086048604787e-01 
+ 5.528000000000e-10  5.714423014991e-01 
+ 5.628000000000e-10  4.577558387660e-01 
+ 5.728000000000e-10  2.965226810522e-01 
+ 5.828000000000e-10  1.140863397721e-01 
+ 5.928000000000e-10 -7.916165526171e-02 
+ 6.028000000000e-10 -2.731282141304e-01 
+ 6.128000000000e-10 -4.465714488852e-01 
+ 6.228000000000e-10 -5.680918089739e-01 
+ 6.328000000000e-10 -6.087809432803e-01 
+ 6.428000000000e-10 -5.612546972849e-01 
+ 6.528000000000e-10 -4.400500904524e-01 
+ 6.628000000000e-10 -2.751690190519e-01 
+ 6.728000000000e-10 -9.106761382953e-02 
+ 6.828000000000e-10  1.029968797521e-01 
+ 6.928000000000e-10  2.958257130252e-01 
+ 7.028000000000e-10  4.648013192379e-01 
+ 7.128000000000e-10  5.777063572260e-01 
+ 7.228000000000e-10  6.076218987809e-01 
+ 7.328000000000e-10  5.499646386996e-01 
+ 7.428000000000e-10  4.217057221764e-01 
+ 7.528000000000e-10  2.535632375360e-01 
+ 7.628000000000e-10  6.789614061290e-02 
+ 7.728000000000e-10 -1.268193581673e-01 
+ 7.828000000000e-10 -3.181808612885e-01 
+ 7.928000000000e-10 -4.821903021659e-01 
+ 8.028000000000e-10 -5.860591830893e-01 
+ 8.128000000000e-10 -6.051306912086e-01 
+ 8.228000000000e-10 -5.376046096264e-01 
+ 8.328000000000e-10 -4.027756137924e-01 
+ 8.428000000000e-10 -2.317126300703e-01 
+ 8.528000000000e-10 -4.455549072905e-02 
+ 8.628000000000e-10  1.506398273088e-01 
+ 8.728000000000e-10  3.401881982667e-01 
+ 8.828000000000e-10  4.987168422738e-01 
+ 8.928000000000e-10  5.931649578198e-01 
+ 9.028000000000e-10  6.013494541833e-01 
+ 9.128000000000e-10  5.242449683991e-01 
+ 9.228000000000e-10  3.833231535447e-01 
+ 9.328000000000e-10  2.096470589865e-01 
+ 9.428000000000e-10  2.110110280871e-02 
+ 9.528000000000e-10 -1.743676839347e-01 
+ 9.628000000000e-10 -3.617308880367e-01 
+ 9.728000000000e-10 -5.142636715347e-01 
+ 9.828000000000e-10 -5.989629387124e-01 
+ 9.928000000000e-10 -5.962786821895e-01 
+ 1.000000000000e-09 -5.406592435476e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/conditions.yaml
new file mode 100644
index 00000000..9b83fa72
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 8
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_08
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb.sch
new file mode 100644
index 00000000..24da899c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb_9.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb_9.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb_9.data
new file mode 100644
index 00000000..2993c56d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_core_tb_9.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.668053088994e-01 
+ 1.728000000000e-10  5.857254764211e-01 
+ 1.828000000000e-10  5.012885034242e-01 
+ 1.928000000000e-10  3.496119161339e-01 
+ 2.028000000000e-10  1.832231223385e-01 
+ 2.128000000000e-10  1.814016746348e-02 
+ 2.228000000000e-10 -1.582488922184e-01 
+ 2.328000000000e-10 -3.434810675640e-01 
+ 2.428000000000e-10 -5.067125803648e-01 
+ 2.528000000000e-10 -5.886170858536e-01 
+ 2.628000000000e-10 -5.623087079277e-01 
+ 2.728000000000e-10 -4.437897754944e-01 
+ 2.828000000000e-10 -2.803473323284e-01 
+ 2.928000000000e-10 -1.154437766492e-01 
+ 3.028000000000e-10  5.298892056425e-02 
+ 3.128000000000e-10  2.348763033985e-01 
+ 3.228000000000e-10  4.167289199396e-01 
+ 3.328000000000e-10  5.534898949576e-01 
+ 3.428000000000e-10  5.908111329708e-01 
+ 3.528000000000e-10  5.222863413108e-01 
+ 3.628000000000e-10  3.781315285794e-01 
+ 3.728000000000e-10  2.115997289284e-01 
+ 3.828000000000e-10  4.701053084038e-02 
+ 3.928000000000e-10 -1.267436670640e-01 
+ 4.028000000000e-10 -3.118715354619e-01 
+ 4.128000000000e-10 -4.825510114000e-01 
+ 4.228000000000e-10 -5.821722089926e-01 
+ 4.328000000000e-10 -5.742542254893e-01 
+ 4.428000000000e-10 -4.690576377049e-01 
+ 4.528000000000e-10 -3.091055349154e-01 
+ 4.628000000000e-10 -1.436815907828e-01 
+ 4.728000000000e-10  2.320195326925e-02 
+ 4.828000000000e-10  2.028356601470e-01 
+ 4.928000000000e-10  3.870062310368e-01 
+ 5.028000000000e-10  5.360981275586e-01 
+ 5.128000000000e-10  5.923134931039e-01 
+ 5.228000000000e-10  5.407044044462e-01 
+ 5.328000000000e-10  4.062163744597e-01 
+ 5.428000000000e-10  2.400594094322e-01 
+ 5.528000000000e-10  7.574547495214e-02 
+ 5.628000000000e-10 -9.573670339165e-02 
+ 5.728000000000e-10 -2.797908939581e-01 
+ 5.828000000000e-10 -4.563610748463e-01 
+ 5.928000000000e-10 -5.723989589010e-01 
+ 6.028000000000e-10 -5.833681745524e-01 
+ 6.128000000000e-10 -4.925316152611e-01 
+ 6.228000000000e-10 -3.380117706452e-01 
+ 6.328000000000e-10 -1.718187486666e-01 
+ 6.428000000000e-10 -6.311096017310e-03 
+ 6.528000000000e-10  1.710417477038e-01 
+ 6.628000000000e-10  3.561610603242e-01 
+ 6.728000000000e-10  5.157419068689e-01 
+ 6.828000000000e-10  5.903632413079e-01 
+ 6.928000000000e-10  5.566690398802e-01 
+ 7.028000000000e-10  4.332577725691e-01 
+ 7.128000000000e-10  2.687661939284e-01 
+ 7.228000000000e-10  1.040962406345e-01 
+ 7.328000000000e-10 -6.514380203775e-02 
+ 7.428000000000e-10 -2.477516573600e-01 
+ 7.528000000000e-10 -4.283810997893e-01 
+ 7.628000000000e-10 -5.595560501887e-01 
+ 7.728000000000e-10 -5.893136746958e-01 
+ 7.828000000000e-10 -5.141806750048e-01 
+ 7.928000000000e-10 -3.666907626534e-01 
+ 8.028000000000e-10 -2.001605247775e-01 
+ 8.128000000000e-10 -3.539844999637e-02 
+ 8.228000000000e-10  1.393801501742e-01 
+ 8.328000000000e-10  3.246733270368e-01 
+ 8.428000000000e-10  4.925514879874e-01 
+ 8.528000000000e-10  5.851746152462e-01 
+ 8.628000000000e-10  5.697858900390e-01 
+ 8.728000000000e-10  4.590951362034e-01 
+ 8.828000000000e-10  2.975143674948e-01 
+ 8.928000000000e-10  1.323427539482e-01 
+ 9.028000000000e-10 -3.514510890180e-02 
+ 9.128000000000e-10 -2.156968702842e-01 
+ 9.228000000000e-10 -3.991100939526e-01 
+ 9.328000000000e-10 -5.434600882914e-01 
+ 9.428000000000e-10 -5.921215711709e-01 
+ 9.528000000000e-10 -5.335762414989e-01 
+ 9.628000000000e-10 -3.950234022959e-01 
+ 9.728000000000e-10 -2.285812895409e-01 
+ 9.828000000000e-10 -6.423644498198e-02 
+ 9.928000000000e-10  1.081622418334e-01 
+ 1.000000000000e-09  2.412230503845e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/conditions.yaml
new file mode 100644
index 00000000..3f03bbe2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 9
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_09
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb.sch
new file mode 100644
index 00000000..498e92f5
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb_10.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb_10.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb_10.data
new file mode 100644
index 00000000..3f80dd94
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_core_tb_10.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.428454097944e-01 
+ 1.728000000000e-10  5.887232665160e-01 
+ 1.828000000000e-10  5.330123444355e-01 
+ 1.928000000000e-10  4.002306682823e-01 
+ 2.028000000000e-10  2.376864868930e-01 
+ 2.128000000000e-10  7.678280982833e-02 
+ 2.228000000000e-10 -9.183070296933e-02 
+ 2.328000000000e-10 -2.735408409540e-01 
+ 2.428000000000e-10 -4.488104547239e-01 
+ 2.528000000000e-10 -5.660499400086e-01 
+ 2.628000000000e-10 -5.832044710923e-01 
+ 2.728000000000e-10 -5.025294495918e-01 
+ 2.828000000000e-10 -3.561389451591e-01 
+ 2.928000000000e-10 -1.931509973895e-01 
+ 3.028000000000e-10 -3.161724055927e-02 
+ 3.128000000000e-10  1.410162521305e-01 
+ 3.228000000000e-10  3.241425761048e-01 
+ 3.328000000000e-10  4.896722689474e-01 
+ 3.428000000000e-10  5.810994290094e-01 
+ 3.528000000000e-10  5.697787336600e-01 
+ 3.628000000000e-10  4.667491870485e-01 
+ 3.728000000000e-10  3.110523622229e-01 
+ 3.828000000000e-10  1.489204686804e-01 
+ 3.928000000000e-10 -1.441683887549e-02 
+ 4.028000000000e-10 -1.911114176137e-01 
+ 4.128000000000e-10 -3.736007816207e-01 
+ 4.228000000000e-10 -5.247269258094e-01 
+ 4.328000000000e-10 -5.883619802608e-01 
+ 4.428000000000e-10 -5.493709568696e-01 
+ 4.528000000000e-10 -4.268560645732e-01 
+ 4.628000000000e-10 -2.659216134563e-01 
+ 4.728000000000e-10 -1.046762237276e-01 
+ 4.828000000000e-10  6.154083598056e-02 
+ 4.928000000000e-10  2.417370283704e-01 
+ 5.028000000000e-10  4.207944424121e-01 
+ 5.128000000000e-10  5.525507732105e-01 
+ 5.228000000000e-10  5.875753342204e-01 
+ 5.328000000000e-10  5.224235076500e-01 
+ 5.428000000000e-10  3.839329178331e-01 
+ 5.528000000000e-10  2.211099477749e-01 
+ 5.628000000000e-10  5.996738384120e-02 
+ 5.728000000000e-10 -1.099674418154e-01 
+ 5.828000000000e-10 -2.925437637672e-01 
+ 5.928000000000e-10 -4.645883613969e-01 
+ 6.028000000000e-10 -5.726945090474e-01 
+ 6.128000000000e-10 -5.790563278825e-01 
+ 6.228000000000e-10 -4.898564008421e-01 
+ 6.328000000000e-10 -3.393681751694e-01 
+ 6.428000000000e-10 -1.767412253591e-01 
+ 6.528000000000e-10 -1.454956388405e-02 
+ 6.628000000000e-10  1.594975892711e-01 
+ 6.728000000000e-10  3.427835897317e-01 
+ 6.828000000000e-10  5.034181189969e-01 
+ 6.928000000000e-10  5.847881744116e-01 
+ 7.028000000000e-10  5.629416678024e-01 
+ 7.128000000000e-10  4.524088161704e-01 
+ 7.228000000000e-10  2.942348359352e-01 
+ 7.328000000000e-10  1.325830680191e-01 
+ 7.428000000000e-10 -3.185512433972e-02 
+ 7.528000000000e-10 -2.098392063323e-01 
+ 7.628000000000e-10 -3.915363466654e-01 
+ 7.728000000000e-10 -5.359377717046e-01 
+ 7.828000000000e-10 -5.890964735012e-01 
+ 7.928000000000e-10 -5.400822293487e-01 
+ 8.028000000000e-10 -4.113016871798e-01 
+ 8.128000000000e-10 -2.492332141259e-01 
+ 8.228000000000e-10 -8.824437749447e-02 
+ 8.328000000000e-10  7.936811900351e-02 
+ 8.428000000000e-10  2.605063461685e-01 
+ 8.528000000000e-10  4.375102433552e-01 
+ 8.628000000000e-10  5.608346246038e-01 
+ 8.728000000000e-10  5.853101833106e-01 
+ 8.828000000000e-10  5.109008400826e-01 
+ 8.928000000000e-10  3.675780917482e-01 
+ 9.028000000000e-10  2.045751110844e-01 
+ 9.128000000000e-10  4.327185431609e-02 
+ 9.228000000000e-10 -1.282588076844e-01 
+ 9.328000000000e-10 -3.112363383013e-01 
+ 9.428000000000e-10 -4.796448869807e-01 
+ 9.528000000000e-10 -5.779714766981e-01 
+ 9.628000000000e-10 -5.738664100326e-01 
+ 9.728000000000e-10 -4.763674754779e-01 
+ 9.828000000000e-10 -3.226217811241e-01 
+ 9.928000000000e-10 -1.602653782787e-01 
+ 1.000000000000e-09 -4.451885084543e-02 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/conditions.yaml
new file mode 100644
index 00000000..62ddc3f2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 10
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_10
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb.sch
new file mode 100644
index 00000000..d82d43e6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb_11.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb_11.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb_11.data
new file mode 100644
index 00000000..9458f6ce
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_core_tb_11.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.827936810554e-01 
+ 1.728000000000e-10  5.810792076977e-01 
+ 1.828000000000e-10  4.754509601432e-01 
+ 1.928000000000e-10  3.123193265552e-01 
+ 2.028000000000e-10  1.445094956986e-01 
+ 2.128000000000e-10 -2.384329014267e-02 
+ 2.228000000000e-10 -2.052873687362e-01 
+ 2.328000000000e-10 -3.914038413672e-01 
+ 2.428000000000e-10 -5.430039178242e-01 
+ 2.528000000000e-10 -5.974115721655e-01 
+ 2.628000000000e-10 -5.389960693485e-01 
+ 2.728000000000e-10 -3.964329868203e-01 
+ 2.828000000000e-10 -2.268489588437e-01 
+ 2.928000000000e-10 -6.061675885961e-02 
+ 3.028000000000e-10  1.135421560512e-01 
+ 3.128000000000e-10  3.001127750219e-01 
+ 3.228000000000e-10  4.761699337604e-01 
+ 3.328000000000e-10  5.845551088541e-01 
+ 3.428000000000e-10  5.810137437748e-01 
+ 3.528000000000e-10  4.742887126822e-01 
+ 3.628000000000e-10  3.105573370732e-01 
+ 3.728000000000e-10  1.429035289472e-01 
+ 3.828000000000e-10 -2.566941675042e-02 
+ 3.928000000000e-10 -2.070892792811e-01 
+ 4.028000000000e-10 -3.932550397965e-01 
+ 4.128000000000e-10 -5.440358639049e-01 
+ 4.228000000000e-10 -5.974545613679e-01 
+ 4.328000000000e-10 -5.378639915963e-01 
+ 4.428000000000e-10 -3.948698115068e-01 
+ 4.528000000000e-10 -2.251456197037e-01 
+ 4.628000000000e-10 -5.904004941792e-02 
+ 4.728000000000e-10  1.153874791980e-01 
+ 4.828000000000e-10  3.018826859494e-01 
+ 4.928000000000e-10  4.777357070651e-01 
+ 5.028000000000e-10  5.850209286479e-01 
+ 5.128000000000e-10  5.804772883663e-01 
+ 5.228000000000e-10  4.728085019241e-01 
+ 5.328000000000e-10  3.089457683616e-01 
+ 5.428000000000e-10  1.412323614058e-01 
+ 5.528000000000e-10 -2.730899411782e-02 
+ 5.628000000000e-10 -2.089765034267e-01 
+ 5.728000000000e-10 -3.949384733604e-01 
+ 5.828000000000e-10 -5.451565863598e-01 
+ 5.928000000000e-10 -5.973527500019e-01 
+ 6.028000000000e-10 -5.368466314030e-01 
+ 6.128000000000e-10 -3.931843583920e-01 
+ 6.228000000000e-10 -2.235601147375e-01 
+ 6.328000000000e-10 -5.734349959237e-02 
+ 6.428000000000e-10  1.171162736371e-01 
+ 6.528000000000e-10  3.037703409726e-01 
+ 6.628000000000e-10  4.791912331459e-01 
+ 6.728000000000e-10  5.855798214314e-01 
+ 6.828000000000e-10  5.798240328394e-01 
+ 6.928000000000e-10  4.714288640290e-01 
+ 7.028000000000e-10  3.072315620121e-01 
+ 7.128000000000e-10  1.396641030954e-01 
+ 7.228000000000e-10 -2.905607141113e-02 
+ 7.328000000000e-10 -2.107594500296e-01 
+ 7.428000000000e-10 -3.967211258950e-01 
+ 7.528000000000e-10 -5.461706344704e-01 
+ 7.628000000000e-10 -5.973374521174e-01 
+ 7.728000000000e-10 -5.357205733965e-01 
+ 7.828000000000e-10 -3.915911928777e-01 
+ 7.928000000000e-10 -2.218810155195e-01 
+ 8.028000000000e-10 -5.573969116904e-02 
+ 8.128000000000e-10  1.189424413261e-01 
+ 8.228000000000e-10  3.055646827560e-01 
+ 8.328000000000e-10  4.807259154011e-01 
+ 8.428000000000e-10  5.860453138042e-01 
+ 8.528000000000e-10  5.792476749867e-01 
+ 8.628000000000e-10  4.699583360894e-01 
+ 8.728000000000e-10  3.056009455537e-01 
+ 8.828000000000e-10  1.380131640820e-01 
+ 8.928000000000e-10 -3.071912961450e-02 
+ 9.028000000000e-10 -2.126264792163e-01 
+ 9.128000000000e-10 -3.984185561653e-01 
+ 9.228000000000e-10 -5.472502664204e-01 
+ 9.328000000000e-10 -5.972326176360e-01 
+ 9.428000000000e-10 -5.346663530098e-01 
+ 9.528000000000e-10 -3.899201147490e-01 
+ 9.628000000000e-10 -2.202777602246e-01 
+ 9.728000000000e-10 -5.405978815575e-02 
+ 9.828000000000e-10  1.206936521389e-01 
+ 9.928000000000e-10  3.074328997109e-01 
+ 1.000000000000e-09  4.391748152565e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/conditions.yaml
new file mode 100644
index 00000000..3a3bb59b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 11
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_11
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb.sch
new file mode 100644
index 00000000..4c820c55
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb_12.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb_12.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb_12.data
new file mode 100644
index 00000000..17b5ef26
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_core_tb_12.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.555711411691e-01 
+ 1.728000000000e-10  5.654533109598e-01 
+ 1.828000000000e-10  4.795726584841e-01 
+ 1.928000000000e-10  3.326502253637e-01 
+ 2.028000000000e-10  1.687296913114e-01 
+ 2.128000000000e-10  2.259632268033e-03 
+ 2.228000000000e-10 -1.737904072321e-01 
+ 2.328000000000e-10 -3.537060570041e-01 
+ 2.428000000000e-10 -5.045948747149e-01 
+ 2.528000000000e-10 -5.731435474460e-01 
+ 2.628000000000e-10 -5.391555089404e-01 
+ 2.728000000000e-10 -4.213148150041e-01 
+ 2.828000000000e-10 -2.626455484716e-01 
+ 2.928000000000e-10 -9.794124042607e-02 
+ 3.028000000000e-10  7.187921157535e-02 
+ 3.128000000000e-10  2.517461177776e-01 
+ 3.228000000000e-10  4.250624796943e-01 
+ 3.328000000000e-10  5.465250931262e-01 
+ 3.428000000000e-10  5.707653915460e-01 
+ 3.528000000000e-10  4.967299254069e-01 
+ 3.628000000000e-10  3.552764122875e-01 
+ 3.728000000000e-10  1.920279556884e-01 
+ 3.828000000000e-10  2.619193487626e-02 
+ 3.928000000000e-10 -1.481848868503e-01 
+ 4.028000000000e-10 -3.289567215963e-01 
+ 4.128000000000e-10 -4.870422839129e-01 
+ 4.228000000000e-10 -5.697831693720e-01 
+ 4.328000000000e-10 -5.497939882973e-01 
+ 4.428000000000e-10 -4.417146267181e-01 
+ 4.528000000000e-10 -2.858120458911e-01 
+ 4.628000000000e-10 -1.213979132799e-01 
+ 4.728000000000e-10  4.724925592827e-02 
+ 4.828000000000e-10  2.259536453083e-01 
+ 4.928000000000e-10  4.023731180618e-01 
+ 5.028000000000e-10  5.346129641317e-01 
+ 5.128000000000e-10  5.737179052380e-01 
+ 5.228000000000e-10  5.122194835459e-01 
+ 5.328000000000e-10  3.776695186105e-01 
+ 5.428000000000e-10  2.152751132312e-01 
+ 5.528000000000e-10  5.007645335031e-02 
+ 5.628000000000e-10 -1.228407452739e-01 
+ 5.728000000000e-10 -3.036742853578e-01 
+ 5.828000000000e-10 -4.679879288367e-01 
+ 5.928000000000e-10 -5.641705522090e-01 
+ 6.028000000000e-10 -5.586855895079e-01 
+ 6.128000000000e-10 -4.609840869152e-01 
+ 6.228000000000e-10 -3.089721186467e-01 
+ 6.328000000000e-10 -1.446728205678e-01 
+ 6.428000000000e-10  2.279331244334e-02 
+ 6.528000000000e-10  2.003088005884e-01 
+ 6.628000000000e-10  3.787966390790e-01 
+ 6.728000000000e-10  5.208271612122e-01 
+ 6.828000000000e-10  5.744915662569e-01 
+ 6.928000000000e-10  5.263276638189e-01 
+ 7.028000000000e-10  3.995002166786e-01 
+ 7.128000000000e-10  2.386440244848e-01 
+ 7.228000000000e-10  7.372747398587e-02 
+ 7.328000000000e-10 -9.758660335090e-02 
+ 7.428000000000e-10 -2.781765911571e-01 
+ 7.528000000000e-10 -4.474216397573e-01 
+ 7.628000000000e-10 -5.565126829014e-01 
+ 7.728000000000e-10 -5.655838789355e-01 
+ 7.828000000000e-10 -4.792180968458e-01 
+ 7.928000000000e-10 -3.318840785190e-01 
+ 8.028000000000e-10 -1.680007152563e-01 
+ 8.128000000000e-10 -1.392642620268e-03 
+ 8.228000000000e-10  1.746034541840e-01 
+ 8.328000000000e-10  3.545844335081e-01 
+ 8.428000000000e-10  5.051160584363e-01 
+ 8.528000000000e-10  5.732956921486e-01 
+ 8.628000000000e-10  5.387645428348e-01 
+ 8.728000000000e-10  4.207248762860e-01 
+ 8.828000000000e-10  2.618825805652e-01 
+ 8.928000000000e-10  9.726427312832e-02 
+ 9.028000000000e-10 -7.269024640303e-02 
+ 9.128000000000e-10 -2.524920750937e-01 
+ 9.228000000000e-10 -4.257908972026e-01 
+ 9.328000000000e-10 -5.468163600121e-01 
+ 9.428000000000e-10 -5.706862728602e-01 
+ 9.528000000000e-10 -4.961873446797e-01 
+ 9.628000000000e-10 -3.546245289348e-01 
+ 9.728000000000e-10 -1.912707334797e-01 
+ 9.828000000000e-10 -2.549745252487e-02 
+ 9.928000000000e-10  1.490100171927e-01 
+ 1.000000000000e-09  2.804042562760e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/conditions.yaml
new file mode 100644
index 00000000..888ce14c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 12
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_12
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb.sch
new file mode 100644
index 00000000..f446017d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb_13.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb_13.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb_13.data
new file mode 100644
index 00000000..8b7e6d70
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_core_tb_13.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.371025020126e-01 
+ 1.728000000000e-10  5.671843434062e-01 
+ 1.828000000000e-10  5.026115974197e-01 
+ 1.928000000000e-10  3.698761175828e-01 
+ 2.028000000000e-10  2.107945230966e-01 
+ 2.128000000000e-10  4.885765443345e-02 
+ 2.228000000000e-10 -1.214244875766e-01 
+ 2.328000000000e-10 -3.000962430122e-01 
+ 2.428000000000e-10 -4.624539664009e-01 
+ 2.528000000000e-10 -5.578757965231e-01 
+ 2.628000000000e-10 -5.558325665603e-01 
+ 2.728000000000e-10 -4.651326499641e-01 
+ 2.828000000000e-10 -3.191410163203e-01 
+ 2.928000000000e-10 -1.584099737262e-01 
+ 3.028000000000e-10  5.260769792198e-03 
+ 3.128000000000e-10  1.792990320727e-01 
+ 3.228000000000e-10  3.568297244920e-01 
+ 3.328000000000e-10  5.033634481423e-01 
+ 3.428000000000e-10  5.679821613760e-01 
+ 3.528000000000e-10  5.348129833029e-01 
+ 3.628000000000e-10  4.215344084463e-01 
+ 3.728000000000e-10  2.671542738628e-01 
+ 3.828000000000e-10  1.058757320965e-01 
+ 3.928000000000e-10 -6.050653364250e-02 
+ 4.028000000000e-10 -2.376716892488e-01 
+ 4.128000000000e-10 -4.103945694446e-01 
+ 4.228000000000e-10 -5.351601037742e-01 
+ 4.328000000000e-10 -5.676142836602e-01 
+ 4.428000000000e-10 -5.052568222955e-01 
+ 4.528000000000e-10 -3.735630033165e-01 
+ 4.628000000000e-10 -2.147878950708e-01 
+ 4.728000000000e-10 -5.279672745046e-02 
+ 4.828000000000e-10  1.170845769200e-01 
+ 4.928000000000e-10  2.958542242500e-01 
+ 5.028000000000e-10  4.590288791838e-01 
+ 5.128000000000e-10  5.567565195036e-01 
+ 5.228000000000e-10  5.569827168059e-01 
+ 5.328000000000e-10  4.682426459242e-01 
+ 5.428000000000e-10  3.229559579659e-01 
+ 5.528000000000e-10  1.624050480172e-01 
+ 5.628000000000e-10 -1.216462084933e-03 
+ 5.728000000000e-10 -1.748700359540e-01 
+ 5.828000000000e-10 -3.527133673253e-01 
+ 5.928000000000e-10 -5.005383343433e-01 
+ 6.028000000000e-10 -5.676419424320e-01 
+ 6.128000000000e-10 -5.366502150486e-01 
+ 6.228000000000e-10 -4.250364870874e-01 
+ 6.328000000000e-10 -2.710292619083e-01 
+ 6.428000000000e-10 -1.098860218949e-01 
+ 6.528000000000e-10  5.636178196080e-02 
+ 6.628000000000e-10  2.332315395616e-01 
+ 6.728000000000e-10  4.065646248987e-01 
+ 6.828000000000e-10  5.330713538115e-01 
+ 6.928000000000e-10  5.680516295798e-01 
+ 7.028000000000e-10  5.077031668006e-01 
+ 7.128000000000e-10  3.773236938350e-01 
+ 7.228000000000e-10  2.186754316018e-01 
+ 7.328000000000e-10  5.685392835133e-02 
+ 7.428000000000e-10 -1.128372519467e-01 
+ 7.528000000000e-10 -2.914707069496e-01 
+ 7.628000000000e-10 -4.556375739225e-01 
+ 7.728000000000e-10 -5.554573322047e-01 
+ 7.828000000000e-10 -5.581623461271e-01 
+ 7.928000000000e-10 -4.712054490488e-01 
+ 8.028000000000e-10 -3.268259207673e-01 
+ 8.128000000000e-10 -1.662806807239e-01 
+ 8.228000000000e-10 -2.934244527428e-03 
+ 8.328000000000e-10  1.705229918111e-01 
+ 8.428000000000e-10  3.484637076667e-01 
+ 8.528000000000e-10  4.977273630891e-01 
+ 8.628000000000e-10  5.671286836934e-01 
+ 8.728000000000e-10  5.384999695443e-01 
+ 8.828000000000e-10  4.283929102026e-01 
+ 8.928000000000e-10  2.749581851622e-01 
+ 9.028000000000e-10  1.137763955641e-01 
+ 9.128000000000e-10 -5.216954389059e-02 
+ 9.228000000000e-10 -2.289115148628e-01 
+ 9.328000000000e-10 -4.026435402191e-01 
+ 9.428000000000e-10 -5.309621390281e-01 
+ 9.528000000000e-10 -5.682754939619e-01 
+ 9.628000000000e-10 -5.101282301777e-01 
+ 9.728000000000e-10 -3.809401272304e-01 
+ 9.828000000000e-10 -2.225992291958e-01 
+ 9.928000000000e-10 -6.078764252406e-02 
+ 1.000000000000e-09  5.969538211773e-02 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/conditions.yaml
new file mode 100644
index 00000000..ab043f8b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 13
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_13
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb.sch
new file mode 100644
index 00000000..98f70c99
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb_14.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb_14.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb_14.data
new file mode 100644
index 00000000..e2d4a86a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_core_tb_14.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.685994494077e-01 
+ 1.728000000000e-10  5.680033173677e-01 
+ 1.828000000000e-10  4.702563674856e-01 
+ 1.928000000000e-10  3.158730593689e-01 
+ 2.028000000000e-10  1.495129091369e-01 
+ 2.128000000000e-10 -1.953292317378e-02 
+ 2.228000000000e-10 -1.985217743373e-01 
+ 2.328000000000e-10 -3.791996140847e-01 
+ 2.428000000000e-10 -5.257312756755e-01 
+ 2.528000000000e-10 -5.827082806958e-01 
+ 2.628000000000e-10 -5.336126237469e-01 
+ 2.728000000000e-10 -4.031247045394e-01 
+ 2.828000000000e-10 -2.394215940201e-01 
+ 2.928000000000e-10 -7.255659698483e-02 
+ 3.028000000000e-10  1.005529440013e-01 
+ 3.128000000000e-10  2.828780215576e-01 
+ 3.228000000000e-10  4.542894564617e-01 
+ 3.328000000000e-10  5.653036008536e-01 
+ 3.428000000000e-10  5.725850512251e-01 
+ 3.528000000000e-10  4.810772025614e-01 
+ 3.628000000000e-10  3.289224425154e-01 
+ 3.728000000000e-10  1.627522206878e-01 
+ 3.828000000000e-10 -5.901236406385e-03 
+ 3.928000000000e-10 -1.839457166775e-01 
+ 4.028000000000e-10 -3.655051783869e-01 
+ 4.128000000000e-10 -5.167269598088e-01 
+ 4.228000000000e-10 -5.822517587470e-01 
+ 4.328000000000e-10 -5.410257088985e-01 
+ 4.428000000000e-10 -4.155309597132e-01 
+ 4.528000000000e-10 -2.526519838626e-01 
+ 4.628000000000e-10 -8.602442024441e-02 
+ 4.728000000000e-10  8.639716695153e-02 
+ 4.828000000000e-10  2.682378418749e-01 
+ 4.928000000000e-10  4.420446926342e-01 
+ 5.028000000000e-10  5.599611899078e-01 
+ 5.128000000000e-10  5.759765965943e-01 
+ 5.228000000000e-10  4.911677219482e-01 
+ 5.328000000000e-10  3.420625461523e-01 
+ 5.428000000000e-10  1.759664901080e-01 
+ 5.528000000000e-10  7.881982455238e-03 
+ 5.628000000000e-10 -1.694304774333e-01 
+ 5.728000000000e-10 -3.514381880500e-01 
+ 5.828000000000e-10 -5.071893150425e-01 
+ 5.928000000000e-10 -5.809527514514e-01 
+ 6.028000000000e-10 -5.479847244619e-01 
+ 6.128000000000e-10 -4.275846591595e-01 
+ 6.228000000000e-10 -2.659766117963e-01 
+ 6.328000000000e-10 -9.933722257759e-02 
+ 6.428000000000e-10  7.221956138870e-02 
+ 6.528000000000e-10  2.536833280759e-01 
+ 6.628000000000e-10  4.293709903854e-01 
+ 6.728000000000e-10  5.540487051204e-01 
+ 6.828000000000e-10  5.786193688372e-01 
+ 6.928000000000e-10  5.009476225142e-01 
+ 7.028000000000e-10  3.550417804446e-01 
+ 7.128000000000e-10  1.892841058759e-01 
+ 7.228000000000e-10  2.151387736973e-02 
+ 7.328000000000e-10 -1.548540580094e-01 
+ 7.428000000000e-10 -3.373021911532e-01 
+ 7.528000000000e-10 -4.969984208918e-01 
+ 7.628000000000e-10 -5.790298461209e-01 
+ 7.728000000000e-10 -5.542735467165e-01 
+ 7.828000000000e-10 -4.394491668012e-01 
+ 7.928000000000e-10 -2.791980749240e-01 
+ 8.028000000000e-10 -1.126948717144e-01 
+ 8.128000000000e-10  5.821099623132e-02 
+ 8.228000000000e-10  2.390333865018e-01 
+ 8.328000000000e-10  4.164796242174e-01 
+ 8.428000000000e-10  5.474016405952e-01 
+ 8.528000000000e-10  5.806820904512e-01 
+ 8.628000000000e-10  5.102199864307e-01 
+ 8.728000000000e-10  3.680116262167e-01 
+ 8.828000000000e-10  2.025355376563e-01 
+ 8.928000000000e-10  3.516640628822e-02 
+ 9.028000000000e-10 -1.404006287987e-01 
+ 9.128000000000e-10 -3.229571323578e-01 
+ 9.228000000000e-10 -4.863481312502e-01 
+ 9.328000000000e-10 -5.763266230399e-01 
+ 9.428000000000e-10 -5.600311989004e-01 
+ 9.528000000000e-10 -4.509360688916e-01 
+ 9.628000000000e-10 -2.924638512409e-01 
+ 9.728000000000e-10 -1.259546505516e-01 
+ 9.828000000000e-10  4.421130530697e-02 
+ 9.928000000000e-10  2.244486902223e-01 
+ 1.000000000000e-09  3.563189549212e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/conditions.yaml
new file mode 100644
index 00000000..f3906847
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 14
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_14
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb.sch
new file mode 100644
index 00000000..ee3209dd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb_15.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb_15.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb_15.data
new file mode 100644
index 00000000..2e85e4e6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_core_tb_15.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.344960387987e-01 
+ 1.728000000000e-10  5.452560643354e-01 
+ 1.828000000000e-10  4.673129977556e-01 
+ 1.928000000000e-10  3.303067915845e-01 
+ 2.028000000000e-10  1.707484920037e-01 
+ 2.128000000000e-10  5.181087662118e-03 
+ 2.228000000000e-10 -1.675494404811e-01 
+ 2.328000000000e-10 -3.401592495055e-01 
+ 2.428000000000e-10 -4.829519141621e-01 
+ 2.528000000000e-10 -5.505340174514e-01 
+ 2.628000000000e-10 -5.235059140976e-01 
+ 2.728000000000e-10 -4.172147065113e-01 
+ 2.828000000000e-10 -2.674081541308e-01 
+ 2.928000000000e-10 -1.048630150144e-01 
+ 3.028000000000e-10  6.333682141777e-02 
+ 3.128000000000e-10  2.380835653681e-01 
+ 3.228000000000e-10  4.036717768786e-01 
+ 3.328000000000e-10  5.212857330835e-01 
+ 3.428000000000e-10  5.508388819728e-01 
+ 3.528000000000e-10  4.886846456314e-01 
+ 3.628000000000e-10  3.600535598894e-01 
+ 3.728000000000e-10  2.028200071044e-01 
+ 3.828000000000e-10  3.817873185626e-02 
+ 3.928000000000e-10 -1.330304531359e-01 
+ 4.028000000000e-10 -3.073574559208e-01 
+ 4.128000000000e-10 -4.594561993841e-01 
+ 4.228000000000e-10 -5.448052398968e-01 
+ 4.328000000000e-10 -5.359418383134e-01 
+ 4.428000000000e-10 -4.429420179764e-01 
+ 4.528000000000e-10 -2.984950838016e-01 
+ 4.628000000000e-10 -1.373019478795e-01 
+ 4.728000000000e-10  2.965174653267e-02 
+ 4.828000000000e-10  2.035061242558e-01 
+ 4.928000000000e-10  3.733469326425e-01 
+ 5.028000000000e-10  5.041915675507e-01 
+ 5.128000000000e-10  5.527110611332e-01 
+ 5.228000000000e-10  5.072274444340e-01 
+ 5.328000000000e-10  3.888403459299e-01 
+ 5.428000000000e-10  2.345873591410e-01 
+ 5.528000000000e-10  7.106266792034e-02 
+ 5.628000000000e-10 -9.874543593339e-02 
+ 5.728000000000e-10 -2.735849121761e-01 
+ 5.828000000000e-10 -4.333235700941e-01 
+ 5.928000000000e-10 -5.351812080818e-01 
+ 6.028000000000e-10 -5.451422835470e-01 
+ 6.128000000000e-10 -4.665505412081e-01 
+ 6.228000000000e-10 -3.291302258797e-01 
+ 6.328000000000e-10 -1.694802467479e-01 
+ 6.428000000000e-10 -3.821233014841e-03 
+ 6.528000000000e-10  1.689419826635e-01 
+ 6.628000000000e-10  3.414985173658e-01 
+ 6.728000000000e-10  4.838530688650e-01 
+ 6.828000000000e-10  5.507420108834e-01 
+ 6.928000000000e-10  5.229758848356e-01 
+ 7.028000000000e-10  4.162178351163e-01 
+ 7.128000000000e-10  2.661956516874e-01 
+ 7.228000000000e-10  1.036319474485e-01 
+ 7.328000000000e-10 -6.464764646601e-02 
+ 7.428000000000e-10 -2.393878849216e-01 
+ 7.528000000000e-10 -4.048132784755e-01 
+ 7.628000000000e-10 -5.218578949147e-01 
+ 7.728000000000e-10 -5.507107181542e-01 
+ 7.828000000000e-10 -4.879111720627e-01 
+ 7.928000000000e-10 -3.589466891516e-01 
+ 8.028000000000e-10 -2.015905948669e-01 
+ 8.128000000000e-10 -3.693360096320e-02 
+ 8.228000000000e-10  1.343543548759e-01 
+ 8.328000000000e-10  3.086174200492e-01 
+ 8.428000000000e-10  4.604141752903e-01 
+ 8.528000000000e-10  5.450873437482e-01 
+ 8.628000000000e-10  5.355380307875e-01 
+ 8.728000000000e-10  4.419896176703e-01 
+ 8.828000000000e-10  2.973286305239e-01 
+ 8.928000000000e-10  1.360616231662e-01 
+ 9.028000000000e-10 -3.092064447201e-02 
+ 9.128000000000e-10 -2.048337989979e-01 
+ 9.228000000000e-10 -3.745222574082e-01 
+ 9.328000000000e-10 -5.049124474742e-01 
+ 9.428000000000e-10 -5.526994993257e-01 
+ 9.528000000000e-10 -5.065798817364e-01 
+ 9.628000000000e-10 -3.877585771317e-01 
+ 9.728000000000e-10 -2.333895166498e-01 
+ 9.828000000000e-10 -6.980875104219e-02 
+ 9.928000000000e-10  1.000379638374e-01 
+ 1.000000000000e-09  2.266578768883e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/conditions.yaml
new file mode 100644
index 00000000..37399e5f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 15
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_15
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb.sch
new file mode 100644
index 00000000..82789548
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb_16.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb_16.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb_16.data
new file mode 100644
index 00000000..f9e049c3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_core_tb_16.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.180119885725e-01 
+ 1.728000000000e-10  5.428150273087e-01 
+ 1.828000000000e-10  4.804584228924e-01 
+ 1.928000000000e-10  3.549741441244e-01 
+ 2.028000000000e-10  2.010895036379e-01 
+ 2.128000000000e-10  3.990849152816e-02 
+ 2.228000000000e-10 -1.285229050412e-01 
+ 2.328000000000e-10 -3.004511766915e-01 
+ 2.428000000000e-10 -4.509267588359e-01 
+ 2.528000000000e-10 -5.360472886334e-01 
+ 2.628000000000e-10 -5.308476150918e-01 
+ 2.728000000000e-10 -4.442065506601e-01 
+ 2.828000000000e-10 -3.056124141550e-01 
+ 2.928000000000e-10 -1.482443277933e-01 
+ 3.028000000000e-10  1.494851437600e-02 
+ 3.128000000000e-10  1.858420503105e-01 
+ 3.228000000000e-10  3.546289687231e-01 
+ 3.328000000000e-10  4.884116146647e-01 
+ 3.428000000000e-10  5.444051327513e-01 
+ 3.528000000000e-10  5.100351620157e-01 
+ 3.628000000000e-10  4.021886871948e-01 
+ 3.728000000000e-10  2.543879635859e-01 
+ 3.828000000000e-10  9.485214544103e-02 
+ 3.928000000000e-10 -7.075032672641e-02 
+ 4.028000000000e-10 -2.431563423365e-01 
+ 4.128000000000e-10 -4.051321357110e-01 
+ 4.228000000000e-10 -5.170375321361e-01 
+ 4.328000000000e-10 -5.425914254342e-01 
+ 4.428000000000e-10 -4.810164877195e-01 
+ 4.528000000000e-10 -3.557735325851e-01 
+ 4.628000000000e-10 -2.021049505527e-01 
+ 4.728000000000e-10 -4.082726638447e-02 
+ 4.828000000000e-10  1.274525546110e-01 
+ 4.928000000000e-10  2.995340763584e-01 
+ 5.028000000000e-10  4.501478854236e-01 
+ 5.128000000000e-10  5.358688831659e-01 
+ 5.228000000000e-10  5.310853197453e-01 
+ 5.328000000000e-10  4.449536567085e-01 
+ 5.428000000000e-10  3.064466861380e-01 
+ 5.528000000000e-10  1.492307891452e-01 
+ 5.628000000000e-10 -1.402970778054e-02 
+ 5.728000000000e-10 -1.847805764035e-01 
+ 5.828000000000e-10 -3.537555851935e-01 
+ 5.928000000000e-10 -4.877779299846e-01 
+ 6.028000000000e-10 -5.443965298452e-01 
+ 6.128000000000e-10 -5.104273583024e-01 
+ 6.228000000000e-10 -4.030190625192e-01 
+ 6.328000000000e-10 -2.552526844497e-01 
+ 6.428000000000e-10 -9.584365232983e-02 
+ 6.528000000000e-10  6.980767621840e-02 
+ 6.628000000000e-10  2.421063163491e-01 
+ 6.728000000000e-10  4.043299670627e-01 
+ 6.828000000000e-10  5.165725259787e-01 
+ 6.928000000000e-10  5.427511708711e-01 
+ 7.028000000000e-10  4.815471993596e-01 
+ 7.128000000000e-10  3.566618958690e-01 
+ 7.228000000000e-10  2.029878940739e-01 
+ 7.328000000000e-10  4.182623114247e-02 
+ 7.428000000000e-10 -1.264911878621e-01 
+ 7.528000000000e-10 -2.985161336122e-01 
+ 7.628000000000e-10 -4.494546695817e-01 
+ 7.728000000000e-10 -5.355872510690e-01 
+ 7.828000000000e-10 -5.314076392591e-01 
+ 7.928000000000e-10 -4.456031332240e-01 
+ 8.028000000000e-10 -3.073711989751e-01 
+ 8.128000000000e-10 -1.501267367277e-01 
+ 8.228000000000e-10  1.301977512060e-02 
+ 8.328000000000e-10  1.838083734602e-01 
+ 8.428000000000e-10  3.527931139928e-01 
+ 8.528000000000e-10  4.872248737515e-01 
+ 8.628000000000e-10  5.443010344572e-01 
+ 8.728000000000e-10  5.108995141754e-01 
+ 8.828000000000e-10  4.037638610128e-01 
+ 8.928000000000e-10  2.561974779182e-01 
+ 9.028000000000e-10  9.675266685198e-02 
+ 9.128000000000e-10 -6.878530852337e-02 
+ 9.228000000000e-10 -2.411372387693e-01 
+ 9.328000000000e-10 -4.034503900353e-01 
+ 9.428000000000e-10 -5.161800098612e-01 
+ 9.528000000000e-10 -5.428337693361e-01 
+ 9.628000000000e-10 -4.821501423095e-01 
+ 9.728000000000e-10 -3.574746220144e-01 
+ 9.828000000000e-10 -2.039425985968e-01 
+ 9.928000000000e-10 -4.275126436145e-02 
+ 1.000000000000e-09  7.745091708332e-02 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/conditions.yaml
new file mode 100644
index 00000000..fd6ef12a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 16
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_16
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb.sch
new file mode 100644
index 00000000..61ee9699
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb_17.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb_17.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb_17.data
new file mode 100644
index 00000000..c30d205a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_core_tb_17.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10  5.463781676649e-01 
+ 1.728000000000e-10  5.536807365176e-01 
+ 1.828000000000e-10  4.700770949122e-01 
+ 1.928000000000e-10  3.283560096374e-01 
+ 2.028000000000e-10  1.661765018961e-01 
+ 2.128000000000e-10 -1.672370944420e-03 
+ 2.228000000000e-10 -1.765606556303e-01 
+ 2.328000000000e-10 -3.508537683178e-01 
+ 2.428000000000e-10 -4.950313094104e-01 
+ 2.528000000000e-10 -5.620298540958e-01 
+ 2.628000000000e-10 -5.312461007842e-01 
+ 2.728000000000e-10 -4.198540992456e-01 
+ 2.828000000000e-10 -2.664960217947e-01 
+ 2.928000000000e-10 -1.016301612782e-01 
+ 3.028000000000e-10  6.876015467442e-02 
+ 3.128000000000e-10  2.454396012797e-01 
+ 3.228000000000e-10  4.129162458203e-01 
+ 3.328000000000e-10  5.323840357395e-01 
+ 3.428000000000e-10  5.614013358642e-01 
+ 3.528000000000e-10  4.957648642518e-01 
+ 3.628000000000e-10  3.630462655612e-01 
+ 3.728000000000e-10  2.031966960814e-01 
+ 3.828000000000e-10  3.641362117762e-02 
+ 3.928000000000e-10 -1.368114278219e-01 
+ 4.028000000000e-10 -3.130570983897e-01 
+ 4.128000000000e-10 -4.678223855211e-01 
+ 4.228000000000e-10 -5.556303003937e-01 
+ 4.328000000000e-10 -5.462642326143e-01 
+ 4.428000000000e-10 -4.501399217455e-01 
+ 4.528000000000e-10 -3.025339874182e-01 
+ 4.628000000000e-10 -1.391211386078e-01 
+ 4.728000000000e-10  2.985973753259e-02 
+ 4.828000000000e-10  2.055652009596e-01 
+ 4.928000000000e-10  3.777164222946e-01 
+ 5.028000000000e-10  5.123237313715e-01 
+ 5.128000000000e-10  5.636674481973e-01 
+ 5.228000000000e-10  5.176804469731e-01 
+ 5.328000000000e-10  3.966493941254e-01 
+ 5.428000000000e-10  2.399755060346e-01 
+ 5.528000000000e-10  7.439347821169e-02 
+ 5.628000000000e-10 -9.728144141853e-02 
+ 5.728000000000e-10 -2.740298162715e-01 
+ 5.828000000000e-10 -4.370863804142e-01 
+ 5.928000000000e-10 -5.439077566444e-01 
+ 6.028000000000e-10 -5.568064057279e-01 
+ 6.128000000000e-10 -4.776550720163e-01 
+ 6.228000000000e-10 -3.379986837372e-01 
+ 6.328000000000e-10 -1.763039651121e-01 
+ 6.428000000000e-10 -8.754956992321e-03 
+ 6.528000000000e-10  1.657016199867e-01 
+ 6.628000000000e-10  3.406597684088e-01 
+ 6.728000000000e-10  4.880038370068e-01 
+ 6.828000000000e-10  5.608300027041e-01 
+ 6.928000000000e-10  5.358420893635e-01 
+ 7.028000000000e-10  4.284358145311e-01 
+ 7.128000000000e-10  2.764778248798e-01 
+ 7.228000000000e-10  1.119749819386e-01 
+ 7.328000000000e-10 -5.800762940386e-02 
+ 7.428000000000e-10 -2.344840217603e-01 
+ 7.528000000000e-10 -4.034266117712e-01 
+ 7.628000000000e-10 -5.273160770028e-01 
+ 7.728000000000e-10 -5.625139938790e-01 
+ 7.828000000000e-10 -5.021596064605e-01 
+ 7.928000000000e-10 -3.724404268933e-01 
+ 8.028000000000e-10 -2.133571863679e-01 
+ 8.128000000000e-10 -4.690703294164e-02 
+ 8.228000000000e-10  1.258913504065e-01 
+ 8.328000000000e-10  3.023910361449e-01 
+ 8.428000000000e-10  4.596790829686e-01 
+ 8.528000000000e-10  5.529129573994e-01 
+ 8.628000000000e-10  5.496313201411e-01 
+ 8.728000000000e-10  4.580052762854e-01 
+ 8.828000000000e-10  3.123772721548e-01 
+ 8.928000000000e-10  1.493839199912e-01 
+ 9.028000000000e-10 -1.918666707897e-02 
+ 9.128000000000e-10 -1.945822922857e-01 
+ 9.228000000000e-10 -3.676654591511e-01 
+ 9.328000000000e-10 -5.060424720484e-01 
+ 9.428000000000e-10 -5.633948067326e-01 
+ 9.528000000000e-10 -5.230854707832e-01 
+ 9.628000000000e-10 -4.056020491363e-01 
+ 9.728000000000e-10 -2.500708181275e-01 
+ 9.828000000000e-10 -8.477389482638e-02 
+ 9.928000000000e-10  8.642889056701e-02 
+ 1.000000000000e-09  2.140970415562e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/conditions.yaml
new file mode 100644
index 00000000..c181174b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 17
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_17
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb.sch
new file mode 100644
index 00000000..daf632f5
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb_18.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb_18.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb_18.data
new file mode 100644
index 00000000..cc7811c4
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_core_tb_18.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.311365518451e-01 
+ 1.728000000000e-10 -5.592957758203e-01 
+ 1.828000000000e-10 -4.797488633791e-01 
+ 1.928000000000e-10 -3.322306134120e-01 
+ 2.028000000000e-10 -1.729422319394e-01 
+ 2.128000000000e-10 -1.699345238010e-02 
+ 2.228000000000e-10  1.494505024445e-01 
+ 2.328000000000e-10  3.277321819870e-01 
+ 2.428000000000e-10  4.870149438745e-01 
+ 2.528000000000e-10  5.631997225486e-01 
+ 2.628000000000e-10  5.268554024906e-01 
+ 2.728000000000e-10  4.016412888170e-01 
+ 2.828000000000e-10  2.419982611570e-01 
+ 2.928000000000e-10  8.556825878920e-02 
+ 3.028000000000e-10 -7.465365168675e-02 
+ 3.128000000000e-10 -2.494948470587e-01 
+ 3.228000000000e-10 -4.232379127345e-01 
+ 3.328000000000e-10 -5.434286569117e-01 
+ 3.428000000000e-10 -5.557093238954e-01 
+ 3.528000000000e-10 -4.638334293452e-01 
+ 3.628000000000e-10 -3.116470017089e-01 
+ 3.728000000000e-10 -1.529016666152e-01 
+ 3.828000000000e-10  3.530326886623e-03 
+ 3.928000000000e-10  1.720120307534e-01 
+ 4.028000000000e-10  3.502496598539e-01 
+ 4.128000000000e-10  5.026743598077e-01 
+ 4.228000000000e-10  5.645714571224e-01 
+ 4.328000000000e-10  5.146411371541e-01 
+ 4.428000000000e-10  3.815837412567e-01 
+ 4.528000000000e-10  2.215521808706e-01 
+ 4.628000000000e-10  6.558760297240e-02 
+ 4.728000000000e-10 -9.625239139173e-02 
+ 4.828000000000e-10 -2.725616547809e-01 
+ 4.928000000000e-10 -4.433312319638e-01 
+ 5.028000000000e-10 -5.516126019735e-01 
+ 5.128000000000e-10 -5.493294749001e-01 
+ 5.228000000000e-10 -4.466582063962e-01 
+ 5.328000000000e-10 -2.911102791776e-01 
+ 5.428000000000e-10 -1.330529430787e-01 
+ 5.528000000000e-10  2.419306484897e-02 
+ 5.628000000000e-10  1.946826166774e-01 
+ 5.728000000000e-10  3.723408844791e-01 
+ 5.828000000000e-10  5.166736750015e-01 
+ 5.928000000000e-10  5.640453324252e-01 
+ 6.028000000000e-10  5.010275355383e-01 
+ 6.128000000000e-10  3.611142538615e-01 
+ 6.228000000000e-10  2.011675579635e-01 
+ 6.328000000000e-10  4.543787953785e-02 
+ 6.428000000000e-10 -1.182323448552e-01 
+ 6.528000000000e-10 -2.956572850723e-01 
+ 6.628000000000e-10 -4.624607451942e-01 
+ 6.728000000000e-10 -5.578545785905e-01 
+ 6.828000000000e-10 -5.411926355366e-01 
+ 6.928000000000e-10 -4.285055769816e-01 
+ 7.028000000000e-10 -2.706297728416e-01 
+ 7.128000000000e-10 -1.132730447688e-01 
+ 7.228000000000e-10  4.503568429756e-02 
+ 7.328000000000e-10  2.174591325681e-01 
+ 7.428000000000e-10  3.939419516133e-01 
+ 7.528000000000e-10  5.290105305676e-01 
+ 7.628000000000e-10  5.617453823606e-01 
+ 7.728000000000e-10  4.862367997259e-01 
+ 7.828000000000e-10  3.404724989022e-01 
+ 7.928000000000e-10  1.809244921990e-01 
+ 8.028000000000e-10  2.511358192793e-02 
+ 8.128000000000e-10 -1.405112120148e-01 
+ 8.228000000000e-10 -3.186423567873e-01 
+ 8.328000000000e-10 -4.803054508961e-01 
+ 8.428000000000e-10 -5.620811329932e-01 
+ 8.528000000000e-10 -5.312734499961e-01 
+ 8.628000000000e-10 -4.094530758118e-01 
+ 8.728000000000e-10 -2.501524174489e-01 
+ 8.828000000000e-10 -9.347907818178e-02 
+ 8.928000000000e-10  6.615100779827e-02 
+ 9.028000000000e-10  2.403448238761e-01 
+ 9.128000000000e-10  4.150145923347e-01 
+ 9.228000000000e-10  5.396682113219e-01 
+ 9.328000000000e-10  5.577613949069e-01 
+ 9.428000000000e-10  4.704097965482e-01 
+ 9.528000000000e-10  3.198411419468e-01 
+ 9.628000000000e-10  1.608480611662e-01 
+ 9.728000000000e-10  4.653662126493e-03 
+ 9.828000000000e-10 -1.630114284973e-01 
+ 9.928000000000e-10 -3.413270422713e-01 
+ 1.000000000000e-09 -4.613528250395e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/conditions.yaml
new file mode 100644
index 00000000..7a230467
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 18
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_18
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb.sch
new file mode 100644
index 00000000..b07304f3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb_19.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb_19.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb_19.data
new file mode 100644
index 00000000..ce7734f4
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_core_tb_19.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.155675808532e-01 
+ 1.728000000000e-10 -5.590684876064e-01 
+ 1.828000000000e-10 -4.970485200967e-01 
+ 1.928000000000e-10 -3.613266108292e-01 
+ 2.028000000000e-10 -2.055839293821e-01 
+ 2.128000000000e-10 -5.419308304169e-02 
+ 2.228000000000e-10  1.051049218561e-01 
+ 2.328000000000e-10  2.795443727843e-01 
+ 2.428000000000e-10  4.471043056604e-01 
+ 2.528000000000e-10  5.502799551771e-01 
+ 2.628000000000e-10  5.466723192198e-01 
+ 2.728000000000e-10  4.475047904806e-01 
+ 2.828000000000e-10  2.965469054731e-01 
+ 2.928000000000e-10  1.424984493475e-01 
+ 3.028000000000e-10 -1.009734334473e-02 
+ 3.128000000000e-10 -1.761990552073e-01 
+ 3.228000000000e-10 -3.522714070339e-01 
+ 3.328000000000e-10 -5.015943728299e-01 
+ 3.428000000000e-10 -5.618459732258e-01 
+ 3.528000000000e-10 -5.151710002321e-01 
+ 3.628000000000e-10 -3.878721717088e-01 
+ 3.728000000000e-10 -2.320108967809e-01 
+ 3.828000000000e-10 -8.021590752923e-02 
+ 3.928000000000e-10  7.659358427726e-02 
+ 4.028000000000e-10  2.490479319101e-01 
+ 4.128000000000e-10  4.207782470121e-01 
+ 4.228000000000e-10  5.397262440240e-01 
+ 4.328000000000e-10  5.547212850072e-01 
+ 4.428000000000e-10  4.696030890105e-01 
+ 4.528000000000e-10  3.234581596635e-01 
+ 4.628000000000e-10  1.684623006214e-01 
+ 4.728000000000e-10  1.676979869404e-02 
+ 4.828000000000e-10 -1.464309122676e-01 
+ 4.928000000000e-10 -3.224564481247e-01 
+ 5.028000000000e-10 -4.808409761453e-01 
+ 5.128000000000e-10 -5.594658041433e-01 
+ 5.228000000000e-10 -5.302379687070e-01 
+ 5.328000000000e-10 -4.135626525439e-01 
+ 5.428000000000e-10 -2.587218271587e-01 
+ 5.528000000000e-10 -1.061069434306e-01 
+ 5.628000000000e-10  4.863244468104e-02 
+ 5.728000000000e-10  2.186435392419e-01 
+ 5.828000000000e-10  3.930244224828e-01 
+ 5.928000000000e-10  5.259796084394e-01 
+ 6.028000000000e-10  5.597842989924e-01 
+ 6.128000000000e-10  4.899102313230e-01 
+ 6.228000000000e-10  3.503762799238e-01 
+ 6.328000000000e-10  1.946627850762e-01 
+ 6.428000000000e-10  4.331344034385e-02 
+ 6.528000000000e-10 -1.170605128593e-01 
+ 6.628000000000e-10 -2.921153654664e-01 
+ 6.728000000000e-10 -4.574138319818e-01 
+ 6.828000000000e-10 -5.536758582513e-01 
+ 6.928000000000e-10 -5.425122630801e-01 
+ 7.028000000000e-10 -4.379661274856e-01 
+ 7.128000000000e-10 -2.855394493318e-01 
+ 7.228000000000e-10 -1.319119665575e-01 
+ 7.328000000000e-10  2.120629112930e-02 
+ 7.428000000000e-10  1.884806690649e-01 
+ 7.528000000000e-10  3.642798751115e-01 
+ 7.628000000000e-10  5.092746298205e-01 
+ 7.728000000000e-10  5.618748341869e-01 
+ 7.828000000000e-10  5.082788605290e-01 
+ 7.928000000000e-10  3.770821656158e-01 
+ 8.028000000000e-10  2.211144870134e-01 
+ 8.128000000000e-10  6.955039106327e-02 
+ 8.228000000000e-10 -8.822607507269e-02 
+ 8.328000000000e-10 -2.615556886470e-01 
+ 8.428000000000e-10 -4.317787817928e-01 
+ 8.528000000000e-10 -5.444558745209e-01 
+ 8.628000000000e-10 -5.517931188559e-01 
+ 8.728000000000e-10 -4.607631664440e-01 
+ 8.828000000000e-10 -3.124291013351e-01 
+ 8.928000000000e-10 -1.578021736335e-01 
+ 9.028000000000e-10 -5.805662459480e-03 
+ 9.128000000000e-10  1.585834552713e-01 
+ 9.228000000000e-10  3.347468424066e-01 
+ 9.328000000000e-10  4.896812097952e-01 
+ 9.428000000000e-10  5.608455231926e-01 
+ 9.528000000000e-10  5.243851341899e-01 
+ 9.628000000000e-10  4.031712702683e-01 
+ 9.728000000000e-10  2.477647716128e-01 
+ 9.828000000000e-10  9.552196707385e-02 
+ 9.928000000000e-10 -6.001371212577e-02 
+ 1.000000000000e-09 -1.819785427008e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/conditions.yaml
new file mode 100644
index 00000000..1f44945e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 19
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_19
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb.sch
new file mode 100644
index 00000000..ff550b9f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb_20.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb_20.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb_20.data
new file mode 100644
index 00000000..97f6482f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_core_tb_20.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.458151853251e-01 
+ 1.728000000000e-10 -5.643254766548e-01 
+ 1.828000000000e-10 -4.723962973094e-01 
+ 1.928000000000e-10 -3.161158967937e-01 
+ 2.028000000000e-10 -1.536236623040e-01 
+ 2.128000000000e-10  6.154159790893e-03 
+ 2.228000000000e-10  1.776400865005e-01 
+ 2.328000000000e-10  3.585728203369e-01 
+ 2.428000000000e-10  5.128898110550e-01 
+ 2.528000000000e-10  5.720795092985e-01 
+ 2.628000000000e-10  5.146802704471e-01 
+ 2.728000000000e-10  3.734987790907e-01 
+ 2.828000000000e-10  2.093224278876e-01 
+ 2.928000000000e-10  5.016262450452e-02 
+ 3.028000000000e-10 -1.160740173948e-01 
+ 3.128000000000e-10 -2.959691947518e-01 
+ 3.228000000000e-10 -4.664972833740e-01 
+ 3.328000000000e-10 -5.651437249055e-01 
+ 3.428000000000e-10 -5.468542207504e-01 
+ 3.528000000000e-10 -4.285892608711e-01 
+ 3.628000000000e-10 -2.656908007009e-01 
+ 3.728000000000e-10 -1.050444097649e-01 
+ 3.828000000000e-10  5.700889760574e-02 
+ 3.928000000000e-10  2.330826685219e-01 
+ 4.028000000000e-10  4.114835103448e-01 
+ 4.128000000000e-10  5.434543045193e-01 
+ 4.228000000000e-10  5.659306587180e-01 
+ 4.328000000000e-10  4.772694406511e-01 
+ 4.428000000000e-10  3.222111998943e-01 
+ 4.528000000000e-10  1.595126496403e-01 
+ 4.628000000000e-10 -8.158595572394e-05 
+ 4.728000000000e-10 -1.709892096568e-01 
+ 4.828000000000e-10 -3.519999279876e-01 
+ 4.928000000000e-10 -5.084951612902e-01 
+ 5.028000000000e-10 -5.720572917833e-01 
+ 5.128000000000e-10 -5.186602309448e-01 
+ 5.228000000000e-10 -3.795775987311e-01 
+ 5.328000000000e-10 -2.153237508215e-01 
+ 5.428000000000e-10 -5.608567178453e-02 
+ 5.528000000000e-10  1.096334054592e-01 
+ 5.628000000000e-10  2.892266745620e-01 
+ 5.728000000000e-10  4.609323786102e-01 
+ 5.828000000000e-10  5.635117430170e-01 
+ 5.928000000000e-10  5.495128317803e-01 
+ 6.028000000000e-10  4.341133868886e-01 
+ 6.128000000000e-10  2.716819382573e-01 
+ 6.228000000000e-10  1.108215375576e-01 
+ 6.328000000000e-10 -5.088594388569e-02 
+ 6.428000000000e-10 -2.264513702937e-01 
+ 6.528000000000e-10 -4.053353489572e-01 
+ 6.628000000000e-10 -5.403522985221e-01 
+ 6.728000000000e-10 -5.672014897407e-01 
+ 6.828000000000e-10 -4.820454848354e-01 
+ 6.928000000000e-10 -3.282943306675e-01 
+ 7.028000000000e-10 -1.653834725625e-01 
+ 7.128000000000e-10 -5.939055440262e-03 
+ 7.228000000000e-10  1.643952927308e-01 
+ 7.328000000000e-10  3.454317737162e-01 
+ 7.428000000000e-10  5.040001061821e-01 
+ 7.528000000000e-10  5.718789197400e-01 
+ 7.628000000000e-10  5.225332090982e-01 
+ 7.728000000000e-10  3.856179995450e-01 
+ 7.828000000000e-10  2.213278078794e-01 
+ 7.928000000000e-10  6.198746116702e-02 
+ 8.028000000000e-10 -1.032305577426e-01 
+ 8.128000000000e-10 -2.824883762098e-01 
+ 8.228000000000e-10 -4.552880309271e-01 
+ 8.328000000000e-10 -5.617059595217e-01 
+ 8.428000000000e-10 -5.520242696182e-01 
+ 8.528000000000e-10 -4.395509181377e-01 
+ 8.628000000000e-10 -2.776753414549e-01 
+ 8.728000000000e-10 -1.165949753256e-01 
+ 8.828000000000e-10  4.478485508267e-02 
+ 8.928000000000e-10  2.198282007479e-01 
+ 9.028000000000e-10  3.991459743212e-01 
+ 9.128000000000e-10  5.370997636905e-01 
+ 9.228000000000e-10  5.683346517250e-01 
+ 9.328000000000e-10  4.867396233883e-01 
+ 9.428000000000e-10  3.343950630196e-01 
+ 9.528000000000e-10  1.712745810974e-01 
+ 9.628000000000e-10  1.195401594982e-02 
+ 9.728000000000e-10 -1.578063240111e-01 
+ 9.828000000000e-10 -3.388254664564e-01 
+ 9.928000000000e-10 -4.993515803500e-01 
+ 1.000000000000e-09 -5.639567217174e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/conditions.yaml
new file mode 100644
index 00000000..0c6bad2c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 20
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_20
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb.sch
new file mode 100644
index 00000000..8857e213
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb_21.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb_21.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb_21.data
new file mode 100644
index 00000000..db5e56e6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_core_tb_21.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.967584163944e-01 
+ 1.728000000000e-10 -5.441307121147e-01 
+ 1.828000000000e-10 -4.869491122499e-01 
+ 1.928000000000e-10 -3.554632512115e-01 
+ 2.028000000000e-10 -1.988621239548e-01 
+ 2.128000000000e-10 -4.121542293437e-02 
+ 2.228000000000e-10  1.234192116705e-01 
+ 2.328000000000e-10  2.975128220079e-01 
+ 2.428000000000e-10  4.558011352882e-01 
+ 2.528000000000e-10  5.430951048215e-01 
+ 2.628000000000e-10  5.249696364398e-01 
+ 2.728000000000e-10  4.172520503926e-01 
+ 2.828000000000e-10  2.649511784525e-01 
+ 2.928000000000e-10  1.072252439852e-01 
+ 3.028000000000e-10 -5.314590859624e-02 
+ 3.128000000000e-10 -2.244467961392e-01 
+ 3.228000000000e-10 -3.944081861133e-01 
+ 3.328000000000e-10 -5.185011785564e-01 
+ 3.428000000000e-10 -5.449839484085e-01 
+ 3.528000000000e-10 -4.705368687179e-01 
+ 3.628000000000e-10 -3.305422608546e-01 
+ 3.728000000000e-10 -1.730083852902e-01 
+ 3.828000000000e-10 -1.502725063011e-02 
+ 3.928000000000e-10  1.514848242575e-01 
+ 4.028000000000e-10  3.255090834192e-01 
+ 4.128000000000e-10  4.764210192724e-01 
+ 4.228000000000e-10  5.473819399546e-01 
+ 4.328000000000e-10  5.126114234729e-01 
+ 4.428000000000e-10  3.941363884649e-01 
+ 4.528000000000e-10  2.393230716168e-01 
+ 4.628000000000e-10  8.172293040000e-02 
+ 4.728000000000e-10 -8.009952092223e-02 
+ 4.828000000000e-10 -2.528470149998e-01 
+ 4.928000000000e-10 -4.193789155753e-01 
+ 5.028000000000e-10 -5.302774742884e-01 
+ 5.128000000000e-10 -5.393121879551e-01 
+ 5.228000000000e-10 -4.511079223488e-01 
+ 5.328000000000e-10 -3.052703536520e-01 
+ 5.428000000000e-10 -1.474976315314e-01 
+ 5.528000000000e-10  1.115548934129e-02 
+ 5.628000000000e-10  1.796144633165e-01 
+ 5.728000000000e-10  3.527923691049e-01 
+ 5.828000000000e-10  4.946340719334e-01 
+ 5.928000000000e-10  5.486364242717e-01 
+ 6.028000000000e-10  4.978842118109e-01 
+ 6.128000000000e-10  3.699928712855e-01 
+ 6.228000000000e-10  2.136243513812e-01 
+ 6.328000000000e-10  5.606424822427e-02 
+ 6.428000000000e-10 -1.074494638422e-01 
+ 6.528000000000e-10 -2.811956311550e-01 
+ 6.628000000000e-10 -4.429543495671e-01 
+ 6.728000000000e-10 -5.392711864894e-01 
+ 6.828000000000e-10 -5.310358699952e-01 
+ 6.928000000000e-10 -4.301531742275e-01 
+ 7.028000000000e-10 -2.798496238488e-01 
+ 7.128000000000e-10 -1.220649947350e-01 
+ 7.228000000000e-10  3.758346172733e-02 
+ 7.328000000000e-10  2.078957475644e-01 
+ 7.428000000000e-10  3.793298108372e-01 
+ 7.528000000000e-10  5.104288103282e-01 
+ 7.628000000000e-10  5.470998205174e-01 
+ 7.728000000000e-10  4.811320557219e-01 
+ 7.828000000000e-10  3.451918285639e-01 
+ 7.928000000000e-10  1.879491684004e-01 
+ 8.028000000000e-10  3.020898924804e-02 
+ 8.128000000000e-10 -1.351690342614e-01 
+ 8.228000000000e-10 -3.093059054867e-01 
+ 8.328000000000e-10 -4.647122494429e-01 
+ 8.428000000000e-10 -5.452822275400e-01 
+ 8.528000000000e-10 -5.201390848957e-01 
+ 8.628000000000e-10 -4.077752992205e-01 
+ 8.728000000000e-10 -2.542922053220e-01 
+ 8.828000000000e-10 -9.661975914604e-02 
+ 8.928000000000e-10  6.432342589314e-02 
+ 9.028000000000e-10  2.362706572610e-01 
+ 9.128000000000e-10  4.049510846020e-01 
+ 9.228000000000e-10  5.237279887269e-01 
+ 9.328000000000e-10  5.429357050019e-01 
+ 9.428000000000e-10  4.626367298941e-01 
+ 9.528000000000e-10  3.200395578321e-01 
+ 9.628000000000e-10  1.623716797215e-01 
+ 9.728000000000e-10  4.151080756644e-03 
+ 9.828000000000e-10 -1.631757576893e-01 
+ 9.928000000000e-10 -3.369512690495e-01 
+ 1.000000000000e-09 -4.509059119523e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/conditions.yaml
new file mode 100644
index 00000000..8586e52a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 21
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_21
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb.sch
new file mode 100644
index 00000000..141c3009
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb_22.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb_22.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb_22.data
new file mode 100644
index 00000000..a4ce7c24
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_core_tb_22.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.848304249426e-01 
+ 1.728000000000e-10 -5.391759724127e-01 
+ 1.828000000000e-10 -4.922259523619e-01 
+ 1.928000000000e-10 -3.698272371178e-01 
+ 2.028000000000e-10 -2.180065872843e-01 
+ 2.128000000000e-10 -6.460953632397e-02 
+ 2.228000000000e-10  9.486881736254e-02 
+ 2.328000000000e-10  2.659762288236e-01 
+ 2.428000000000e-10  4.283087304849e-01 
+ 2.528000000000e-10  5.305600274544e-01 
+ 2.628000000000e-10  5.328402076396e-01 
+ 2.728000000000e-10  4.435481399688e-01 
+ 2.828000000000e-10  3.004968146615e-01 
+ 2.928000000000e-10  1.466955607821e-01 
+ 3.028000000000e-10 -7.955269451838e-03 
+ 3.128000000000e-10 -1.732653913612e-01 
+ 3.228000000000e-10 -3.446973183600e-01 
+ 3.328000000000e-10 -4.867593957189e-01 
+ 3.428000000000e-10 -5.444778628748e-01 
+ 3.528000000000e-10 -5.012307219623e-01 
+ 3.628000000000e-10 -3.811909292380e-01 
+ 3.728000000000e-10 -2.294630790072e-01 
+ 3.828000000000e-10 -7.603948824832e-02 
+ 3.928000000000e-10  8.251748845427e-02 
+ 4.028000000000e-10  2.530057604989e-01 
+ 4.128000000000e-10  4.174101003034e-01 
+ 4.228000000000e-10  5.262084834453e-01 
+ 4.328000000000e-10  5.362794555234e-01 
+ 4.428000000000e-10  4.529098257573e-01 
+ 4.528000000000e-10  3.122318792142e-01 
+ 4.628000000000e-10  1.584523736303e-01 
+ 4.728000000000e-10  4.199840693064e-03 
+ 4.828000000000e-10 -1.601057245874e-01 
+ 4.928000000000e-10 -3.319184262514e-01 
+ 5.028000000000e-10 -4.782861050312e-01 
+ 5.128000000000e-10 -5.437882777035e-01 
+ 5.228000000000e-10 -5.078115699859e-01 
+ 5.328000000000e-10 -3.922181326894e-01 
+ 5.428000000000e-10 -2.413352028336e-01 
+ 5.528000000000e-10 -8.785436874396e-02 
+ 5.628000000000e-10  6.988521236924e-02 
+ 5.728000000000e-10  2.396851953072e-01 
+ 5.828000000000e-10  4.059032189477e-01 
+ 5.928000000000e-10  5.210647965533e-01 
+ 6.028000000000e-10  5.390696565050e-01 
+ 6.128000000000e-10  4.619069423368e-01 
+ 6.228000000000e-10  3.239253657148e-01 
+ 6.328000000000e-10  1.702371555105e-01 
+ 6.428000000000e-10  1.630025752745e-02 
+ 6.528000000000e-10 -1.469932571368e-01 
+ 6.628000000000e-10 -3.189977520107e-01 
+ 6.728000000000e-10 -4.692924010411e-01 
+ 6.828000000000e-10 -5.424709166410e-01 
+ 6.928000000000e-10 -5.139003061272e-01 
+ 7.028000000000e-10 -4.030319985636e-01 
+ 7.128000000000e-10 -2.532011514544e-01 
+ 7.228000000000e-10 -9.964112975079e-02 
+ 7.328000000000e-10  5.734317287693e-02 
+ 7.428000000000e-10  2.263630430604e-01 
+ 7.528000000000e-10  3.941121782167e-01 
+ 7.628000000000e-10  5.153270127073e-01 
+ 7.728000000000e-10  5.412967448822e-01 
+ 7.828000000000e-10  4.705474701310e-01 
+ 7.928000000000e-10  3.355637546850e-01 
+ 8.028000000000e-10  1.820411848493e-01 
+ 8.128000000000e-10  2.834442810943e-02 
+ 8.228000000000e-10 -1.339458962945e-01 
+ 8.328000000000e-10 -3.059576766696e-01 
+ 8.428000000000e-10 -4.598017832852e-01 
+ 8.528000000000e-10 -5.405123993680e-01 
+ 8.628000000000e-10 -5.194744212788e-01 
+ 8.728000000000e-10 -4.135975609875e-01 
+ 8.828000000000e-10 -2.650548198522e-01 
+ 8.928000000000e-10 -1.114064015915e-01 
+ 9.028000000000e-10  4.488627822513e-02 
+ 9.128000000000e-10  2.130539878193e-01 
+ 9.228000000000e-10  3.820706486624e-01 
+ 9.328000000000e-10  5.090159169311e-01 
+ 9.428000000000e-10  5.429577078007e-01 
+ 9.528000000000e-10  4.788190270704e-01 
+ 9.628000000000e-10  3.471301013300e-01 
+ 9.728000000000e-10  1.938672644672e-01 
+ 9.828000000000e-10  4.033398182710e-02 
+ 9.928000000000e-10 -1.209697116944e-01 
+ 1.000000000000e-09 -2.451863854579e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/conditions.yaml
new file mode 100644
index 00000000..2f1f9908
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 22
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_22
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb.sch
new file mode 100644
index 00000000..b0417a2c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb_23.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb_23.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb_23.data
new file mode 100644
index 00000000..d5da674a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_core_tb_23.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -5.031698867449e-01 
+ 1.728000000000e-10 -5.559494115492e-01 
+ 1.828000000000e-10 -4.998730322938e-01 
+ 1.928000000000e-10 -3.658283790605e-01 
+ 2.028000000000e-10 -2.057211236409e-01 
+ 2.128000000000e-10 -4.489568269094e-02 
+ 2.228000000000e-10  1.222382606752e-01 
+ 2.328000000000e-10  2.986158355312e-01 
+ 2.428000000000e-10  4.606359926614e-01 
+ 2.528000000000e-10  5.521473773306e-01 
+ 2.628000000000e-10  5.345812393627e-01 
+ 2.728000000000e-10  4.238201873249e-01 
+ 2.828000000000e-10  2.676796377075e-01 
+ 2.928000000000e-10  1.066794684340e-01 
+ 3.028000000000e-10 -5.678604565117e-02 
+ 3.128000000000e-10 -2.306492037078e-01 
+ 3.228000000000e-10 -4.028933320857e-01 
+ 3.328000000000e-10 -5.288428511057e-01 
+ 3.428000000000e-10 -5.537272595675e-01 
+ 3.528000000000e-10 -4.743039424122e-01 
+ 3.628000000000e-10 -3.290350313112e-01 
+ 3.728000000000e-10 -1.680892829913e-01 
+ 3.828000000000e-10 -6.795755635653e-03 
+ 3.928000000000e-10  1.629203496285e-01 
+ 4.028000000000e-10  3.391611982248e-01 
+ 4.128000000000e-10  4.905466116494e-01 
+ 4.228000000000e-10  5.578106684004e-01 
+ 4.328000000000e-10  5.155575864532e-01 
+ 4.428000000000e-10  3.893295485048e-01 
+ 4.528000000000e-10  2.300915101026e-01 
+ 4.628000000000e-10  6.929126792669e-02 
+ 4.728000000000e-10 -9.624408118273e-02 
+ 4.828000000000e-10 -2.719338399007e-01 
+ 4.928000000000e-10 -4.389200417759e-01 
+ 5.028000000000e-10 -5.449342986188e-01 
+ 5.128000000000e-10 -5.439031126331e-01 
+ 5.228000000000e-10 -4.446530253554e-01 
+ 5.328000000000e-10 -2.918490615077e-01 
+ 5.428000000000e-10 -1.307639726990e-01 
+ 5.528000000000e-10  3.164732743246e-02 
+ 5.628000000000e-10  2.039847772760e-01 
+ 5.728000000000e-10  3.784050515971e-01 
+ 5.828000000000e-10  5.154866410800e-01 
+ 5.928000000000e-10  5.571793595685e-01 
+ 6.028000000000e-10  4.917497295790e-01 
+ 6.128000000000e-10  3.529773366480e-01 
+ 6.228000000000e-10  1.923890461403e-01 
+ 6.328000000000e-10  3.147558002288e-02 
+ 6.428000000000e-10 -1.365240202614e-01 
+ 6.528000000000e-10 -3.130216882928e-01 
+ 6.628000000000e-10 -4.717005257356e-01 
+ 6.728000000000e-10 -5.548816454072e-01 
+ 6.828000000000e-10 -5.284672024606e-01 
+ 6.928000000000e-10 -4.119333253215e-01 
+ 7.028000000000e-10 -2.544413325779e-01 
+ 7.128000000000e-10 -9.352454025311e-02 
+ 7.228000000000e-10  7.062104261896e-02 
+ 7.328000000000e-10  2.452119740286e-01 
+ 7.428000000000e-10  4.158977506374e-01 
+ 7.528000000000e-10  5.351728589329e-01 
+ 7.628000000000e-10  5.508876924354e-01 
+ 7.728000000000e-10  4.641954978457e-01 
+ 7.828000000000e-10  3.159291426141e-01 
+ 7.928000000000e-10  1.548820672850e-01 
+ 8.028000000000e-10 -6.726886093597e-03 
+ 8.128000000000e-10 -1.773917774576e-01 
+ 8.228000000000e-10 -3.531882556336e-01 
+ 8.328000000000e-10 -4.999436828040e-01 
+ 8.428000000000e-10 -5.582723309440e-01 
+ 8.528000000000e-10 -5.076454127540e-01 
+ 8.628000000000e-10 -3.766411335267e-01 
+ 8.728000000000e-10 -2.167811502550e-01 
+ 8.828000000000e-10 -5.599118467032e-02 
+ 8.928000000000e-10  1.103715238301e-01 
+ 9.028000000000e-10  2.864948163408e-01 
+ 9.128000000000e-10  4.509329110582e-01 
+ 9.228000000000e-10  5.491880863676e-01 
+ 9.328000000000e-10  5.390993007317e-01 
+ 9.428000000000e-10  4.334459560763e-01 
+ 9.528000000000e-10  2.786741986561e-01 
+ 9.628000000000e-10  1.176317365997e-01 
+ 9.728000000000e-10 -4.533239585396e-02 
+ 9.828000000000e-10 -2.185195339366e-01 
+ 9.928000000000e-10 -3.918650482151e-01 
+ 1.000000000000e-09 -4.962236612550e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/conditions.yaml
new file mode 100644
index 00000000..3d23fe4b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 23
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_23
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb.sch
new file mode 100644
index 00000000..6b2776b5
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb_24.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb_24.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb_24.data
new file mode 100644
index 00000000..c41c24d8
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_core_tb_24.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.327910324256e-01 
+ 1.728000000000e-10 -5.104523204344e-01 
+ 1.828000000000e-10 -4.919049595295e-01 
+ 1.928000000000e-10 -3.909061576120e-01 
+ 2.028000000000e-10 -2.463905832969e-01 
+ 2.128000000000e-10 -9.030729814880e-02 
+ 2.228000000000e-10  7.090337967192e-02 
+ 2.328000000000e-10  2.391128518003e-01 
+ 2.428000000000e-10  3.979068244163e-01 
+ 2.528000000000e-10  5.057784369939e-01 
+ 2.628000000000e-10  5.222442811568e-01 
+ 2.728000000000e-10  4.475463421234e-01 
+ 2.828000000000e-10  3.135857176625e-01 
+ 2.928000000000e-10  1.594708320831e-01 
+ 3.028000000000e-10  8.984576080604e-04 
+ 3.128000000000e-10 -1.645587525434e-01 
+ 3.228000000000e-10 -3.311340835825e-01 
+ 3.328000000000e-10 -4.679485266507e-01 
+ 3.428000000000e-10 -5.277100272002e-01 
+ 3.528000000000e-10 -4.910003875365e-01 
+ 3.628000000000e-10 -3.782517931754e-01 
+ 3.728000000000e-10 -2.293684093697e-01 
+ 3.828000000000e-10 -7.248392410840e-02 
+ 3.928000000000e-10  8.947351034921e-02 
+ 4.028000000000e-10  2.577913488707e-01 
+ 4.128000000000e-10  4.135082684608e-01 
+ 4.228000000000e-10  5.128426072357e-01 
+ 4.328000000000e-10  5.187626011362e-01 
+ 4.428000000000e-10  4.357788211303e-01 
+ 4.528000000000e-10  2.980558508264e-01 
+ 4.628000000000e-10  1.431490581765e-01 
+ 4.728000000000e-10 -1.591265626250e-02 
+ 4.828000000000e-10 -1.821667232795e-01 
+ 4.928000000000e-10 -3.475025723663e-01 
+ 5.028000000000e-10 -4.784637362759e-01 
+ 5.128000000000e-10 -5.282831491711e-01 
+ 5.228000000000e-10 -4.822697516961e-01 
+ 5.328000000000e-10 -3.637830931217e-01 
+ 5.428000000000e-10 -2.133005363205e-01 
+ 5.528000000000e-10 -5.603973127618e-02 
+ 5.628000000000e-10  1.066850525713e-01 
+ 5.728000000000e-10  2.750581839130e-01 
+ 5.828000000000e-10  4.273008627169e-01 
+ 5.928000000000e-10  5.181067568383e-01 
+ 6.028000000000e-10  5.139063333086e-01 
+ 6.128000000000e-10  4.233641609123e-01 
+ 6.228000000000e-10  2.823752498996e-01 
+ 6.328000000000e-10  1.269005897264e-01 
+ 6.428000000000e-10 -3.275126442225e-02 
+ 6.528000000000e-10 -1.996704202465e-01 
+ 6.628000000000e-10 -3.634780398743e-01 
+ 6.728000000000e-10 -4.879892997483e-01 
+ 6.828000000000e-10 -5.277920833828e-01 
+ 6.928000000000e-10 -4.727131411481e-01 
+ 7.028000000000e-10 -3.490253785841e-01 
+ 7.128000000000e-10 -1.971666354585e-01 
+ 7.228000000000e-10 -3.957870648492e-02 
+ 7.328000000000e-10  1.239927359929e-01 
+ 7.428000000000e-10  2.921256198799e-01 
+ 7.528000000000e-10  4.404193015741e-01 
+ 7.628000000000e-10  5.222557511529e-01 
+ 7.728000000000e-10  5.081185505306e-01 
+ 7.828000000000e-10  4.103785543253e-01 
+ 7.928000000000e-10  2.665844078783e-01 
+ 8.028000000000e-10  1.105880832534e-01 
+ 8.128000000000e-10 -4.965159634504e-02 
+ 8.228000000000e-10 -2.171832072956e-01 
+ 8.328000000000e-10 -3.790547756631e-01 
+ 8.428000000000e-10 -4.966582386238e-01 
+ 8.528000000000e-10 -5.262999861314e-01 
+ 8.628000000000e-10 -4.624510461450e-01 
+ 8.728000000000e-10 -3.339637098432e-01 
+ 8.828000000000e-10 -1.809943980113e-01 
+ 8.928000000000e-10 -2.300609478627e-02 
+ 9.028000000000e-10  1.413751270982e-01 
+ 9.128000000000e-10  3.090431666435e-01 
+ 9.228000000000e-10  4.527815787591e-01 
+ 9.328000000000e-10  5.253391487746e-01 
+ 9.428000000000e-10  5.013727724367e-01 
+ 9.528000000000e-10  3.969006854251e-01 
+ 9.628000000000e-10  2.506746363374e-01 
+ 9.728000000000e-10  9.427227745141e-02 
+ 9.828000000000e-10 -6.667584352686e-02 
+ 9.928000000000e-10 -2.346505575192e-01 
+ 1.000000000000e-09 -3.536890741260e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/conditions.yaml
new file mode 100644
index 00000000..b187d61a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 24
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_24
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb.sch
new file mode 100644
index 00000000..60a09d77
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb_25.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb_25.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb_25.data
new file mode 100644
index 00000000..5b20472d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_core_tb_25.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.234652372470e-01 
+ 1.728000000000e-10 -5.023350411985e-01 
+ 1.828000000000e-10 -4.882370947196e-01 
+ 1.928000000000e-10 -3.934622991782e-01 
+ 2.028000000000e-10 -2.540849756424e-01 
+ 2.128000000000e-10 -1.022077626652e-01 
+ 2.228000000000e-10  5.487463989292e-02 
+ 2.328000000000e-10  2.201387084143e-01 
+ 2.428000000000e-10  3.793010385310e-01 
+ 2.528000000000e-10  4.928092825825e-01 
+ 2.628000000000e-10  5.196604221395e-01 
+ 2.728000000000e-10  4.569333044751e-01 
+ 2.828000000000e-10  3.319491455483e-01 
+ 2.928000000000e-10  1.828241959120e-01 
+ 3.028000000000e-10  2.875417263246e-02 
+ 3.128000000000e-10 -1.322085231319e-01 
+ 3.228000000000e-10 -2.979591628573e-01 
+ 3.328000000000e-10 -4.419921797151e-01 
+ 3.428000000000e-10 -5.181142235199e-01 
+ 3.528000000000e-10 -5.011276271936e-01 
+ 3.628000000000e-10 -4.047301057605e-01 
+ 3.728000000000e-10 -2.642146009991e-01 
+ 3.828000000000e-10 -1.120554869934e-01 
+ 3.928000000000e-10  4.449697941514e-02 
+ 4.028000000000e-10  2.092158976339e-01 
+ 4.128000000000e-10  3.698137386910e-01 
+ 4.228000000000e-10  4.880993908984e-01 
+ 4.328000000000e-10  5.216646824640e-01 
+ 4.428000000000e-10  4.646374646662e-01 
+ 4.528000000000e-10  3.428387452384e-01 
+ 4.628000000000e-10  1.944050088817e-01 
+ 4.728000000000e-10  4.065056841101e-02 
+ 4.828000000000e-10 -1.196538800530e-01 
+ 4.928000000000e-10 -2.856080481145e-01 
+ 5.028000000000e-10 -4.328604027743e-01 
+ 5.128000000000e-10 -5.155684125841e-01 
+ 5.228000000000e-10 -5.056146117143e-01 
+ 5.328000000000e-10 -4.141876506985e-01 
+ 5.428000000000e-10 -2.756803009980e-01 
+ 5.528000000000e-10 -1.238226525070e-01 
+ 5.628000000000e-10  3.221018080289e-02 
+ 5.728000000000e-10  1.964355129807e-01 
+ 5.828000000000e-10  3.583575591201e-01 
+ 5.928000000000e-10  4.816985038066e-01 
+ 6.028000000000e-10  5.224947498493e-01 
+ 6.128000000000e-10  4.718193125923e-01 
+ 6.228000000000e-10  3.536174083497e-01 
+ 6.328000000000e-10  2.061296412053e-01 
+ 6.428000000000e-10  5.261608296359e-02 
+ 6.528000000000e-10 -1.069794898843e-01 
+ 6.628000000000e-10 -2.730503720825e-01 
+ 6.728000000000e-10 -4.231934075288e-01 
+ 6.828000000000e-10 -5.124136353084e-01 
+ 6.928000000000e-10 -5.095785569986e-01 
+ 7.028000000000e-10 -4.234260154720e-01 
+ 7.128000000000e-10 -2.870921093466e-01 
+ 7.228000000000e-10 -1.356399571892e-01 
+ 7.328000000000e-10  1.994586721238e-02 
+ 7.428000000000e-10  1.835653494556e-01 
+ 7.528000000000e-10  3.466515630325e-01 
+ 7.628000000000e-10  4.747178407660e-01 
+ 7.728000000000e-10  5.227707225181e-01 
+ 7.828000000000e-10  4.785566684900e-01 
+ 7.928000000000e-10  3.642543025781e-01 
+ 8.028000000000e-10  2.178048074733e-01 
+ 8.128000000000e-10  6.456648208830e-02 
+ 8.228000000000e-10 -9.438288801709e-02 
+ 8.328000000000e-10 -2.603879663713e-01 
+ 8.428000000000e-10 -4.131715855760e-01 
+ 8.528000000000e-10 -5.086601982059e-01 
+ 8.628000000000e-10 -5.130504205797e-01 
+ 8.728000000000e-10 -4.323341026072e-01 
+ 8.828000000000e-10 -2.984457952852e-01 
+ 8.928000000000e-10 -1.474159969866e-01 
+ 9.028000000000e-10  7.721087988347e-03 
+ 9.128000000000e-10  1.707348336950e-01 
+ 9.228000000000e-10  3.347409452624e-01 
+ 9.328000000000e-10  4.672737333583e-01 
+ 9.428000000000e-10  5.224691058784e-01 
+ 9.528000000000e-10  4.848897255043e-01 
+ 9.628000000000e-10  3.746840785486e-01 
+ 9.728000000000e-10  2.294653719965e-01 
+ 9.828000000000e-10  7.645843789077e-02 
+ 9.928000000000e-10 -8.182784111963e-02 
+ 1.000000000000e-09 -2.014421894108e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/conditions.yaml
new file mode 100644
index 00000000..5feb9da2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 25
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_25
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb.sch
new file mode 100644
index 00000000..b257137a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb.sch
@@ -0,0 +1,73 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 740 -940 740 -920 {lab=GND}
+N 740 -1090 740 -1060 {lab=VDD}
+N 600 -1020 620 -1020 {lab=Vinplus}
+N 600 -980 620 -980 {lab=Vinminus}
+N 860 -1020 880 -1020 {lab=Voplus}
+N 860 -980 880 -980 {lab=Vominus}
+N 1150 -850 1150 -820 {lab=VDD}
+N 1150 -760 1150 -730 {lab=GND}
+N 930 -850 930 -820 {lab=Vinminus}
+N 930 -760 930 -730 {lab=GND}
+N 720 -850 720 -820 {lab=Vinplus}
+N 720 -760 720 -730 {lab=GND}
+C {code_shown.sym} 10 -1220 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.param A=0
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write CML_core_tb.raw
+set appendwrite
+tran 10p 1n 160p
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb_26.data vo_diff
+quit
+
+.endc
+"}
+C {opin.sym} 880 -1020 2 1 {name=p6 lab=Voplus}
+C {opin.sym} 880 -980 0 0 {name=p9 lab=Vominus}
+C {devices/code_shown.sym} 10 -620 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 740 -1090 0 1 {name=p2 lab=VDD}
+C {ipin.sym} 600 -1020 2 1 {name=p4 lab=Vinplus}
+C {ipin.sym} 600 -980 2 1 {name=p1 lab=Vinminus}
+C {CML_divider.sym} 740 -1000 0 1 {name=x1}
+C {vsource.sym} 1150 -790 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1150 -730 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1150 -850 0 0 {name=p5 sig_type=std_logic lab=VDD}
+C {gnd.sym} 930 -730 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 930 -850 0 0 {name=p8 sig_type=std_logic lab=Vinminus}
+C {vsource.sym} 720 -790 0 0 {name=V3 value="SIN(0.6 A 10G 0 0 0)" savecurrent=false}
+C {gnd.sym} 720 -730 0 0 {name=l4 lab=GND
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {lab_pin.sym} 720 -850 0 0 {name=p10 sig_type=std_logic lab=Vinplus
+value="dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"}
+C {vsource.sym} 930 -790 0 0 {name=V2 value="SIN(0.6 A 10G 0 0 180)" savecurrent=false}
+C {gnd.sym} 740 -920 0 0 {name=l3 lab=GND}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb_26.data b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb_26.data
new file mode 100644
index 00000000..f50fb91c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_core_tb_26.data
@@ -0,0 +1,85 @@
+ 1.628000000000e-10 -4.323817786181e-01 
+ 1.728000000000e-10 -5.218197731172e-01 
+ 1.828000000000e-10 -5.130055457506e-01 
+ 1.928000000000e-10 -4.161806120260e-01 
+ 2.028000000000e-10 -2.707614247853e-01 
+ 2.128000000000e-10 -1.119567587354e-01 
+ 2.228000000000e-10  5.136762599758e-02 
+ 2.328000000000e-10  2.215286991565e-01 
+ 2.428000000000e-10  3.860326290053e-01 
+ 2.528000000000e-10  5.068500219960e-01 
+ 2.628000000000e-10  5.377768628838e-01 
+ 2.728000000000e-10  4.721051539524e-01 
+ 2.828000000000e-10  3.402635220541e-01 
+ 2.928000000000e-10  1.841583768191e-01 
+ 3.028000000000e-10  2.301269990977e-02 
+ 3.128000000000e-10 -1.440620364153e-01 
+ 3.228000000000e-10 -3.141964231002e-01 
+ 3.328000000000e-10 -4.612191139012e-01 
+ 3.428000000000e-10 -5.367771990781e-01 
+ 3.528000000000e-10 -5.127750466140e-01 
+ 3.628000000000e-10 -4.056871368496e-01 
+ 3.728000000000e-10 -2.562682158482e-01 
+ 3.828000000000e-10 -9.672900675225e-02 
+ 3.928000000000e-10  6.713808807349e-02 
+ 4.028000000000e-10  2.375373509974e-01 
+ 4.128000000000e-10  4.000093780223e-01 
+ 4.228000000000e-10  5.140628089507e-01 
+ 4.328000000000e-10  5.356814484820e-01 
+ 4.428000000000e-10  4.622754301517e-01 
+ 4.528000000000e-10  3.266573796267e-01 
+ 4.628000000000e-10  1.696986500434e-01 
+ 4.728000000000e-10  8.224133790347e-03 
+ 4.828000000000e-10 -1.595501346883e-01 
+ 4.928000000000e-10 -3.290121653328e-01 
+ 5.028000000000e-10 -4.717216871818e-01 
+ 5.128000000000e-10 -5.386966497187e-01 
+ 5.228000000000e-10 -5.060218758391e-01 
+ 5.328000000000e-10 -3.932361292887e-01 
+ 5.428000000000e-10 -2.420585407817e-01 
+ 5.528000000000e-10 -8.215190368253e-02 
+ 5.628000000000e-10  8.228124773791e-02 
+ 5.728000000000e-10  2.529751404914e-01 
+ 5.828000000000e-10  4.131313439142e-01 
+ 5.928000000000e-10  5.202699684622e-01 
+ 6.028000000000e-10  5.326658673636e-01 
+ 6.128000000000e-10  4.519586245162e-01 
+ 6.228000000000e-10  3.128850848163e-01 
+ 6.328000000000e-10  1.552673526240e-01 
+ 6.428000000000e-10 -6.618031234040e-03 
+ 6.528000000000e-10 -1.750036732844e-01 
+ 6.628000000000e-10 -3.436243240549e-01 
+ 6.728000000000e-10 -4.815176030347e-01 
+ 6.828000000000e-10 -5.397683152546e-01 
+ 6.928000000000e-10 -4.985592512398e-01 
+ 7.028000000000e-10 -3.805077765022e-01 
+ 7.128000000000e-10 -2.277734449826e-01 
+ 7.228000000000e-10 -6.758418108638e-02 
+ 7.328000000000e-10  9.750342024286e-02 
+ 7.428000000000e-10  2.682954130339e-01 
+ 7.528000000000e-10  4.258393021470e-01 
+ 7.628000000000e-10  5.256345626853e-01 
+ 7.728000000000e-10  5.289060292912e-01 
+ 7.828000000000e-10  4.411430993719e-01 
+ 7.928000000000e-10  2.990145992376e-01 
+ 8.028000000000e-10  1.407841701293e-01 
+ 8.128000000000e-10 -2.148551411031e-02 
+ 8.228000000000e-10 -1.904941552057e-01 
+ 8.328000000000e-10 -3.579942758686e-01 
+ 8.428000000000e-10 -4.907023738119e-01 
+ 8.528000000000e-10 -5.400209406036e-01 
+ 8.628000000000e-10 -4.904872044524e-01 
+ 8.728000000000e-10 -3.674750163499e-01 
+ 8.828000000000e-10 -2.134433797210e-01 
+ 8.928000000000e-10 -5.293556734921e-02 
+ 9.028000000000e-10  1.127840525322e-01 
+ 9.128000000000e-10  2.835604325687e-01 
+ 9.228000000000e-10  4.380556116504e-01 
+ 9.328000000000e-10  5.301928903803e-01 
+ 9.428000000000e-10  5.243535525106e-01 
+ 9.528000000000e-10  4.298886927263e-01 
+ 9.628000000000e-10  2.850186727532e-01 
+ 9.728000000000e-10  1.263001165080e-01 
+ 9.828000000000e-10 -3.646027271135e-02 
+ 9.928000000000e-10 -2.059993087376e-01 
+ 1.000000000000e-09 -3.287656823991e-01 
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_divider.sym b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_divider.sym
new file mode 100644
index 00000000..e46eb233
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/CML_divider.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 100 -20 120 -20 {}
+L 4 100 20 120 20 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -122.5 -22.5 -117.5 -17.5 {name=Vo+ dir=out}
+B 5 -122.5 17.5 -117.5 22.5 {name=Vo- dir=out}
+B 5 117.5 -22.5 122.5 -17.5 {name=Vi+ dir=in}
+B 5 117.5 17.5 122.5 22.5 {name=Vi- dir=in}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout}
+B 5 -2.5 57.5 2.5 62.5 {name=gnd dir=inout}
+P 4 5 100 -40 -100 -40 -100 40 100 40 100 -40 {}
+T {@symname} -44 -6 0 0 0.3 0.3 {}
+T {@name} 45 -52 0 0 0.2 0.2 {}
+T {Vo+} -95 -24 0 0 0.2 0.2 {}
+T {Vo-} -95 16 0 0 0.2 0.2 {}
+T {Vi+} 95 -16 2 0 0.2 0.2 {}
+T {Vi-} 95 24 2 0 0.2 0.2 {}
+T {vdd} 10 -39 0 1 0.2 0.2 {}
+T {gnd} -10 34 2 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/conditions.yaml
new file mode 100644
index 00000000..dc34a5cc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/xschem/simulations/schematic/CML_divider.spice
+N: 26
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: CML_core_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/run_26
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/simulation_summary.csv b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/simulation_summary.csv
new file mode 100644
index 00000000..b3ff8851
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/simulation_summary.csv
@@ -0,0 +1,28 @@
+run,corner,temperature,vdd,time,vo_diff,frequency,amplitude,voltage_swing
+run_00,tt,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.417, 0.566, 0.643, …]",5.902e+09,0.652,1.304
+run_01,ff,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.388, 0.541, 0.624, …]",5.902e+09,0.636,1.273
+run_02,ss,-40,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.437, 0.584, 0.658, …]",5.902e+09,0.666,1.331
+run_03,tt,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.379, 0.531, 0.612, …]",5.902e+09,0.623,1.246
+run_04,ff,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.353, 0.507, 0.592, …]",5.902e+09,0.606,1.211
+run_05,ss,27,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.390, 0.545, 0.627, …]",5.902e+09,0.638,1.277
+run_06,tt,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.327, 0.482, 0.573, …]",5.902e+09,0.591,1.182
+run_07,ff,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.305, 0.459, 0.552, …]",5.902e+09,0.573,1.145
+run_08,ss,80,0.8,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.333, 0.492, 0.587, …]",5.902e+09,0.609,1.217
+run_09,tt,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.567, 0.586, 0.501, …]",5.902e+09,0.592,1.184
+run_10,ff,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.543, 0.589, 0.533, …]",5.902e+09,0.589,1.178
+run_11,ss,-40,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.583, 0.581, 0.475, …]",5.902e+09,0.592,1.183
+run_12,tt,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.556, 0.565, 0.480, …]",5.902e+09,0.574,1.148
+run_13,ff,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.537, 0.567, 0.503, …]",5.902e+09,0.568,1.136
+run_14,ss,27,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.569, 0.568, 0.470, …]",5.902e+09,0.582,1.163
+run_15,tt,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.534, 0.545, 0.467, …]",5.902e+09,0.553,1.105
+run_16,ff,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.518, 0.543, 0.480, …]",5.902e+09,0.544,1.089
+run_17,ss,80,1.2,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[0.546, 0.554, 0.470, …]",5.902e+09,0.564,1.127
+run_18,tt,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.311e-01, -5.593e-01, -4.797e-01, …]",5.902e+09,0.563,1.127
+run_19,ff,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.156e-01, -5.591e-01, -4.970e-01, …]",5.902e+09,0.562,1.124
+run_20,ss,-40,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.458e-01, -5.643e-01, -4.724e-01, …]",5.902e+09,0.572,1.144
+run_21,tt,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.968e-01, -5.441e-01, -4.869e-01, …]",5.902e+09,0.547,1.094
+run_22,ff,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.848e-01, -5.392e-01, -4.922e-01, …]",5.902e+09,0.544,1.087
+run_23,ss,27,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-5.032e-01, -5.559e-01, -4.999e-01, …]",5.902e+09,0.558,1.116
+run_24,tt,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.328e-01, -5.105e-01, -4.919e-01, …]",5.902e+09,0.527,1.054
+run_25,ff,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.235e-01, -5.023e-01, -4.882e-01, …]",5.902e+09,0.520,1.041
+run_26,ss,80,1.6,"[1.628e-10, 1.728e-10, 1.828e-10, …]","[-4.324e-01, -5.218e-01, -5.130e-01, …]",5.902e+09,0.539,1.078
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/simulation_summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/simulation_summary.md
new file mode 100644
index 00000000..eb3c339b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/simulation_summary.md
@@ -0,0 +1,31 @@
+# Simulation Summary for CML divider frequency response
+
+| run | corner | temperature | vdd | time | vo_diff | frequency | amplitude | voltage_swing |
+| :-- | -----: | ----------: | --: | ---: | ------: | --------: | --------: | ------------: |
+| run_00 | tt | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.417, 0.566, 0.643, …] | 5.902e+09 | 0.652 | 1.304 |
+| run_01 | ff | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.388, 0.541, 0.624, …] | 5.902e+09 | 0.636 | 1.273 |
+| run_02 | ss | -40 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.437, 0.584, 0.658, …] | 5.902e+09 | 0.666 | 1.331 |
+| run_03 | tt | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.379, 0.531, 0.612, …] | 5.902e+09 | 0.623 | 1.246 |
+| run_04 | ff | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.353, 0.507, 0.592, …] | 5.902e+09 | 0.606 | 1.211 |
+| run_05 | ss | 27 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.390, 0.545, 0.627, …] | 5.902e+09 | 0.638 | 1.277 |
+| run_06 | tt | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.327, 0.482, 0.573, …] | 5.902e+09 | 0.591 | 1.182 |
+| run_07 | ff | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.305, 0.459, 0.552, …] | 5.902e+09 | 0.573 | 1.145 |
+| run_08 | ss | 80 | 0.8 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.333, 0.492, 0.587, …] | 5.902e+09 | 0.609 | 1.217 |
+| run_09 | tt | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.567, 0.586, 0.501, …] | 5.902e+09 | 0.592 | 1.184 |
+| run_10 | ff | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.543, 0.589, 0.533, …] | 5.902e+09 | 0.589 | 1.178 |
+| run_11 | ss | -40 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.583, 0.581, 0.475, …] | 5.902e+09 | 0.592 | 1.183 |
+| run_12 | tt | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.556, 0.565, 0.480, …] | 5.902e+09 | 0.574 | 1.148 |
+| run_13 | ff | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.537, 0.567, 0.503, …] | 5.902e+09 | 0.568 | 1.136 |
+| run_14 | ss | 27 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.569, 0.568, 0.470, …] | 5.902e+09 | 0.582 | 1.163 |
+| run_15 | tt | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.534, 0.545, 0.467, …] | 5.902e+09 | 0.553 | 1.105 |
+| run_16 | ff | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.518, 0.543, 0.480, …] | 5.902e+09 | 0.544 | 1.089 |
+| run_17 | ss | 80 | 1.2 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [0.546, 0.554, 0.470, …] | 5.902e+09 | 0.564 | 1.127 |
+| run_18 | tt | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.311e-01, -5.593e-01, -4.797e-01, …] | 5.902e+09 | 0.563 | 1.127 |
+| run_19 | ff | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.156e-01, -5.591e-01, -4.970e-01, …] | 5.902e+09 | 0.562 | 1.124 |
+| run_20 | ss | -40 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.458e-01, -5.643e-01, -4.724e-01, …] | 5.902e+09 | 0.572 | 1.144 |
+| run_21 | tt | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.968e-01, -5.441e-01, -4.869e-01, …] | 5.902e+09 | 0.547 | 1.094 |
+| run_22 | ff | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.848e-01, -5.392e-01, -4.922e-01, …] | 5.902e+09 | 0.544 | 1.087 |
+| run_23 | ss | 27 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-5.032e-01, -5.559e-01, -4.999e-01, …] | 5.902e+09 | 0.558 | 1.116 |
+| run_24 | tt | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.328e-01, -5.105e-01, -4.919e-01, …] | 5.902e+09 | 0.527 | 1.054 |
+| run_25 | ff | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.235e-01, -5.023e-01, -4.882e-01, …] | 5.902e+09 | 0.520 | 1.041 |
+| run_26 | ss | 80 | 1.6 | [1.628e-10, 1.728e-10, 1.828e-10, …] | [-4.324e-01, -5.218e-01, -5.130e-01, …] | 5.902e+09 | 0.539 | 1.078 |
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/vo_diff_vs_time.png
new file mode 100644
index 00000000..926b1f5c
Binary files /dev/null and b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/parameters/ac_params/vo_diff_vs_time.png differ
diff --git a/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/summary.md b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/summary.md
new file mode 100644
index 00000000..10bb6ebe
--- /dev/null
+++ b/modules/module_4_type_2_PLL/CML_divider/runs/RUN_2025-11-17_08-43-29/summary.md
@@ -0,0 +1,11 @@
+
+# CACE Summary for CML_divider
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |  5.902 GHz |      5.0 GHz |  5.902 GHz |      5.2 GHz |  5.902 GHz |   Fail ❌    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |    0.520 V |        0.4 V |    0.573 V |        0.6 V |    0.666 V |   Fail ❌    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |    1.041 V |        0.8 V |    1.145 V |        1.2 V |    1.331 V |   Fail ❌    |
+
diff --git a/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch b/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch
index 0fc8ac25..52af1de9 100644
--- a/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch
+++ b/modules/module_4_type_2_PLL/CML_divider/testbench/CML_core_tb.sch
@@ -1,19 +1,20 @@
-v {xschem version=3.4.6 file_version=1.2}
+v {xschem version=3.4.8RC file_version=1.3}
 G {}
 K {}
 V {}
 S {}
+F {}
 E {}
 B 2 1110 -700 1910 -300 {flags=graph
-y1=0.72
-y2=1.2
+y1=0.29
+y2=1.1
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=2.9974739e-10
-x2=5.9578291e-10
+x1=1.628e-10
+x2=1e-09
 divx=5
 subdivx=1
 xlabmag=1.0
@@ -26,15 +27,15 @@ color="4 7"
 node="vo_m
 vo_p"}
 B 2 1110 -1120 1910 -720 {flags=graph
-y1=0.17956962
-y2=0.4801486
+y1=0.3
+y2=0.9
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=2.9974739e-10
-x2=5.9578291e-10
+x1=1.628e-10
+x2=1e-09
 divx=5
 subdivx=1
 xlabmag=1.0
@@ -48,15 +49,15 @@ node="vinplus
 vinminus"
 }
 B 2 1930 -1120 2730 -720 {flags=graph
-y1=-0.41
-y2=0.41
+y1=-0.79
+y2=0.79
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=2.9974739e-10
-x2=5.9578291e-10
+x1=1.628e-10
+x2=1e-09
 divx=5
 subdivx=1
 xlabmag=1.0
@@ -83,7 +84,7 @@ C {code_shown.sym} 10 -1150 0 0 {name=transient_tb only_toplevel=false
 value="
 .include CML_core_tb.save
 .param temp=100
-.param A = 0.3
+.param A = 0
 .ic V(Voplus)=1.2
 .control
 set noaskquit
diff --git a/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch b/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch
index ad08aabc..30f06097 100644
--- a/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch
+++ b/modules/module_4_type_2_PLL/CML_divider/xschem/CML_divider.sch
@@ -1,8 +1,9 @@
-v {xschem version=3.4.6 file_version=1.2}
+v {xschem version=3.4.8RC file_version=1.3}
 G {}
 K {}
 V {}
 S {}
+F {}
 E {}
 N 310 -500 310 -440 {lab=#net1}
 N 420 -440 530 -440 {lab=#net1}
@@ -135,7 +136,7 @@ m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
-C {isource.sym} 730 -250 0 0 {name=I0 value=200u}
+C {isource.sym} 730 -250 0 0 {name=I0 value=400u}
 C {sg13g2_pr/sg13_lv_nmos.sym} 1060 -380 0 1 {name=M4
 l=0.2u
 w=2u
@@ -210,7 +211,7 @@ m=1
 model=sg13_lv_nmos
 spiceprefix=X
 }
-C {isource.sym} 1690 -250 0 0 {name=I1 value=200u}
+C {isource.sym} 1690 -250 0 0 {name=I1 value=400u}
 C {sg13g2_pr/sg13_lv_nmos.sym} 2020 -380 0 1 {name=M10
 l=0.2u
 w=2u
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/cace/LC_Oscillator.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/cace/LC_Oscillator.yaml
new file mode 100644
index 00000000..cd625789
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/cace/LC_Oscillator.yaml
@@ -0,0 +1,115 @@
+#--------------------------------------------------------------
+# CACE circuit characterization file
+#--------------------------------------------------------------
+
+name:           LC_Oscillator
+description:    LC based voltage controlled oscillator
+PDK:            ihp-sg13g2
+
+cace_format:    5.2
+
+authorship:
+  designer: Phillip F. Baade-Pedersen      
+  company: IHP
+  creation_date:    
+  license:          Apache 2.0
+
+paths:
+  root:             ..
+  schematic:        xschem/
+  netlist:          xschem/simulations
+  documentation:    docs
+
+pins:
+  VDD:
+    description: Positive analog power supply
+    type: power
+    direction: inout
+    Vmin: 0.8
+    Vmax: 1.6
+  Vinplus:
+    description: Positive Input
+    type: signal
+    direction: input
+  Vinminus:
+    description: Negative Input
+    type: signal
+    direction: input
+  
+default_conditions:
+  vdd:
+    description: Analog power supply voltage
+    display: Vdd
+    unit: V
+    typical: 1.2
+  corner:
+    description: Process corner
+    display: Corner
+    typical: tt
+  temperature:
+    description: Ambient temperature
+    display: Temp
+    unit: °C
+    typical: 27
+
+parameters:
+  ac_params:
+    description: Frequency characterization of the LC-VCO
+    display: VCO Control Voltage Repsonse
+    spec:
+      frequency:
+        display: Frequency
+        description: Output frequency of the VCO
+        unit: GHz
+        minimum:
+          value: 4.3
+        typical:
+          value: 5.0
+        maximum:
+          value: 5.2
+      amplitude:
+        display: Amplitude
+        description: Differential output amplitude (half swing)
+        unit: V
+        minimum:
+          value: 0.2
+        typical:
+          value: 0.4
+        maximum:
+          value: 0.6
+      voltage_swing:
+        display: Voltage swing
+        description: Differential peak-to-peak output swing
+        unit: V
+        minimum:
+          value: 0.4
+        typical:
+          value: 0.8
+        maximum:
+          value: 1.2
+    tool:
+      ngspice:
+        template: LC_Oscillator_tb.sch
+        format: ascii
+        suffix: .data
+        variables: [time, vo_diff]
+        script: freq.py
+        script_variables: [frequency, amplitude, voltage_swing]
+    plot:
+      vo_diff_vs_time:
+        type: xyplot
+        xaxis: time
+        yaxis: vo_diff
+    conditions:
+      vdd:
+        minimum: 0.8
+        typical: 1.2
+        maximum: 1.6
+      corner:
+        enumerate: [tt, ff, ss]
+      temperature:
+        minimum: -40
+        typical: 27
+        maximum: 80
+      
+   
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/cace/scripts/__pycache__/freq.cpython-310.pyc b/modules/module_4_type_2_PLL/LC_Oscillator/cace/scripts/__pycache__/freq.cpython-310.pyc
new file mode 100644
index 00000000..6523f1ed
Binary files /dev/null and b/modules/module_4_type_2_PLL/LC_Oscillator/cace/scripts/__pycache__/freq.cpython-310.pyc differ
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/cace/scripts/freq.py b/modules/module_4_type_2_PLL/LC_Oscillator/cace/scripts/freq.py
new file mode 100644
index 00000000..3c457ffe
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/cace/scripts/freq.py
@@ -0,0 +1,41 @@
+from typing import Any
+import numpy as np
+
+def postprocess(results: dict[str, list], conditions: dict[str, Any]) -> dict[str, list]:
+    # Extract waveform
+    t = np.array(results['time'])
+    v = np.array(results['vo_diff'])
+
+    if len(t) < 2 or len(v) == 0:
+        return {
+            'frequency': [0.0],
+            'amplitude': [0.0],
+            'voltage_swing': [0.0]
+        }
+
+    # --- Compute sampling frequency ---
+    dt = np.mean(np.diff(t))
+    fs = 1.0 / dt
+
+    # --- FFT to find main tone ---
+    Y = np.fft.fft(v - np.mean(v))  # remove DC
+    freqs = np.fft.fftfreq(len(Y), d=dt)
+
+    # Use positive frequencies only
+    mask = freqs > 0
+    freqs = freqs[mask]
+    Y = np.abs(Y[mask])
+
+    freq_peak = freqs[np.argmax(Y)]
+
+    # --- Compute amplitude and voltage swing ---
+    v_max = np.max(v)
+    v_min = np.min(v)
+    voltage_swing = v_max - v_min
+    amplitude = voltage_swing / 2.0
+
+    return {
+        'frequency': [freq_peak],
+        'amplitude': [amplitude],
+        'voltage_swing': [voltage_swing]
+    }
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/cace/templates/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/cace/templates/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..adca2361
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/cace/templates/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/cace/templates/xschemrc b/modules/module_4_type_2_PLL/LC_Oscillator/cace/templates/xschemrc
new file mode 100644
index 00000000..36e35c71
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/cace/templates/xschemrc
@@ -0,0 +1 @@
+source [file dirname [info script]]/../../xschem/xschemrc
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider.md b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider.md
new file mode 100644
index 00000000..06216088
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider.md
@@ -0,0 +1,54 @@
+# CML_divider
+
+- Description: Current mode logic divider
+- PDK: ihp-sg13g2
+
+## Authorship
+
+- Designer: Phillip F. Baade-Pedersen
+- Company: IHP
+- Created: None
+- License: Apache 2.0
+- Last modified: None
+
+## Pins
+
+- VDD
+  + Description: Positive analog power supply
+  + Type: power
+  + Direction: inout
+  + Vmin: 0.8
+  + Vmax: 1.6
+- Vinplus
+  + Description: Positive Input
+  + Type: signal
+  + Direction: input
+- Vinminus
+  + Description: Negative Input
+  + Type: signal
+  + Direction: input
+
+## Default Conditions
+
+- vdd
+  + Description: Analog power supply voltage
+  + Display: Vdd
+  + Unit: V
+  + Typical: 1.2
+- corner
+  + Description: Process corner
+  + Display: Corner
+  + Typical: tt
+- temperature
+  + Description: Ambient temperature
+  + Display: Temp
+  + Unit: °C
+  + Typical: 27
+
+## Symbol
+
+![Symbol of CML_divider](CML_divider_symbol.svg)
+
+## Schematic
+
+![Schematic of CML_divider](CML_divider_schematic.svg)
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider/schematic/frequency.png b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider/schematic/frequency.png
new file mode 100644
index 00000000..e4b0a21a
Binary files /dev/null and b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider/schematic/frequency.png differ
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider/schematic/vo_diff_vs_time.png b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider/schematic/vo_diff_vs_time.png
new file mode 100644
index 00000000..b3049fae
Binary files /dev/null and b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider/schematic/vo_diff_vs_time.png differ
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_schematic.md b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_schematic.md
new file mode 100644
index 00000000..51ae9078
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_schematic.md
@@ -0,0 +1,17 @@
+
+# CACE Summary for CML_divider
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |  4.722 GHz |      5.0 GHz |  4.722 GHz |      5.2 GHz |  4.722 GHz |   Pass ✅    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |    0.315 V |        0.4 V |    0.382 V |        0.6 V |    0.429 V |   Pass ✅    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |    0.629 V |        0.8 V |    0.763 V |        1.2 V |    0.857 V |   Pass ✅    |
+
+
+## Plots
+
+## vo_diff_vs_time
+
+![vo_diff_vs_time](./CML_divider/schematic/vo_diff_vs_time.png)
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_schematic.svg b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_schematic.svg
new file mode 100644
index 00000000..5de9a6fa
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_schematic.svg
@@ -0,0 +1,160 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="1000" height="700" version="1.1">
+<style type="text/css">
+.l0{
+  fill: #000000;
+  stroke: #000000;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l1{
+  fill: #00ccee;
+  stroke: #00ccee;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l2{
+  fill: #4f4f4f; fill-opacity: 0.2;
+  stroke: #4f4f4f;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l3{
+  fill: #cccccc; fill-opacity: 0.5;
+  stroke: #cccccc;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l4{
+  fill: #88dd00;
+  stroke: #88dd00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l5{
+  fill: #bb2200;
+  stroke: #bb2200;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l6{
+  fill: #00ccee; fill-opacity: 0.5;
+  stroke: #00ccee;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l7{
+  fill: #ff0000; fill-opacity: 0.5;
+  stroke: #ff0000;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l8{
+  fill: #ffff00; fill-opacity: 0.5;
+  stroke: #ffff00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l9{
+  fill: #ffffff; fill-opacity: 0.5;
+  stroke: #ffffff;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l10{
+  fill: #ff00ff;
+  stroke: #ff00ff;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l11{
+  fill: #00ff00; fill-opacity: 0.5;
+  stroke: #00ff00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l12{
+  fill: #0000ff; fill-opacity: 0.5;
+  stroke: #0000ff;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l13{
+  fill: #aaaa00; fill-opacity: 0.5;
+  stroke: #aaaa00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l14{
+  fill: #aaccaa; fill-opacity: 0.2;
+  stroke: #aaccaa;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l15{
+  fill: #ff7777; fill-opacity: 0.5;
+  stroke: #ff7777;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l16{
+  fill: #bfff81; fill-opacity: 0.5;
+  stroke: #bfff81;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l17{
+  fill: #00ffcc; fill-opacity: 0.2;
+  stroke: #00ffcc;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l18{
+  fill: #ce0097; fill-opacity: 0.5;
+  stroke: #ce0097;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l19{
+  fill: #d2d46b; fill-opacity: 0.2;
+  stroke: #d2d46b;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l20{
+  fill: #ef6158; fill-opacity: 0.2;
+  stroke: #ef6158;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l21{
+  fill: #fdb200; fill-opacity: 0.2;
+  stroke: #fdb200;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+text {font-family: Sans-Serif;}
+</style>
+<rect class="l0" x="0" y="0" width="1000" height="700"/>
+</svg>
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_symbol.svg b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_symbol.svg
new file mode 100644
index 00000000..5de9a6fa
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/docs/CML_divider_symbol.svg
@@ -0,0 +1,160 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" width="1000" height="700" version="1.1">
+<style type="text/css">
+.l0{
+  fill: #000000;
+  stroke: #000000;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l1{
+  fill: #00ccee;
+  stroke: #00ccee;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l2{
+  fill: #4f4f4f; fill-opacity: 0.2;
+  stroke: #4f4f4f;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l3{
+  fill: #cccccc; fill-opacity: 0.5;
+  stroke: #cccccc;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l4{
+  fill: #88dd00;
+  stroke: #88dd00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l5{
+  fill: #bb2200;
+  stroke: #bb2200;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l6{
+  fill: #00ccee; fill-opacity: 0.5;
+  stroke: #00ccee;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l7{
+  fill: #ff0000; fill-opacity: 0.5;
+  stroke: #ff0000;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l8{
+  fill: #ffff00; fill-opacity: 0.5;
+  stroke: #ffff00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l9{
+  fill: #ffffff; fill-opacity: 0.5;
+  stroke: #ffffff;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l10{
+  fill: #ff00ff;
+  stroke: #ff00ff;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l11{
+  fill: #00ff00; fill-opacity: 0.5;
+  stroke: #00ff00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l12{
+  fill: #0000ff; fill-opacity: 0.5;
+  stroke: #0000ff;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l13{
+  fill: #aaaa00; fill-opacity: 0.5;
+  stroke: #aaaa00;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l14{
+  fill: #aaccaa; fill-opacity: 0.2;
+  stroke: #aaccaa;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l15{
+  fill: #ff7777; fill-opacity: 0.5;
+  stroke: #ff7777;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l16{
+  fill: #bfff81; fill-opacity: 0.5;
+  stroke: #bfff81;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l17{
+  fill: #00ffcc; fill-opacity: 0.2;
+  stroke: #00ffcc;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l18{
+  fill: #ce0097; fill-opacity: 0.5;
+  stroke: #ce0097;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l19{
+  fill: #d2d46b; fill-opacity: 0.2;
+  stroke: #d2d46b;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l20{
+  fill: #ef6158; fill-opacity: 0.2;
+  stroke: #ef6158;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+.l21{
+  fill: #fdb200; fill-opacity: 0.2;
+  stroke: #fdb200;
+  stroke-linecap:round;
+  stroke-linejoin:round;
+  stroke-width: 3.6666;
+}
+text {font-family: Sans-Serif;}
+</style>
+<rect class="l0" x="0" y="0" width="1000" height="700"/>
+</svg>
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/LC VCO.md b/modules/module_4_type_2_PLL/LC_Oscillator/docs/LC VCO.md
new file mode 100644
index 00000000..66d1484a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/docs/LC VCO.md	
@@ -0,0 +1,54 @@
+# LC VCO
+
+- Description: LC based voltage controlled oscillator
+- PDK: ihp-sg13g2
+
+## Authorship
+
+- Designer: Phillip F. Baade-Pedersen
+- Company: IHP
+- Created: None
+- License: Apache 2.0
+- Last modified: None
+
+## Pins
+
+- VDD
+  + Description: Positive analog power supply
+  + Type: power
+  + Direction: inout
+  + Vmin: 0.8
+  + Vmax: 1.6
+- Vinplus
+  + Description: Positive Input
+  + Type: signal
+  + Direction: input
+- Vinminus
+  + Description: Negative Input
+  + Type: signal
+  + Direction: input
+
+## Default Conditions
+
+- vdd
+  + Description: Analog power supply voltage
+  + Display: Vdd
+  + Unit: V
+  + Typical: 1.2
+- corner
+  + Description: Process corner
+  + Display: Corner
+  + Typical: tt
+- temperature
+  + Description: Ambient temperature
+  + Display: Temp
+  + Unit: °C
+  + Typical: 27
+
+## Symbol
+
+![Symbol of LC VCO](LC VCO_symbol.svg)
+
+## Schematic
+
+![Schematic of LC VCO](LC VCO_schematic.svg)
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/docs/LC VCO_schematic.md b/modules/module_4_type_2_PLL/LC_Oscillator/docs/LC VCO_schematic.md
new file mode 100644
index 00000000..0ab01435
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/docs/LC VCO_schematic.md	
@@ -0,0 +1,13 @@
+
+# CACE Summary for LC VCO
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |          ​ |      5.0 GHz |          ​ |      5.2 GHz |          ​ |   Skip 🟧    |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |          ​ |        0.4 V |          ​ |        0.6 V |          ​ |   Skip 🟧    |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |          ​ |        0.8 V |          ​ |        1.2 V |          ​ |   Skip 🟧    |
+
+
+## Plots
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..adca2361
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata CACE\{simpath\}/CACE\{filename\}_CACE\{N\}.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=CACE\{vdd\} savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib CACE\{PDK_ROOT\}/CACE\{PDK\}/libs.tech/ngspice/models/cornerMOSlv.lib mos_CACE\{corner\}
+
+.include CACE\{DUT_path\}
+
+.temp CACE\{temperature\}
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..f2c9ddb3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/LC_Oscillator_tb_0.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/conditions.yaml
new file mode 100644
index 00000000..367b2deb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 0
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_00
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..99a2d4a7
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb_1.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb_1.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb_1.data
new file mode 100644
index 00000000..4770777e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/LC_Oscillator_tb_1.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  8.565847765148e-03 
+ 1.728000000000e-10 -6.623891474136e-03 
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+ 9.222800000000e-09 -2.441554104755e-01 
+ 9.232800000000e-09 -3.802685152522e-01 
+ 9.242800000000e-09 -4.595254273568e-01 
+ 9.252800000000e-09 -4.708980436339e-01 
+ 9.262800000000e-09 -4.163426325433e-01 
+ 9.272800000000e-09 -3.066233790089e-01 
+ 9.282800000000e-09 -1.582287590700e-01 
+ 9.292800000000e-09  1.204158483739e-02 
+ 9.302800000000e-09  1.854755615929e-01 
+ 9.312800000000e-09  3.365187856105e-01 
+ 9.322800000000e-09  4.384121015246e-01 
+ 9.332800000000e-09  4.746325438472e-01 
+ 9.342800000000e-09  4.430438328376e-01 
+ 9.352800000000e-09  3.516554423001e-01 
+ 9.362800000000e-09  2.152473815735e-01 
+ 9.372800000000e-09  5.101666211968e-02 
+ 9.382800000000e-09 -1.239088110897e-01 
+ 9.392800000000e-09 -2.862898538942e-01 
+ 9.402800000000e-09 -4.086283865924e-01 
+ 9.412800000000e-09 -4.695453664284e-01 
+ 9.422800000000e-09 -4.620727802601e-01 
+ 9.432800000000e-09 -3.908572400200e-01 
+ 9.442800000000e-09 -2.686111439183e-01 
+ 9.452800000000e-09 -1.125381264041e-01 
+ 9.462800000000e-09  6.079870306913e-02 
+ 9.472800000000e-09  2.308216899808e-01 
+ 9.482800000000e-09  3.707015176506e-01 
+ 9.492800000000e-09  4.553681422057e-01 
+ 9.502800000000e-09  4.725064407028e-01 
+ 9.512800000000e-09  4.231763569955e-01 
+ 9.522800000000e-09  3.175166157190e-01 
+ 9.532800000000e-09  1.717013832461e-01 
+ 9.542800000000e-09  2.657335955213e-03 
+ 9.552800000000e-09 -1.713870925589e-01 
+ 9.562800000000e-09 -3.253654144422e-01 
+ 9.572800000000e-09 -4.322097206151e-01 
+ 9.582800000000e-09 -4.741848054597e-01 
+ 9.592800000000e-09 -4.481034122689e-01 
+ 9.602800000000e-09 -3.612331987207e-01 
+ 9.612800000000e-09 -2.279096366069e-01 
+ 9.622800000000e-09 -6.541185777728e-02 
+ 9.632800000000e-09  1.093725922642e-01 
+ 9.642800000000e-09  2.738177273356e-01 
+ 9.652800000000e-09  4.004725473997e-01 
+ 9.662800000000e-09  4.670119955316e-01 
+ 9.672800000000e-09  4.652431338827e-01 
+ 9.682800000000e-09  3.989630884507e-01 
+ 9.692800000000e-09  2.803492903980e-01 
+ 9.702800000000e-09  1.264668581205e-01 
+ 9.712800000000e-09 -4.609901262979e-02 
+ 9.722800000000e-09 -2.173662583407e-01 
+ 9.732800000000e-09 -3.608299222224e-01 
+ 9.742800000000e-09 -4.508055807148e-01 
+ 9.752800000000e-09 -4.736936144943e-01 
+ 9.762800000000e-09 -4.296319777317e-01 
+ 9.772800000000e-09 -3.282621309804e-01 
+ 9.782800000000e-09 -1.852727462566e-01 
+ 9.792800000000e-09 -1.751785697417e-02 
+ 9.802800000000e-09  1.570670899042e-01 
+ 9.812800000000e-09  3.139061628357e-01 
+ 9.822800000000e-09  4.256911863098e-01 
+ 9.832800000000e-09  4.734981197836e-01 
+ 9.842800000000e-09  4.530355607929e-01 
+ 9.852800000000e-09  3.708008431751e-01 
+ 9.862800000000e-09  2.406649872183e-01 
+ 9.872800000000e-09  7.995256048710e-02 
+ 9.882800000000e-09 -9.461609584678e-02 
+ 9.892800000000e-09 -2.610384551620e-01 
+ 9.902800000000e-09 -3.919661505565e-01 
+ 9.912800000000e-09 -4.641867401380e-01 
+ 9.922800000000e-09 -4.682314424888e-01 
+ 9.932800000000e-09 -4.070067908672e-01 
+ 9.942800000000e-09 -2.921347567102e-01 
+ 9.952800000000e-09 -1.405043945224e-01 
+ 9.962800000000e-09  3.122434420400e-02 
+ 9.972800000000e-09  2.036393764277e-01 
+ 9.982800000000e-09  3.506070576859e-01 
+ 9.992800000000e-09  4.458981402800e-01 
+ 1.000000000000e-08  4.734856603609e-01 
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/conditions.yaml
new file mode 100644
index 00000000..a047ec8a
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 1
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_01
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..37f086ac
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/LC_Oscillator_tb_2.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/conditions.yaml
new file mode 100644
index 00000000..f01f6d74
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 2
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_02
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..24f72f1e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/LC_Oscillator_tb_3.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/conditions.yaml
new file mode 100644
index 00000000..b514bdcd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 3
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_03
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..fe098a0e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb_4.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb_4.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb_4.data
new file mode 100644
index 00000000..19009f58
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/LC_Oscillator_tb_4.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  8.921994627659e-03 
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diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/conditions.yaml
new file mode 100644
index 00000000..3f88ef7f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 4
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_04
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..5ce5e08c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/LC_Oscillator_tb_5.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/conditions.yaml
new file mode 100644
index 00000000..4b006409
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 5
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_05
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..c846cb86
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/LC_Oscillator_tb_6.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/conditions.yaml
new file mode 100644
index 00000000..32678e67
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 6
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_06
+temperature: '-40'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..21baf117
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb_7.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb_7.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb_7.data
new file mode 100644
index 00000000..ad238f94
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/LC_Oscillator_tb_7.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  8.466139813278e-03 
+ 1.728000000000e-10 -6.989764545663e-03 
+ 1.828000000000e-10 -2.211384336733e-02 
+ 1.928000000000e-10 -3.476199246532e-02 
+ 2.028000000000e-10 -4.304137789423e-02 
+ 2.128000000000e-10 -4.559970872536e-02 
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diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/conditions.yaml
new file mode 100644
index 00000000..f677d6cc
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 7
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_07
+temperature: '-40'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..61381427
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/LC_Oscillator_tb_8.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp -40
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/conditions.yaml
new file mode 100644
index 00000000..35f59447
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 8
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_08
+temperature: '-40'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..127bee86
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/LC_Oscillator_tb_9.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/conditions.yaml
new file mode 100644
index 00000000..7574932f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 9
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_09
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..286e4f0c
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb_10.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb_10.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb_10.data
new file mode 100644
index 00000000..b7f86069
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/LC_Oscillator_tb_10.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  7.784089647675e-03 
+ 1.728000000000e-10 -6.659867527503e-03 
+ 1.828000000000e-10 -2.065836564882e-02 
+ 1.928000000000e-10 -3.223183497866e-02 
+ 2.028000000000e-10 -3.967063809564e-02 
+ 2.128000000000e-10 -4.179084703358e-02 
+ 2.228000000000e-10 -3.812078754614e-02 
+ 2.328000000000e-10 -2.898703649634e-02 
+ 2.428000000000e-10 -1.548756892133e-02 
+ 2.528000000000e-10  6.375687295537e-04 
+ 2.628000000000e-10  1.722177212335e-02 
+ 2.728000000000e-10  3.195248709933e-02 
+ 2.828000000000e-10  4.269136137453e-02 
+ 2.928000000000e-10  4.779016992350e-02 
+ 3.028000000000e-10  4.634832244203e-02 
+ 3.128000000000e-10  3.836165802964e-02 
+ 3.228000000000e-10  2.474052176555e-02 
+ 3.328000000000e-10  7.202795888793e-03 
+ 3.428000000000e-10 -1.193518862712e-02 
+ 3.528000000000e-10 -3.004917466656e-02 
+ 3.628000000000e-10 -4.455651087068e-02 
+ 3.728000000000e-10 -5.328857165539e-02 
+ 3.828000000000e-10 -5.482486386471e-02 
+ 3.928000000000e-10 -4.872252714300e-02 
+ 4.028000000000e-10 -3.559778133135e-02 
+ 4.128000000000e-10 -1.705752539469e-02 
+ 4.228000000000e-10  4.494514684145e-03 
+ 4.328000000000e-10  2.614990918727e-02 
+ 4.428000000000e-10  4.486858984942e-02 
+ 4.528000000000e-10  5.790499680702e-02 
+ 4.628000000000e-10  6.322761536228e-02 
+ 4.728000000000e-10  5.984554126646e-02 
+ 4.828000000000e-10  4.797198577690e-02 
+ 4.928000000000e-10  2.900503894818e-02 
+ 5.028000000000e-10  5.354576688624e-03 
+ 5.128000000000e-10 -1.984566286256e-02 
+ 5.228000000000e-10 -4.312025347072e-02 
+ 5.328000000000e-10 -6.111668946312e-02 
+ 5.428000000000e-10 -7.110590788686e-02 
+ 5.528000000000e-10 -7.142203495109e-02 
+ 5.628000000000e-10 -6.173530049101e-02 
+ 5.728000000000e-10 -4.310134196595e-02 
+ 5.828000000000e-10 -1.783859548906e-02 
+ 5.928000000000e-10  1.075961503623e-02 
+ 6.028000000000e-10  3.882583046492e-02 
+ 6.128000000000e-10  6.238623562187e-02 
+ 6.228000000000e-10  7.793696325367e-02 
+ 6.328000000000e-10  8.301116327128e-02 
+ 6.428000000000e-10  7.658901562543e-02 
+ 6.528000000000e-10  5.925537503877e-02 
+ 6.628000000000e-10  3.310547039510e-02 
+ 6.728000000000e-10  1.475565202656e-03 
+ 6.828000000000e-10 -3.143628246095e-02 
+ 6.928000000000e-10 -6.105869531550e-02 
+ 7.028000000000e-10 -8.306545944817e-02 
+ 7.128000000000e-10 -9.406086743390e-02 
+ 7.228000000000e-10 -9.216062921479e-02 
+ 7.328000000000e-10 -7.729185188302e-02 
+ 7.428000000000e-10 -5.118768714920e-02 
+ 7.528000000000e-10 -1.712523584952e-02 
+ 7.628000000000e-10  2.047047781981e-02 
+ 7.728000000000e-10  5.648855402944e-02 
+ 7.828000000000e-10  8.574056972983e-02 
+ 7.928000000000e-10  1.038101477910e-01 
+ 8.028000000000e-10  1.078060471304e-01 
+ 8.128000000000e-10  9.679553692925e-02 
+ 8.228000000000e-10  7.195903105367e-02 
+ 8.328000000000e-10  3.636541105657e-02 
+ 8.428000000000e-10 -5.463976843783e-03 
+ 8.528000000000e-10 -4.794552017313e-02 
+ 8.628000000000e-10 -8.510161379414e-02 
+ 8.728000000000e-10 -1.114516353823e-01 
+ 8.828000000000e-10 -1.228469522842e-01 
+ 8.928000000000e-10 -1.172662109428e-01 
+ 9.028000000000e-10 -9.514637917753e-02 
+ 9.128000000000e-10 -5.918133055417e-02 
+ 9.228000000000e-10 -1.385862264427e-02 
+ 9.328000000000e-10  3.491713431321e-02 
+ 9.428000000000e-10  8.039772010753e-02 
+ 9.528000000000e-10  1.159989414826e-01 
+ 9.628000000000e-10  1.362728766964e-01 
+ 9.728000000000e-10  1.378609481665e-01 
+ 9.828000000000e-10  1.201654675877e-01 
+ 9.928000000000e-10  8.531845800935e-02 
+ 1.002800000000e-09  3.762175912380e-02 
+ 1.012800000000e-09 -1.685664100816e-02 
+ 1.022800000000e-09 -7.076872562088e-02 
+ 1.032800000000e-09 -1.164143387352e-01 
+ 1.042800000000e-09 -1.469386398655e-01 
+ 1.052800000000e-09 -1.575081369809e-01 
+ 1.062800000000e-09 -1.461809922494e-01 
+ 1.072800000000e-09 -1.142388546131e-01 
+ 1.082800000000e-09 -6.564521610040e-02 
+ 1.092800000000e-09 -6.477028338857e-03 
+ 1.102800000000e-09  5.551055899345e-02 
+ 1.112800000000e-09  1.116757578142e-01 
+ 1.122800000000e-09  1.536617521164e-01 
+ 1.132800000000e-09  1.749454695942e-01 
+ 1.142800000000e-09  1.720483324045e-01 
+ 1.152800000000e-09  1.450719574156e-01 
+ 1.162800000000e-09  9.740616623873e-02 
+ 1.172800000000e-09  3.499844305237e-02 
+ 1.182800000000e-09 -3.419951466736e-02 
+ 1.192800000000e-09 -1.008328088904e-01 
+ 1.202800000000e-09 -1.551785296701e-01 
+ 1.212800000000e-09 -1.888856529531e-01 
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+ 8.632800000000e-09  1.833694258867e-01 
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+ 9.842800000000e-09  4.377336225167e-01 
+ 9.852800000000e-09  3.505682171311e-01 
+ 9.862800000000e-09  2.179845523073e-01 
+ 9.872800000000e-09  5.679231329547e-02 
+ 9.882800000000e-09 -1.151519233912e-01 
+ 9.892800000000e-09 -2.751127298994e-01 
+ 9.902800000000e-09 -3.968627871110e-01 
+ 9.912800000000e-09 -4.596231585185e-01 
+ 9.922800000000e-09 -4.555307752008e-01 
+ 9.932800000000e-09 -3.883695919340e-01 
+ 9.942800000000e-09 -2.700784914521e-01 
+ 9.952800000000e-09 -1.171279413116e-01 
+ 9.962800000000e-09  5.330739378300e-02 
+ 9.972800000000e-09  2.206176409949e-01 
+ 9.982800000000e-09  3.591197913484e-01 
+ 9.992800000000e-09  4.447287668034e-01 
+ 1.000000000000e-08  4.658065634617e-01 
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/conditions.yaml
new file mode 100644
index 00000000..bbc20751
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 10
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_10
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..6b4e889e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/LC_Oscillator_tb_11.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/conditions.yaml
new file mode 100644
index 00000000..293acdd4
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 11
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_11
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..b32ccf22
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/LC_Oscillator_tb_12.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/conditions.yaml
new file mode 100644
index 00000000..0c069899
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 12
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_12
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..74d02ed3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb_13.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb_13.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb_13.data
new file mode 100644
index 00000000..67e81b75
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/LC_Oscillator_tb_13.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  8.118333159888e-03 
+ 1.728000000000e-10 -6.329880087169e-03 
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+ 9.602800000000e-09 -4.547046959353e-01 
+ 9.612800000000e-09 -3.857312315368e-01 
+ 9.622800000000e-09 -2.662188447241e-01 
+ 9.632800000000e-09 -1.125308418547e-01 
+ 9.642800000000e-09  5.811613266870e-02 
+ 9.652800000000e-09  2.250456324980e-01 
+ 9.662800000000e-09  3.624489148595e-01 
+ 9.672800000000e-09  4.463975513791e-01 
+ 9.682800000000e-09  4.646852332412e-01 
+ 9.692800000000e-09  4.179266651016e-01 
+ 9.702800000000e-09  3.154839613510e-01 
+ 9.712800000000e-09  1.725777900289e-01 
+ 9.722800000000e-09  6.253628647848e-03 
+ 9.732800000000e-09 -1.647794164684e-01 
+ 9.742800000000e-09 -3.162350021308e-01 
+ 9.752800000000e-09 -4.222435254205e-01 
+ 9.762800000000e-09 -4.655351629575e-01 
+ 9.772800000000e-09 -4.423393851837e-01 
+ 9.782800000000e-09 -3.592595442771e-01 
+ 9.792800000000e-09 -2.295868870697e-01 
+ 9.802800000000e-09 -7.001555229933e-02 
+ 9.812800000000e-09  1.018172202550e-01 
+ 9.822800000000e-09  2.637151159726e-01 
+ 9.832800000000e-09  3.894058063411e-01 
+ 9.842800000000e-09  4.573804246669e-01 
+ 9.852800000000e-09  4.588302271332e-01 
+ 9.862800000000e-09  3.967598241271e-01 
+ 9.872800000000e-09  2.824022778434e-01 
+ 9.882800000000e-09  1.318801482237e-01 
+ 9.892800000000e-09 -3.769121150598e-02 
+ 9.902800000000e-09 -2.063128036268e-01 
+ 9.912800000000e-09 -3.485693523865e-01 
+ 9.922800000000e-09 -4.397407193722e-01 
+ 9.932800000000e-09 -4.659661993700e-01 
+ 9.942800000000e-09 -4.265430171005e-01 
+ 9.952800000000e-09 -3.302090287242e-01 
+ 9.962800000000e-09 -1.914306825298e-01 
+ 9.972800000000e-09 -2.692694651887e-02 
+ 9.982800000000e-09  1.448342393448e-01 
+ 9.992800000000e-09  3.001601116225e-01 
+ 1.000000000000e-08  3.874460036265e-01 
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/conditions.yaml
new file mode 100644
index 00000000..57678b46
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 13
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_13
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..e2272eb3
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/LC_Oscillator_tb_14.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/conditions.yaml
new file mode 100644
index 00000000..044497be
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 14
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_14
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..782eef46
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/LC_Oscillator_tb_15.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/conditions.yaml
new file mode 100644
index 00000000..bd8fcce6
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 15
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_15
+temperature: '27'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..cff378d0
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb_16.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb_16.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb_16.data
new file mode 100644
index 00000000..5e709abb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/LC_Oscillator_tb_16.data
@@ -0,0 +1,985 @@
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diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/conditions.yaml
new file mode 100644
index 00000000..739a2d27
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 16
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_16
+temperature: '27'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..0d420f2f
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/LC_Oscillator_tb_17.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 27
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/conditions.yaml
new file mode 100644
index 00000000..2502cf4b
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 17
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_17
+temperature: '27'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..6dc2ee70
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/LC_Oscillator_tb_18.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/conditions.yaml
new file mode 100644
index 00000000..55193bf9
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 18
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_18
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..12f93083
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb_19.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb_19.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb_19.data
new file mode 100644
index 00000000..04e15afb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/LC_Oscillator_tb_19.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  7.148700138490e-03 
+ 1.728000000000e-10 -6.556248283308e-03 
+ 1.828000000000e-10 -1.971437135227e-02 
+ 1.928000000000e-10 -3.046832510057e-02 
+ 2.028000000000e-10 -3.724484206798e-02 
+ 2.128000000000e-10 -3.898722404017e-02 
+ 2.228000000000e-10 -3.531874717656e-02 
+ 2.328000000000e-10 -2.661104433390e-02 
+ 2.428000000000e-10 -1.394722371181e-02 
+ 2.528000000000e-10  1.010890375025e-03 
+ 2.628000000000e-10  1.623518558993e-02 
+ 2.728000000000e-10  2.959972790204e-02 
+ 2.828000000000e-10  3.917676561508e-02 
+ 2.928000000000e-10  4.351854183212e-02 
+ 3.028000000000e-10  4.187897998930e-02 
+ 3.128000000000e-10  3.433491833145e-02 
+ 3.228000000000e-10  2.178964009036e-02 
+ 3.328000000000e-10  5.862674403261e-03 
+ 3.428000000000e-10 -1.131445345393e-02 
+ 3.528000000000e-10 -2.737440631426e-02 
+ 3.628000000000e-10 -4.003447001271e-02 
+ 3.728000000000e-10 -4.742374767739e-02 
+ 3.828000000000e-10 -4.836506885182e-02 
+ 3.928000000000e-10 -4.256093597883e-02 
+ 4.028000000000e-10 -3.065096603476e-02 
+ 4.128000000000e-10 -1.413831435399e-02 
+ 4.228000000000e-10  4.797692448234e-03 
+ 4.328000000000e-10  2.357802655500e-02 
+ 4.428000000000e-10  3.956516961760e-02 
+ 4.528000000000e-10  5.043395269242e-02 
+ 4.628000000000e-10  5.451894284417e-02 
+ 4.728000000000e-10  5.107393783219e-02 
+ 4.828000000000e-10  4.039477807846e-02 
+ 4.928000000000e-10  2.378773582336e-02 
+ 5.028000000000e-10  3.413561417878e-03 
+ 5.128000000000e-10 -1.798715588926e-02 
+ 5.228000000000e-10 -3.745223885697e-02 
+ 5.328000000000e-10 -5.219304612990e-02 
+ 5.428000000000e-10 -6.000529045762e-02 
+ 5.528000000000e-10 -5.961153530135e-02 
+ 5.628000000000e-10 -5.086480313709e-02 
+ 5.728000000000e-10 -3.478185641254e-02 
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+ 9.772800000000e-09 -3.346824428589e-01 
+ 9.782800000000e-09 -2.028601212935e-01 
+ 9.792800000000e-09 -4.400439860500e-02 
+ 9.802800000000e-09  1.234236306485e-01 
+ 9.812800000000e-09  2.768078469650e-01 
+ 9.822800000000e-09  3.915459502709e-01 
+ 9.832800000000e-09  4.486053590697e-01 
+ 9.842800000000e-09  4.408748739016e-01 
+ 9.852800000000e-09  3.724306116446e-01 
+ 9.862800000000e-09  2.547759754158e-01 
+ 9.872800000000e-09  1.037662637715e-01 
+ 9.882800000000e-09 -6.291942160305e-02 
+ 9.892800000000e-09 -2.242679826661e-01 
+ 9.902800000000e-09 -3.557446468578e-01 
+ 9.912800000000e-09 -4.352750113677e-01 
+ 9.922800000000e-09 -4.511486238742e-01 
+ 9.932800000000e-09 -4.037404398857e-01 
+ 9.942800000000e-09 -3.021993202790e-01 
+ 9.952800000000e-09 -1.613042783594e-01 
+ 9.962800000000e-09  1.850204572038e-03 
+ 9.972800000000e-09  1.678345791808e-01 
+ 9.982800000000e-09  3.129973889485e-01 
+ 9.992800000000e-09  4.133827788063e-01 
+ 1.000000000000e-08  4.484478536981e-01 
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/conditions.yaml
new file mode 100644
index 00000000..6b58f300
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 19
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_19
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..f4413a3d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/LC_Oscillator_tb_20.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/conditions.yaml
new file mode 100644
index 00000000..a736c299
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 20
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: tt
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_20
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..f5b0c8d4
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/LC_Oscillator_tb_21.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/conditions.yaml
new file mode 100644
index 00000000..ce71a314
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 21
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_21
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..ff1fd492
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb_22.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb_22.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb_22.data
new file mode 100644
index 00000000..3bcfec59
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/LC_Oscillator_tb_22.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  7.462015324670e-03 
+ 1.728000000000e-10 -6.256359287127e-03 
+ 1.828000000000e-10 -1.947939464126e-02 
+ 1.928000000000e-10 -3.034608665676e-02 
+ 2.028000000000e-10 -3.727079390626e-02 
+ 2.128000000000e-10 -3.917713039254e-02 
+ 2.228000000000e-10 -3.566402772378e-02 
+ 2.328000000000e-10 -2.707763600809e-02 
+ 2.428000000000e-10 -1.447813124100e-02 
+ 2.528000000000e-10  4.893286847443e-04 
+ 2.628000000000e-10  1.580373551747e-02 
+ 2.728000000000e-10  2.933423360913e-02 
+ 2.828000000000e-10  3.913545495466e-02 
+ 2.928000000000e-10  4.373093390651e-02 
+ 3.028000000000e-10  4.233865012378e-02 
+ 3.128000000000e-10  3.499740504213e-02 
+ 3.228000000000e-10  2.257588627703e-02 
+ 3.328000000000e-10  6.667647601252e-03 
+ 3.428000000000e-10 -1.060854651401e-02 
+ 3.528000000000e-10 -2.688147204474e-02 
+ 3.628000000000e-10 -3.984650084814e-02 
+ 3.728000000000e-10 -4.759459078779e-02 
+ 3.828000000000e-10 -4.889923297470e-02 
+ 3.928000000000e-10 -4.340960680427e-02 
+ 4.028000000000e-10 -3.171564611244e-02 
+ 4.128000000000e-10 -1.528141085475e-02 
+ 4.228000000000e-10  3.736367483853e-03 
+ 4.328000000000e-10  2.275994025390e-02 
+ 4.428000000000e-10  3.912897403376e-02 
+ 4.528000000000e-10  5.047226151644e-02 
+ 4.628000000000e-10  5.506070810499e-02 
+ 4.728000000000e-10  5.207617346251e-02 
+ 4.828000000000e-10  4.174493772919e-02 
+ 4.928000000000e-10  2.531567528440e-02 
+ 5.028000000000e-10  4.911723956107e-03 
+ 5.128000000000e-10 -1.673757535376e-02 
+ 5.228000000000e-10 -3.664841605540e-02 
+ 5.328000000000e-10 -5.198143089124e-02 
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+ 5.528000000000e-10 -6.070345153897e-02 
+ 5.628000000000e-10 -5.247997862317e-02 
+ 5.728000000000e-10 -3.672223292437e-02 
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+ 6.028000000000e-10  3.211102099655e-02 
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+ 6.228000000000e-10  6.470866636109e-02 
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+ 7.128000000000e-10 -7.633734398201e-02 
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+ 7.528000000000e-10 -1.450157143681e-02 
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+ 8.028000000000e-10  8.573801967081e-02 
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+ 8.228000000000e-10  5.763855877903e-02 
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+ 8.628000000000e-10 -6.586749096797e-02 
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+ 1.112800000000e-09  8.155671434407e-02 
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+ 1.152800000000e-09  1.096376067759e-01 
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+ 1.172800000000e-09  2.884004915010e-02 
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+ 1.192800000000e-09 -7.190966934979e-02 
+ 1.202800000000e-09 -1.126431360758e-01 
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+ 1.232800000000e-09 -1.323095643591e-01 
+ 1.242800000000e-09 -1.004494263485e-01 
+ 1.252800000000e-09 -5.397485658337e-02 
+ 1.262800000000e-09  1.163151823916e-03 
+ 1.272800000000e-09  5.761026789043e-02 
+ 1.282800000000e-09  1.074705253488e-01 
+ 1.292800000000e-09  1.434136966323e-01 
+ 1.302800000000e-09  1.599589000088e-01 
+ 1.312800000000e-09  1.544239373438e-01 
+ 1.322800000000e-09  1.273119872972e-01 
+ 1.332800000000e-09  8.204355266655e-02 
+ 1.342800000000e-09  2.437528289482e-02 
+ 1.352800000000e-09 -3.816758544726e-02 
+ 1.362800000000e-09 -9.703299953333e-02 
+ 1.372800000000e-09 -1.437033223974e-01 
+ 1.382800000000e-09 -1.711448362067e-01 
+ 1.392800000000e-09 -1.750592166422e-01 
+ 1.402800000000e-09 -1.546040461286e-01 
+ 1.412800000000e-09 -1.124265193069e-01 
+ 1.422800000000e-09 -5.387980000143e-02 
+ 1.432800000000e-09  1.358751979042e-02 
+ 1.442800000000e-09  8.094481862007e-02 
+ 1.452800000000e-09  1.386381018355e-01 
+ 1.462800000000e-09  1.780283777447e-01 
+ 1.472800000000e-09  1.930455851535e-01 
+ 1.482800000000e-09  1.812795304609e-01 
+ 1.492800000000e-09  1.442214159806e-01 
+ 1.502800000000e-09  8.665025987117e-02 
+ 1.512800000000e-09  1.584846254613e-02 
+ 1.522800000000e-09 -5.896130453386e-02 
+ 1.532800000000e-09 -1.274441358957e-01 
+ 1.542800000000e-09 -1.794946786279e-01 
+ 1.552800000000e-09 -2.071466383415e-01 
+ 1.562800000000e-09 -2.060908858808e-01 
+ 1.572800000000e-09 -1.763343973120e-01 
+ 1.582800000000e-09 -1.218466477637e-01 
+ 1.592800000000e-09 -4.959288242863e-02 
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+ 8.972800000000e-09  9.917658135956e-03 
+ 8.982800000000e-09  1.754444577473e-01 
+ 8.992800000000e-09  3.190048626354e-01 
+ 9.002800000000e-09  4.167494868982e-01 
+ 9.012800000000e-09  4.533069968880e-01 
+ 9.022800000000e-09  4.256214087006e-01 
+ 9.032800000000e-09  3.405157290623e-01 
+ 9.042800000000e-09  2.109456368989e-01 
+ 9.052800000000e-09  5.317747545113e-02 
+ 9.062800000000e-09 -1.143323651434e-01 
+ 9.072800000000e-09 -2.692154568507e-01 
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+ 9.102800000000e-09 -4.434492327994e-01 
+ 9.112800000000e-09 -3.786545807898e-01 
+ 9.122800000000e-09 -2.638542129423e-01 
+ 9.132800000000e-09 -1.146057654528e-01 
+ 9.142800000000e-09  5.155841744751e-02 
+ 9.152800000000e-09  2.140258361192e-01 
+ 9.162800000000e-09  3.483221038618e-01 
+ 9.172800000000e-09  4.318881267061e-01 
+ 9.182800000000e-09  4.523550063090e-01 
+ 9.192800000000e-09  4.094918937189e-01 
+ 9.202800000000e-09  3.117596780726e-01 
+ 9.212800000000e-09  1.734662900911e-01 
+ 9.222800000000e-09  1.155102157897e-02 
+ 9.232800000000e-09 -1.549595462786e-01 
+ 9.242800000000e-09 -3.027034233065e-01 
+ 9.252800000000e-09 -4.073947834745e-01 
+ 9.262800000000e-09 -4.522175723624e-01 
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+ 9.292800000000e-09 -2.293204845041e-01 
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+ 9.312800000000e-09  9.320478651195e-02 
+ 9.322800000000e-09  2.510384881099e-01 
+ 9.332800000000e-09  3.745642376476e-01 
+ 9.342800000000e-09  4.433246588189e-01 
+ 9.352800000000e-09  4.478937360742e-01 
+ 9.362800000000e-09  3.902940459792e-01 
+ 9.372800000000e-09  2.808530270468e-01 
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+ 9.452800000000e-09 -3.271947900137e-01 
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+ 9.482800000000e-09  1.342887191779e-01 
+ 9.492800000000e-09  2.861199900574e-01 
+ 9.502800000000e-09  3.977168385702e-01 
+ 9.512800000000e-09  4.507402217909e-01 
+ 9.522800000000e-09  4.391110351565e-01 
+ 9.532800000000e-09  3.675437714408e-01 
+ 9.542800000000e-09  2.476385608832e-01 
+ 9.552800000000e-09  9.525356388976e-02 
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+ 9.642800000000e-09  8.636202324294e-03 
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+ 9.672800000000e-09  4.164889465397e-01 
+ 9.682800000000e-09  4.535572878800e-01 
+ 9.692800000000e-09  4.263236462633e-01 
+ 9.702800000000e-09  3.415536856094e-01 
+ 9.712800000000e-09  2.121781311737e-01 
+ 9.722800000000e-09  5.446571726142e-02 
+ 9.732800000000e-09 -1.131421009652e-01 
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+ 9.772800000000e-09 -4.439449184184e-01 
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+ 9.792800000000e-09 -2.649981277889e-01 
+ 9.802800000000e-09 -1.158721210561e-01 
+ 9.812800000000e-09  5.031372300316e-02 
+ 9.822800000000e-09  2.129735066346e-01 
+ 9.832800000000e-09  3.476354406006e-01 
+ 9.842800000000e-09  4.316799545378e-01 
+ 9.852800000000e-09  4.526408185429e-01 
+ 9.862800000000e-09  4.102081755019e-01 
+ 9.872800000000e-09  3.127946687819e-01 
+ 9.882800000000e-09  1.746852880125e-01 
+ 9.892800000000e-09  1.281626765136e-02 
+ 9.902800000000e-09 -1.538078553024e-01 
+ 9.912800000000e-09 -3.018441271548e-01 
+ 9.922800000000e-09 -4.069740187264e-01 
+ 9.932800000000e-09 -4.521973532026e-01 
+ 9.942800000000e-09 -4.329168386702e-01 
+ 9.952800000000e-09 -3.549020207436e-01 
+ 9.962800000000e-09 -2.303806136131e-01 
+ 9.972800000000e-09 -7.541460414883e-02 
+ 9.982800000000e-09  9.192950911472e-02 
+ 9.992800000000e-09  2.499117932946e-01 
+ 1.000000000000e-08  3.444880261518e-01 
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/conditions.yaml
new file mode 100644
index 00000000..960ceeec
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 22
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_22
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..dd8ef299
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/LC_Oscillator_tb_23.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/conditions.yaml
new file mode 100644
index 00000000..7353f256
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 23
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ff
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_23
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..a82a85b1
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/LC_Oscillator_tb_24.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=0.8 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/conditions.yaml
new file mode 100644
index 00000000..4ade0832
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 24
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_24
+temperature: '80'
+vdd: '0.8'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..25127dae
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb_25.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb_25.data b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb_25.data
new file mode 100644
index 00000000..f4494484
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/LC_Oscillator_tb_25.data
@@ -0,0 +1,985 @@
+ 1.628000000000e-10  7.012500893491e-03 
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+ 9.982800000000e-09  4.307731403463e-01 
+ 9.992800000000e-09  4.572693054677e-01 
+ 1.000000000000e-08  4.354906013278e-01 
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/conditions.yaml
new file mode 100644
index 00000000..5eec55cb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 25
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_25
+temperature: '80'
+vdd: '1.2'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/.spiceinit b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/.spiceinit
new file mode 100644
index 00000000..02b902fb
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/.spiceinit
@@ -0,0 +1,30 @@
+*  a custom spiceinit file for IHP-Open-PDK 
+
+* export PDK_ROOT and PDK environmental variables first and add it to your .bashrc
+* export PDK_ROOT= installation_specific_directory/IHP-Open-PDK
+* export PDK=ihp-sg13g2 
+
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/spice )
+setcs sourcepath = (  $sourcepath $PDK_ROOT/$PDK/libs.tech/ngspice/models $PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/spice )
+*echo $sourcepath
+
+*option tnom=28
+*option list
+
+* KLU solver still do not work correctly for every simulation
+*option klu
+
+*option node
+*option opts
+*option warn=1
+*option maxwarns=10
+*option savecurrents
+
+*set ngbehavior=hsa
+*set noinit
+
+* add OSDI 
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/psp103_nqs.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/r3_cmc.osdi'
+osdi  '$PDK_ROOT/$PDK/libs.tech/ngspice/osdi/mosvar.osdi'
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator.sym
new file mode 100644
index 00000000..e632b156
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..c1df500e
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator_tb.sch
@@ -0,0 +1,57 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 1570 -1060 1570 -1030 {lab=VDD}
+N 1570 -970 1570 -940 {lab=GND}
+N 1270 -1050 1270 -1030 {lab=GND}
+N 1230 -1060 1230 -1030 {lab=VDD}
+N 1140 -920 1160 -920 {lab=Voplus}
+N 1140 -960 1160 -960 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+
+set wr_singlescale
+wrdata /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/LC_Oscillator_tb_26.data vo_diff
+quit
+
+.endc
+"}
+C {vsource.sym} 1570 -1000 0 0 {name=V1 value=1.6 savecurrent=false}
+C {gnd.sym} 1570 -940 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1570 -1060 0 0 {name=p2 sig_type=std_logic lab=VDD}
+C {opin.sym} 1140 -920 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 1270 -1050 2 0 {name=l3 lab=GND}
+C {opin.sym} 1140 -960 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 1250 -940 2 0 {name=x1}
+C {devices/code_shown.sym} 450 -640 0 0 {name=SETUP only_toplevel=true
+format="tcleval( @value )"
+value="
+.lib /home/pedersen/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ss
+
+.include /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+
+.temp 80
+"
+}
+C {iopin.sym} 1230 -1060 2 0 {name=p1 lab=VDD}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/conditions.yaml b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/conditions.yaml
new file mode 100644
index 00000000..dda699ee
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26/conditions.yaml
@@ -0,0 +1,9 @@
+DUT_path: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/xschem/simulations/schematic/LC_Oscillator.spice
+N: 26
+PDK: ihp-sg13g2
+PDK_ROOT: /home/pedersen/IHP-Open-PDK
+corner: ss
+filename: LC_Oscillator_tb
+simpath: /home/pedersen/projects/IHP-AnalogAcademy/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/parameters/ac_params/run_26
+temperature: '80'
+vdd: '1.6'
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/summary.md b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/summary.md
new file mode 100644
index 00000000..314e0775
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/runs/RUN_2025-11-17_09-25-51/summary.md
@@ -0,0 +1,11 @@
+
+# CACE Summary for LC_Oscillator
+
+**netlist source**: schematic
+
+|      Parameter       |         Tool         |     Result      | Min Limit  |  Min Value   | Typ Target |  Typ Value   | Max Limit  |  Max Value   |  Status  |
+| :------------------- | :------------------- | :-------------- | ---------: | -----------: | ---------: | -----------: | ---------: | -----------: | :------: |
+| Frequency            | ngspice              | frequency            |         4.3 GHz |          ​ |      5.0 GHz |          ​ |      5.2 GHz |          ​ |   Error ❗   |
+| Amplitude            | ngspice              | amplitude            |           0.2 V |          ​ |        0.4 V |          ​ |        0.6 V |          ​ |   Error ❗   |
+| Voltage swing        | ngspice              | voltage_swing        |           0.4 V |          ​ |        0.8 V |          ​ |        1.2 V |          ​ |   Error ❗   |
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/testbench/LC_Oscillator_tb.sch b/modules/module_4_type_2_PLL/LC_Oscillator/testbench/LC_Oscillator_tb.sch
new file mode 100644
index 00000000..8a9049fd
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/testbench/LC_Oscillator_tb.sch
@@ -0,0 +1,132 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+B 2 1120 -1110 1920 -710 {flags=graph
+y1=1.1
+y2=1.3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=1.628e-10
+x2=1e-09
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+dataset=-1
+unitx=1
+logx=0
+logy=0
+color="4 7"
+node="vo_m
+vo_p"}
+B 2 1930 -1120 2730 -720 {flags=graph
+y1=-0.41
+y2=0.41
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=1.628e-10
+x2=1e-09
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+dataset=-1
+unitx=1
+logx=0
+logy=0
+color=4
+node=vo_diff}
+N 1040 -530 1040 -500 {lab=vdd}
+N 1040 -440 1040 -410 {lab=GND}
+N 740 -520 740 -500 {lab=GND}
+N 700 -530 700 -500 {lab=vdd}
+N 610 -390 630 -390 {lab=Voplus}
+N 610 -430 630 -430 {lab=Vominus}
+C {code_shown.sym} 440 -1140 0 0 {name=transient_tb only_toplevel=false
+value="
+.include LC_Oscillator_tb.save
+.param temp=27
+.ic V(Voplus)=1.2
+.control
+set noaskquit
+set numdgt=12
+
+* Save & simulate
+save all
+op
+write LC_Oscillator_tb.raw
+set appendwrite
+tran 10p 10n 160p
+save all
+
+* Explicit vectors
+let vo_p    = v(Voplus)
+let vo_m    = v(Vominus)
+let vo_diff = vo_p - vo_m
+* --- Main output (mimic CACE naming, just to compare) ---
+set wr_singlescale
+wrdata differential_output.txt vo_diff
+
+* --- Extra debug (like we did for CACE) ---
+set wr_vecnames
+wrdata manual_debug.dat time vo_p vo_m vo_diff
+unset wr_vecnames
+
+write LC_Oscillator_tb.raw
+.endc
+"}
+C {devices/code_shown.sym} 810 -1130 0 0 {name=MODEL only_toplevel=true
+format="tcleval( @value )"
+value=".lib cornerMOSlv.lib mos_tt
+"
+}
+C {devices/launcher.sym} 1190 -250 0 0 {name=h1
+descr="OP annotate" 
+tclcommand="xschem annotate_op"
+}
+C {launcher.sym} 1190 -170 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/LC_Oscillator_tb.raw tran"
+}
+C {vsource.sym} 1040 -470 0 0 {name=V1 value=1.2 savecurrent=false}
+C {gnd.sym} 1040 -410 0 0 {name=l2 lab=GND}
+C {lab_pin.sym} 1040 -530 0 0 {name=p2 sig_type=std_logic lab=vdd}
+C {opin.sym} 610 -390 2 0 {name=p6 lab=Voplus}
+C {gnd.sym} 740 -520 2 0 {name=l3 lab=GND}
+C {lab_pin.sym} 700 -530 2 1 {name=p7 sig_type=std_logic lab=vdd}
+C {launcher.sym} 1190 -210 0 0 {name=h2
+descr=SimulateNGSPICE
+tclcommand="
+# Setup the default simulation commands if not already set up
+# for example by already launched simulations.
+set_sim_defaults
+puts $sim(spice,1,cmd) 
+
+# Change the Xyce command. In the spice category there are currently
+# 5 commands (0, 1, 2, 3, 4). Command 3 is the Xyce batch
+# you can get the number by querying $sim(spice,n)
+set sim(spice,1,cmd) \{ngspice  \\"$N\\" -a\}
+
+# change the simulator to be used (Xyce)
+set sim(spice,default) 0
+
+# Create FET and BIP .save file
+mkdir -p $netlist_dir
+write_data [save_params] $netlist_dir/[file rootname [file tail [xschem get current_name]]].save
+
+# run netlist and simulation
+xschem netlist
+simulate
+"}
+C {opin.sym} 610 -430 0 1 {name=p9 lab=Vominus}
+C {LC_Oscillator.sym} 720 -410 2 0 {name=x1}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/testbench/simulations/LC_Oscillator_tb.save b/modules/module_4_type_2_PLL/LC_Oscillator/testbench/simulations/LC_Oscillator_tb.save
new file mode 100644
index 00000000..85bf3b74
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/testbench/simulations/LC_Oscillator_tb.save
@@ -0,0 +1,22 @@
+* Place this .save file with a .include line in your testbench
+
+.save @n.x1.xm1.nsg13_lv_nmos[ids]
+.save @n.x1.xm1.nsg13_lv_nmos[gm]
+.save @n.x1.xm1.nsg13_lv_nmos[gds]
+.save @n.x1.xm1.nsg13_lv_nmos[vth]
+.save @n.x1.xm1.nsg13_lv_nmos[vgs]
+.save @n.x1.xm1.nsg13_lv_nmos[vdss]
+.save @n.x1.xm1.nsg13_lv_nmos[vds]
+.save @n.x1.xm1.nsg13_lv_nmos[cgg]
+.save @n.x1.xm1.nsg13_lv_nmos[cgsol]
+.save @n.x1.xm1.nsg13_lv_nmos[cgdol]
+.save @n.x1.xm2.nsg13_lv_nmos[ids]
+.save @n.x1.xm2.nsg13_lv_nmos[gm]
+.save @n.x1.xm2.nsg13_lv_nmos[gds]
+.save @n.x1.xm2.nsg13_lv_nmos[vth]
+.save @n.x1.xm2.nsg13_lv_nmos[vgs]
+.save @n.x1.xm2.nsg13_lv_nmos[vdss]
+.save @n.x1.xm2.nsg13_lv_nmos[vds]
+.save @n.x1.xm2.nsg13_lv_nmos[cgg]
+.save @n.x1.xm2.nsg13_lv_nmos[cgsol]
+.save @n.x1.xm2.nsg13_lv_nmos[cgdol]
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/testbench/xschemrc b/modules/module_4_type_2_PLL/LC_Oscillator/testbench/xschemrc
new file mode 100644
index 00000000..34b6db6d
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/testbench/xschemrc
@@ -0,0 +1,18 @@
+# xschemrc - Custom configuration file for xschem
+# This file sources another xschemrc file from a known location
+
+# Source the base configuration from a known location
+source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
+
+# (Optional) Add any custom overrides or extensions below
+# set xschem_library_path /home/user/my_libs
+# set xschem_gui_font "Monospace 10"
+
+#### include skywater libraries. Here I use [pwd]. This works if I start xschem from here.
+###only if you dont have this setup already ### 
+###append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
+
+
+#### Add custom libraries (directories with .lib files)
+append XSCHEM_LIBRARY_PATH :../xschem/
+
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/xschem/LC_Oscillator.sch b/modules/module_4_type_2_PLL/LC_Oscillator/xschem/LC_Oscillator.sch
new file mode 100644
index 00000000..5e278143
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/xschem/LC_Oscillator.sch
@@ -0,0 +1,105 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+N 310 -500 310 -440 {lab=#net1}
+N 420 -440 530 -440 {lab=#net1}
+N 530 -500 530 -440 {lab=#net1}
+N 310 -720 310 -690 {lab=vdd}
+N 420 -720 530 -720 {lab=vdd}
+N 530 -720 530 -690 {lab=vdd}
+N 310 -440 420 -440 {lab=#net1}
+N 530 -600 530 -560 {lab=Vominus}
+N 420 -330 420 -290 {lab=gnd}
+N 420 -740 420 -720 {lab=vdd}
+N 310 -720 420 -720 {lab=vdd}
+N 530 -530 580 -530 {lab=gnd}
+N 250 -530 310 -530 {lab=gnd}
+N 420 -440 420 -390 {lab=#net1}
+N 460 -530 490 -530 {lab=Voplus}
+N 310 -590 310 -560 {lab=Voplus}
+N 350 -530 380 -530 {lab=Vominus}
+N 380 -530 530 -630 {lab=Vominus}
+N 310 -630 460 -530 {lab=Voplus}
+N 530 -690 600 -690 {lab=vdd}
+N 530 -630 600 -630 {lab=Vominus}
+N 240 -690 310 -690 {lab=vdd}
+N 240 -630 310 -630 {lab=Voplus}
+N 170 -590 310 -590 {lab=Voplus}
+N 310 -630 310 -590 {lab=Voplus}
+N 530 -600 670 -600 {lab=Vominus}
+N 530 -630 530 -600 {lab=Vominus}
+N 170 -590 170 -580 {lab=Voplus}
+N 170 -520 170 -490 {lab=gnd}
+N 670 -600 670 -590 {lab=Vominus}
+N 670 -530 670 -500 {lab=gnd}
+C {sg13g2_pr/sg13_lv_nmos.sym} 330 -530 0 1 {name=M1
+l=0.13u
+w=16u
+ng=4
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {sg13g2_pr/sg13_lv_nmos.sym} 510 -530 0 0 {name=M2
+l=0.13u
+w=16u
+ng=4
+m=1
+model=sg13_lv_nmos
+spiceprefix=X
+}
+C {res.sym} 600 -660 0 0 {name=R2
+value=393
+footprint=1206
+device=resistor
+m=1}
+C {isource.sym} 420 -360 0 0 {name=I0 value=1m}
+C {lab_pin.sym} 420 -290 2 0 {name=p3 sig_type=std_logic lab=gnd
+}
+C {lab_pin.sym} 420 -740 2 0 {name=p9 sig_type=std_logic lab=vdd
+}
+C {iopin.sym} 230 -370 2 0 {name=p24 lab=vdd}
+C {iopin.sym} 230 -350 2 0 {name=p25 lab=gnd}
+C {ind.sym} 530 -660 0 0 {name=L1
+m=1
+value=1.56n
+footprint=1206
+device=inductor}
+C {lab_pin.sym} 580 -530 2 0 {name=p1 sig_type=std_logic lab=gnd
+}
+C {lab_pin.sym} 250 -530 0 0 {name=p5 sig_type=std_logic lab=gnd
+}
+C {res.sym} 240 -660 0 1 {name=R1
+value=393
+footprint=1206
+device=resistor
+m=1}
+C {ind.sym} 310 -660 0 1 {name=L2
+m=1
+value=1.56n
+footprint=1206
+device=inductor}
+C {capa.sym} 170 -550 0 0 {name=C1
+m=1
+value=400f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 170 -490 0 0 {name=p2 sig_type=std_logic lab=gnd
+}
+C {capa.sym} 670 -560 0 1 {name=C2
+m=1
+value=400f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 670 -500 0 1 {name=p4 sig_type=std_logic lab=gnd
+}
+C {lab_pin.sym} 670 -600 2 0 {name=p6 sig_type=std_logic lab=Vominus
+}
+C {lab_pin.sym} 170 -590 0 0 {name=p7 sig_type=std_logic lab=Voplus
+}
+C {opin.sym} 230 -330 2 0 {name=p8 lab=Voplus}
+C {opin.sym} 230 -310 2 0 {name=p10 lab=Vominus}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/xschem/LC_Oscillator.sym b/modules/module_4_type_2_PLL/LC_Oscillator/xschem/LC_Oscillator.sym
new file mode 100644
index 00000000..b9399769
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/xschem/LC_Oscillator.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.4.6 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 -20 90 -20 {}
+L 4 70 20 90 20 {}
+L 7 20 70 20 90 {}
+L 7 -20 70 -20 90 {}
+B 5 87.5 -22.5 92.5 -17.5 {name=Voplus dir=out}
+B 5 17.5 87.5 22.5 92.5 {name=vdd dir=inout}
+B 5 -22.5 87.5 -17.5 92.5 {name=gnd dir=inout}
+B 5 87.5 17.5 92.5 22.5 {name=Vominus dir=out}
+A 4 -1.666666666666714 1.666666666666714 71.68604389202189 287.5924245621816 360 {}
+A 4 -30 27.5 40.69705149024927 42.51044707800085 94.97910584399833 {}
+A 4 30 -27.5 40.69705149024927 222.5104470780009 94.97910584399833 {}
+T {@symname} -40.5 -56 0 0 0.1 0.1 {}
+T {@name} -40 -47 0 0 0.1 0.1 {
+}
+T {Voplus} 65 -24 0 1 0.2 0.2 {}
+T {vdd} 5 64 2 1 0.2 0.2 {}
+T {gnd} -35 64 2 1 0.2 0.2 {}
+T {Vominus} 65 16 0 1 0.2 0.2 {}
diff --git a/modules/module_4_type_2_PLL/LC_Oscillator/xschem/xschemrc b/modules/module_4_type_2_PLL/LC_Oscillator/xschem/xschemrc
new file mode 100644
index 00000000..14a1e9f2
--- /dev/null
+++ b/modules/module_4_type_2_PLL/LC_Oscillator/xschem/xschemrc
@@ -0,0 +1,12 @@
+# Source the base configuration from a known location
+source $::env(PDK_ROOT)/$::env(PDK)/libs.tech/xschem/xschemrc
+
+# Add current directory to xschem library path
+append XSCHEM_LIBRARY_PATH :[file dirname [info script]]
+
+# Source the dependencies xschemrc files
+foreach rcfile [glob -nocomplain ../ip/*/xschem/xschemrc] {
+  puts "sourcing $rcfile"
+  source $rcfile
+}
+