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Updated FPGA family feature matrix (markdown)

gatecat 2021-11-08 15:24:20 +00:00
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FPGA-family-feature-matrix.md

@ -4,26 +4,26 @@ There is a growing number of FPGA families that have support in the open source
The table on this page aims to keep track of which FPGA primitives are supported by which project.
| FPGA Family | Gowin LittleBee | MachXO2 | Lattice ECP5 |
|----------------|-----------------|----------------|-----------------|
| Project | Apicula |Facade/Trellis | Trellis |
| Logic Slice | ✔️ |✔️ |✔️ |
| ├ LUTRAM | ❌ |❌ |✔️ |
| └ ALU | ✔️ |❌ |✔️ |
| IO buffer | ✔️ |✔️ |✔️ |
| ├ IO standards | ✔️ |⚠️ |✔️ |
| └ DDR/SERDES | ❌ |❌ |✔️ |
| Block RAM | ❌ |❌ |✔️ |
| DSP | ❌ |❌ |✔️ |
| PLL | ❌ |❌ |✔️ |
| Routing | ✔️ |✔️ |✔️ |
| ├ Local | ✔️ |✔️ |✔️ |
| ├ Global | ✔️ |🚧 |✔️ |
| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |
| Timing | ✔️ |❌ |✔️ |
| ├ Logic | ✔️ |❌ |✔️ |
| ├ Routing | ✔️ |❌ |✔️ |
| └ IO buffer | ✔️ |❌ |🚧 |
| FPGA Family | Gowin LittleBee | MachXO2 | Lattice ECP5 | Lattice Nexus |
|----------------|-----------------|----------------|-----------------|----------------|
| Project | Apicula |Facade/Trellis | Trellis | prjoxide |
| Logic Slice | ✔️ |✔️ |✔️ |✔️ |
| ├ LUTRAM | ❌ |❌ |✔️ |✔️ |
| └ ALU | ✔️ |❌ |✔️ |✔️ |
| IO buffer | ✔️ |✔️ |✔️ |✔️ |
| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |
| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 |
| Block RAM | ❌ |❌ |✔️ |✔️ |
| DSP | ❌ |❌ |✔️ |✔️ |
| PLL | ❌ |❌ |✔️ |⚠️ |
| Routing | ✔️ |✔️ |✔️ |✔️ |
| ├ Local | ✔️ |✔️ |✔️ |✔️ |
| ├ Global | ✔️ |🚧 |✔️ |✔️ |
| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) |
| Timing | ✔️ |❌ |✔️ |✔️ |
| ├ Logic | ✔️ |❌ |✔️ |✔️ |
| ├ Routing | ✔️ |❌ |✔️ |✔️ |
| └ IO buffer | ✔️ |❌ |🚧 |🚧 |
| symbol | meaning |
|--------|--------------------------------------|