luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add Intel Cyclone V

Lofty 2022-03-17 18:20:14 +00:00
parent aa9889a183
commit c88ead20f4
1 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
FPGA-family-feature-matrix.md

@ -4,26 +4,26 @@ There is a growing number of FPGA families that have support in the open source
The table on this page aims to keep track of which FPGA primitives are supported by which project.
| FPGA Family | Gowin LittleBee | MachXO2 | Lattice ECP5 | Lattice Nexus | Lattice iCE40 |
|----------------|-----------------|----------------|-----------------|----------------|----------------|
| Project | Apicula |Facade/Trellis | Trellis | prjoxide | Icestorm |
| Logic Slice | ✔️ |✔️ |✔️ |✔️ |✔️ |
| ├ LUTRAM | ❌ |❌ |✔️ |✔️ |❌ (N/A) |
| └ ALU | ✔️ |❌ |✔️ |✔️ |✔️ |
| IO buffer | ✔️ |✔️ |✔️ |✔️ |✔️ |
| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |✔️ |
| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 |✔️ |
| Block RAM | ❌ |❌ |✔️ |✔️ |✔️ |
| DSP | ❌ |❌ |✔️ |✔️ |✔️ (up5k only) |
| PLL | ❌ |❌ |✔️ |⚠️ |✔️ |
| Routing | ✔️ |✔️ |✔️ |✔️ |✔️ |
| ├ Local | ✔️ |✔️ |✔️ |✔️ |✔️ |
| ├ Global | ✔️ |🚧 |✔️ |✔️ |✔️ |
| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |
| Timing | ✔️ |❌ |✔️ |✔️ |✔️ |
| ├ Logic | ✔️ |❌ |✔️ |✔️ |✔️ |
| ├ Routing | ✔️ |❌ |✔️ |✔️ |✔️ |
| └ IO buffer | ✔️ |❌ |🚧 |🚧 |❌ |
| FPGA Family | Gowin LittleBee | MachXO2 | Lattice ECP5 | Lattice Nexus | Lattice iCE40 | Intel Cyclone V |
|----------------|-----------------|----------------|-----------------|----------------|----------------|-----------------|
| Project | Apicula |Facade/Trellis | Trellis | prjoxide | Icestorm | Mistral |
| Logic Slice | ✔️ |✔️ |✔️ |✔️ |✔️ |🚧 (no extended-LUT7) |
| ├ LUTRAM | ❌ |❌ |✔️ |✔️ |❌ (N/A) |🚧 (no MLAB init) |
| └ ALU | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (no share chain) |
| IO buffer | ✔️ |✔️ |✔️ |✔️ |✔️ |🚧 |
| ├ IO standards | ✔️ |⚠️ |✔️ |🚧 |✔️ |❌ |
| └ DDR/SERDES | ❌ |❌ |✔️ |🚧 |✔️ |❌ |
| Block RAM | ❌ |❌ |✔️ |✔️ |✔️ |🚧 (no TDP, no 8x20 mode) |
| DSP | ❌ |❌ |✔️ |✔️ |✔️ (up5k only) |❌ |
| PLL | ❌ |❌ |✔️ |⚠️ |✔️ |❌ |
| Routing | ✔️ |✔️ |✔️ |✔️ |✔️ |⚠️ |
| ├ Local | ✔️ |✔️ |✔️ |✔️ |✔️ |⚠️ |
| ├ Global | ✔️ |🚧 |✔️ |✔️ |✔️ |⚠️ |
| └ Long wires | ❌ |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |❌ (N/A) |
| Timing | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |
| ├ Logic | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |
| ├ Routing | ✔️ |❌ |✔️ |✔️ |✔️ |🚧 (nominal delays only) |
| └ IO buffer | ✔️ |❌ |🚧 |🚧 |❌ |❌ |
| symbol | meaning |
|--------|--------------------------------------|