Fix dead clifford.at/yosys links

Migrating-from-Vivado.md

@@ -16,7 +16,7 @@ TODO
 TODO
 
 # Elaborated Design Schematic / RTL Schematic
-All you have to do is load your Verilog source files and run [``prep``](http://www.clifford.at/yosys/cmd_prep.html). Then, use [``show``](http://www.clifford.at/yosys/cmd_prep.html) to see parts that are of any interest to you. You probably also want to use ``-colors`` and ``-stretch`` flags to make the graph a bit more readable.
+All you have to do is load your Verilog source files and run [``prep``](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/prep.html). Then, use [``show``](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/show.html) to see parts that are of any interest to you. You probably also want to use ``-colors`` and ``-stretch`` flags to make the graph a bit more readable.
 
 Therefore, the command you want to use is:
 ```bash
@@ -28,7 +28,7 @@ You can also export this graph directly to SVG file:
 yosys -p 'prep; show -colors 42 -stretch -format svg -prefix mygraph show top' top.sv foo.sv bar.sv
 ```
 
-See also [Yosys AppNote 011: Interactive Design Investigation](http://www.clifford.at/yosys/files/yosys_appnote_011_design_investigation.pdf).
+See also [Yosys AppNote 011: Interactive Design Investigation](http://yosyshq.net/yosys/files/yosys_appnote_011_design_investigation.pdf).
 
 # Synthesized Design Schematic / Technology Schematic
 TODO