This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-09-02 02:57:40 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
ff785cdb46d6b1ddc19d5acc21b4d1236b3adf3f
yosys
/
techlibs
/
intel
/
max10
T
History
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
...
Fixes
#2058
.
2020-05-19 01:42:40 +02:00
..
cells_arith.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_sim.v
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00