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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
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f60b77a7f01ebffe57a5d74e2e7a42e0dbf449e3
yosys/passes
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History
Jannis Harder 04ecabdd1f Merge pull request #4222 from jix/pdr-X
write_aiger: Include `$assert` and `$assume` cells in -ywmap output
2024-03-05 15:13:51 +01:00
..
cmds
rename -witness: Bug fix and rename formal cells
2024-03-04 16:53:03 +01:00
equiv
equiv_simple: Take FFs into account for driver map
2024-02-21 12:05:52 +01:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 10:31:40 +01:00
memory
opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-23 12:27:53 +01:00
opt
opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-23 12:27:53 +01:00
pmgen
Address SigBit/SigSpec confusion issues under c++20
2024-02-08 17:48:36 +01:00
proc
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
2024-02-19 16:21:40 +01:00
sat
clk2fflogic: Fix handling of $check cells
2024-02-14 11:42:27 +01:00
techmap
Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc
2024-02-25 17:23:56 +01:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
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