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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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f5e357dbf6a8ff30ddfd93bf73bd2a9b95d28ed3
yosys/passes
T
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Emil J. Tywoniak f5e357dbf6 equiv_make: don't copy $input_port
2026-09-17 15:43:54 +02:00
..
cmds
connect: remove input ports on conflict
2026-09-17 15:43:54 +02:00
equiv
equiv_make: don't copy $input_port
2026-09-17 15:43:54 +02:00
fsm
opt_clean: move unused_bits analysis to kernel/unused_bits.h
2026-08-12 11:42:50 +02:00
hierarchy
hierarchy: tolerance for apparent recursive instances in techmap files
2026-09-17 15:43:54 +02:00
memory
memory: add -bram-register
2026-09-17 15:43:54 +02:00
opt
opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
2026-09-17 15:43:54 +02:00
pmgen
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
proc
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
sat
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
techmap
Revert "techmap: call hierarchy on map files to determine port directions"
2026-09-17 15:43:54 +02:00
tests
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
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