yosys/techlibs
Clifford Wolf 32dbf7752d Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v 2013-04-07 16:42:29 +02:00
..
.gitignore
Makefile.inc Added EXTRA_TARGETS Makefile variable 2013-03-28 16:53:40 +01:00
blackbox.sed
simlib.v Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v 2013-04-07 16:42:29 +02:00
stdcells.v Fixed stdcells.v for $adff with undef reset value 2013-03-24 10:43:05 +01:00
stdcells_sim.v