Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
d2c99efa2a24dfa7a28de1d7d01634ff9a2476ef
yosys/passes
T
History
Emil J. Tywoniak b632f6dc3d Revert "techmap: call hierarchy on map files to determine port directions"
This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.
2026-09-17 15:43:54 +02:00
..
cmds
connect: remove input ports on conflict
2026-09-17 15:43:54 +02:00
equiv
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
fsm
opt_clean: move unused_bits analysis to kernel/unused_bits.h
2026-08-12 11:42:50 +02:00
hierarchy
hierarchy: tolerance for apparent recursive instances in techmap files
2026-09-17 15:43:54 +02:00
memory
memory: add -bram-register
2026-09-17 15:43:54 +02:00
opt
opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
2026-09-17 15:43:54 +02:00
pmgen
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
proc
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
sat
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
techmap
Revert "techmap: call hierarchy on map files to determine port directions"
2026-09-17 15:43:54 +02:00
tests
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
Powered by Gitea Version: 1.27.2 Page: 1782ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API