mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-04 19:31:00 +02:00
Udi Finkelstein
536ae16c3a
meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
4 lines
42 B
Verilog
4 lines
42 B
Verilog
module a(input wire x = 1'b0);
|
|
endmodule
|
|
|