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Udi Finkelstein
536ae16c3a
meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
7 lines
64 B
Verilog
7 lines
64 B
Verilog
module a;
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wire [5:0]x;
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wire [3:0]y;
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assign y = x 55;
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endmodule
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