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cc7ad65a7992d82e758011ec63704b65fcb2d7d6
yosys
/
tests
/
errors
/
syntax_err08.v
T
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
module
a
;
wire
[
5
:
0
]
x
;
wire
[
3
:
0
]
y
;
assign
y
=
x
55
;
endmodule
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