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29 lines
611 B
Plaintext
29 lines
611 B
Plaintext
# -script +cmd,arg;cmd
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read_verilog <<EOT
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module top(input [7:0] a, b, output [7:0] y, output c);
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assign {c, y} = a + b;
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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design -save gold
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techmap
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opt
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logger -expect log "\+ &if -g -K 6" 1
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abc_new -liberty openroad/cm_test_cells.lib -script +&st;&if,-g,-K,6;&nf
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logger -check-expected
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select -assert-none t:$_*_
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check -assert
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read_verilog openroad/cells_sim.v
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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miter -equiv -flatten -make_assert gold gate miter
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sat -verify -prove-asserts -show-ports miter
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