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29 lines
664 B
Plaintext
29 lines
664 B
Plaintext
# -script file with comments and blank lines
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read_verilog <<EOT
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module top(input [7:0] a, b, input [2:0] s, output [7:0] y);
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assign y = (a << s) | (b >> s);
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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design -save gold
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techmap
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opt
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logger -expect log "source .*abc_new_delay4.abc" 1
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abc_new -liberty ../openroad/cm_test_cells.lib -script abc_new_delay4.abc
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logger -check-expected
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select -assert-none t:$_*_
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check -assert
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read_verilog ../openroad/cells_sim.v
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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miter -equiv -flatten -make_assert gold gate miter
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sat -verify -prove-asserts -show-ports miter
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