# -script file with comments and blank lines
read_verilog <<EOT
module top(input [7:0] a, b, input [2:0] s, output [7:0] y);
	assign y = (a << s) | (b >> s);
endmodule
EOT

hierarchy -top top
proc
opt
design -save gold

techmap
opt
logger -expect log "source .*abc_new_delay4.abc" 1
abc_new -liberty ../openroad/cm_test_cells.lib -script abc_new_delay4.abc
logger -check-expected
select -assert-none t:$_*_
check -assert

read_verilog ../openroad/cells_sim.v
flatten
opt_clean
design -stash gate
design -copy-from gold -as gold top
design -copy-from gate -as gate top
miter -equiv -flatten -make_assert gold gate miter
sat -verify -prove-asserts -show-ports miter