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35 lines
875 B
Plaintext
35 lines
875 B
Plaintext
# passthrough, port-to-port, constants, undef on outputs and cone inputs, duplicated bits, dangling logic, undriven inout
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read_verilog <<EOT
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module top(input [3:0] a, input b, unused, inout io, output [3:0] y0, y1, output z0, z1, z2, z3, z4, z5, output [1:0] w);
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assign y0 = a;
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assign y1 = y0;
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assign z0 = 1'b0;
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assign z1 = 1'b1;
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assign z2 = 1'bx;
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assign z3 = b;
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assign z4 = a[1] & 1'bx;
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assign z5 = b | 1'bx;
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assign w = {b, b};
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wire dangling = a[0] & b;
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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design -save gold
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techmap
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abc_new -liberty openroad/cm_test_cells.lib
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select -assert-none t:$_*_
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check -assert
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read_verilog openroad/cells_sim.v
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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miter -equiv -flatten -make_assert -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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