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36 lines
978 B
Plaintext
36 lines
978 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/2530
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# flop with async reset from its own output
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read_liberty -lib openroad/sm_test_cells.lib
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read_verilog <<EOT
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module top(input WBs_CLK_i, _1_, _0_, output reg Rx_overflow_detected_o);
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wire rx_fifo_cntr_rst;
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assign rx_fifo_cntr_rst = _1_ | Rx_overflow_detected_o;
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always @(posedge WBs_CLK_i, posedge rx_fifo_cntr_rst)
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if (rx_fifo_cntr_rst) Rx_overflow_detected_o <= 1'h0;
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else Rx_overflow_detected_o <= _0_;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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synth -run fine:
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dfflibmap -liberty openroad/sm_test_cells.lib
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select -assert-count 1 t:DFFR
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abc_new -liberty openroad/cm_test_cells.lib -liberty openroad/sm_test_cells.lib
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select -assert-none t:$_*_
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check -assert
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read_verilog openroad/cells_sim.v
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proc
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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async2sync
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equiv_make gold gate equiv
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equiv_simple -seq 5
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equiv_induct -seq 5
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equiv_status -assert
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