Emil J. Tywoniak f7d40cf1a8 WIP

2026-07-17 23:48:54 +02:00

..

.gitignore

analogdevices: Extra tests

2026-03-05 05:37:13 +00:00

add_sub.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

adffs.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

asym_ram_sdp_read_wider.v

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

asym_ram_sdp_write_wider.v

Add missing EOL

2026-03-06 09:10:55 +01:00

asym_ram_sdp.ys

End of file fix

2026-06-23 07:23:41 +02:00

attributes_test.ys

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

blockram.ys

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

bug1460.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

bug1462.ys

test suite

2026-03-05 05:37:12 +00:00

bug1480.ys

test suite

2026-03-05 05:37:12 +00:00

bug1598.ys

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

counter.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

dffs.ys

End of file fix

2026-06-23 07:23:41 +02:00

dsp_abc9.ys

WIP

2026-07-17 23:48:54 +02:00

fsm.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

generate_mk.py

Convert gen-tests shell script to python

2026-04-16 11:00:44 +02:00

logic.ys

Move rename logic to abc_ops_reintegrate

2026-06-19 10:46:47 +01:00

lutram.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

mem_gen.py

analogdevices: Extra tests

2026-03-05 05:37:13 +00:00

mul_unsigned.v

test suite

2026-03-05 05:37:12 +00:00

mul_unsigned.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00

mul.ys

analogdevices: DSP inference

2026-03-05 05:37:12 +00:00

mux.ys

Revert "Fix tests due to ABC improvements"

2026-05-11 14:47:08 +02:00

opt_lut_ins.ys

Update opt_lut_ins and stat for analogdevices and remove ecp5

2026-03-06 09:10:36 +01:00

shifter.ys

synth_analogdevices: update timing model and tests

2026-03-05 05:37:13 +00:00