Miodrag Milanovic 0a88f002e5 allow range for mux test

2020-06-01 13:48:19 +02:00

..

aiger

tests: aiger test for wire->start_offset != 0

2020-05-02 10:00:32 -07:00

arch

allow range for mux test

2020-06-01 13:48:19 +02:00

asicworld

…

bram

…

errors

…

fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

…

liberty

…

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

memory_dff: Fix checking of feedback mux input when more than one mux

2019-07-02 13:35:50 +01:00

opt

Merge pull request #1994 from YosysHQ/eddie/fix_bug1758

2020-05-14 11:56:22 -07:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

…

rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

…

simple

Expand tests/simple/constmuldivmod.v

2020-05-28 22:59:04 +02:00

simple_abc9

abc9: test to use box file instead of auto

2020-05-14 10:33:56 -07:00

smv

…

sva

…

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

svtypes

ast/simplify: don't bitblast async ROMs declared as logic.

2020-05-05 04:16:59 +00:00

techmap

tests: zinit for new types

2020-04-14 13:08:37 -07:00

tools

autotest.sh to define _AUTOTB when test_autotb

2019-06-28 14:56:22 -07:00

unit

…

various

printattrs: Add test.

2020-05-27 08:00:00 +00:00

verilog

test: add attribute-before-stmt test from @nakengelhardt

2020-05-25 07:36:53 -07:00

vloghtb

…