test: add attribute-before-stmt test from @nakengelhardt

tests/verilog/bug2037.ys

@@ -41,3 +41,18 @@ module test ();
 endmodule
 EOT
 select -assert-none a:*
+
+
+design -reset
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	reg x = 1'b0;
+	always @(*) begin
+		if (y)
+			(* foo *) x <= 1'b1;
+		else
+			(* bar *) x = 1'b0;
+	end
+endmodule
+EOT