nella 9e8f12b9b3 Merge pull request #6207 from YosysHQ/nella/xilinx-rdfirst-xc7 ...

xilinx: fix BRAM mapping for negedge port next to READ_FIRST port [sc-917]

2026-09-16 13:14:35 +00:00

..

aiger

Move rename logic to abc_ops_reintegrate

2026-06-19 10:46:47 +01:00

alumacc

Code cleanup

2026-08-04 17:18:22 +02:00

arch

xilinx: Drop READ_FIRST erratum on 7 series.

2026-09-16 09:14:50 +02:00

arith_tree

arith_tree: add regression tests for truncating narrow chain links

2026-08-21 10:38:58 +02:00

asicworld

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

blif

tests: rebless blif gatesi cell order

2026-09-10 18:16:57 +02:00

bram

Add initial codecov support

2026-07-10 12:19:59 +02:00

bugpoint

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

check_mem

tests/check_mem: Drop unused init check

2026-05-30 11:06:11 +12:00

cxxrtl

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

errors

End of file fix

2026-06-23 07:23:41 +02:00

fmt

Cleanup

2026-04-16 11:00:44 +02:00

fsm

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

functional

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

hana

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

liberty

Move scl cache args to libcache, fix -disable.

2026-08-17 12:37:49 +02:00

lut

Release version 0.69

2026-09-09 07:26:44 +02:00

memfile

Update CI scripts for CMake

2026-06-03 08:58:11 +00:00

memlib

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

memories

Fix OOB read.

2026-08-07 14:29:14 +02:00

opt

Separate non -sat constbits.

2026-08-27 23:10:40 +06:00

opt_share

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

peepopt

Converted some more

2026-04-16 11:00:44 +02:00

proc

Merge branch 'main' into nella/latch-toggle

2026-07-08 11:41:08 +02:00

pyosys

End of file fix

2026-06-23 07:23:41 +02:00

realmath

Cleanup

2026-04-16 11:00:44 +02:00

rpc

Make out of tree build testing possible

2026-05-19 14:26:07 +02:00

rtlil

Testcases for new truncation checks

2026-07-10 14:37:19 +02:00

sat

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

sdc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

select

Converted some more

2026-04-16 11:00:44 +02:00

share

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

sim

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

simple

End of file fix

2026-06-23 07:23:41 +02:00

simple_abc9

Convert autotest script wrapper

2026-04-16 11:00:44 +02:00

smv

End of file fix

2026-06-23 07:23:41 +02:00

sva

End of file fix

2026-06-23 07:23:41 +02:00

svinterfaces

Cleanup

2026-04-16 11:00:44 +02:00

svtypes

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

symfpu

Code cleanup

2026-08-04 17:18:22 +02:00

techmap

xaiger2: add testcase from #4349

2026-09-16 08:13:23 +01:00

tools

End of file fix

2026-06-23 07:23:41 +02:00

unit

log: create LogManager singleton and move implementation

2026-08-19 15:59:46 +02:00

various

Merge pull request #6201 from YosysHQ/nella/check-internal-celltypes

2026-09-15 11:52:15 +00:00

verific

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

verilog

Update tests to reflect change to <inlined>

2026-09-14 10:35:11 +02:00

vloghtb

End of file fix

2026-06-23 07:23:41 +02:00

write_verilog

tests: Add mixed_upto write_verilog test

2026-06-19 11:20:01 +12:00

xprop

Update CI scripts for CMake

2026-06-03 08:58:11 +00:00

.gitignore

Save results, and create summary and report

2026-04-16 11:00:44 +02:00

common.mk

Add VERBOSE (and V) option to Makefiles

2026-06-15 14:48:11 +02:00

gen_tests_makefile.py

Fix OOB read.

2026-08-07 14:29:14 +02:00

Makefile

rtlil: remove dead verilog bindings

2026-08-31 22:13:01 +02:00

pass-fuzzing.md

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00