mirror of https://github.com/YosysHQ/yosys.git
79e05a195d
This makes the Verilog backend handle the $connect and $input_port cells. This represents the undirected $connect cell using the `tran` primitive, so we also extend the frontend to support this. |
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| .. | ||
| Makefile.inc | ||
| ast.cc | ||
| ast.h | ||
| ast_binding.cc | ||
| ast_binding.h | ||
| dpicall.cc | ||
| genrtlil.cc | ||
| simplify.cc | ||