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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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89f32a415b2fcd9fdf08f735fae043fac9e1ab4a
yosys/frontends
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Emil J a80462f27f Merge pull request #5339 from rocallahan/fast-rtlil-parser
Rewrite the RTLIL parser for efficiency
2025-10-08 14:52:37 +02:00
..
aiger
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
aiger2
Remove .c_str() calls from log()/log_error()
2025-09-11 20:59:37 +00:00
ast
verilog: Bufnorm cell backend and frontend support
2025-09-17 14:01:09 +02:00
blif
Merge pull request #4125 from povik/read-blif-gate-ff
2025-09-29 08:21:16 -05:00
json
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
liberty
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
rpc
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
rtlil
Limit the maximum size of parsed RTLIL constants to 1 Gb.
2025-10-01 02:17:22 +00:00
verific
verific: print source location of problematic object on import error (if available)
2025-10-03 12:57:49 +02:00
verilog
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
2025-09-22 11:14:39 +02:00
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