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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
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7f7c61c9f018cd7ed24d8c7e570a80e565ca7c7b
yosys/docs/source
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Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
2023-08-11 04:46:52 +02:00
..
appendix
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APPNOTE_011_Design_Investigation
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CHAPTER_Prog
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bib.rst
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CHAPTER_Approach.rst
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CHAPTER_Basics.rst
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CHAPTER_CellLib.rst
fmt: remove lzero by lowering during Verilog parse
2023-08-11 04:46:52 +02:00
CHAPTER_Eval.rst
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CHAPTER_Intro.rst
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CHAPTER_Memorymap.rst
docs: reflow memory map
2023-06-19 12:05:51 +12:00
CHAPTER_Optimize.rst
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CHAPTER_Overview.rst
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CHAPTER_Prog.rst
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CHAPTER_Techmap.rst
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CHAPTER_Verilog.rst
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cmd_ref.rst
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conf.py
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index.rst
Initial version of memory mapping doc
2023-05-26 09:36:01 +12:00
literature.bib
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requirements.txt
…
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